Logic circuit and its fabrication method

A logic circuit (C1) having a first logic gate (L4-L9) and the remaining logic gate or gates (L1-L3). The first logic gate (L4-L9) is interposed in a signal path determining an operating speed, and includes at least one first MOS transistor (42) which has a threshold voltage lower than a predetermined voltage and operates at a high speed. The remaining logic gate or gates (L1-L3) include at least one of a second MOS transistor (22, 23) and a third MOS transistor (12) as a transistor having a margin for operating speed. The second MOS transistor (22, 23) has a middle threshold voltage equal to or greater than the predetermined voltage, and the third MOS transistor (12) has a high threshold voltage equal to or greater than the predetermined voltage. The power consumption of the entire logic circuit at the time of operation is reduced, while maintaining the maximum operating speed.