Semiconductor device with intermetal dielectric and method of making
19 claims: 8 independent, 11 dependent
- 1A semiconductor device (10) comprising;a first conductor (22) and a second conductor (24) disposed adjacent one another;an intermetal body (46) formed from a dielectric material and disposed between the first metal conductor and the second metal conductor, characterised in that the dielectric material is a polymeric material consisting of a mixture of perfluorinated poly (para-xylylene) and non-perfluorinated poly (para-xylylene).
- 2An intermetal dielectric material for integrated circuits consisting of a polymer mixture of perfluorinated poly (para-xylylene) and non-perfluorinated poly (para-xylylene).
- 3A method of forming an intermetal dielectric material for integrated circuits comprising:sublimating poly (para-xylylene) dimers (60) and dissociating then into reactive poly (para-xylylene) monomers (62);exposing the reactive poly (para-xylylene) monomers to a fluorinating agent;and depositing the resulting mixture of perfluorinated and non-perfluorinated reactive poly (para-xylylene) monomers (64) on a substrate to form a polymeric dielectric material consisting of a mixture of perfluorinated poly (para-xylylene) and non-perfluorinated poly (para-xylylene).
- 4The method of Claim 3, further comprising performing the depositing step at a low temperature.
- 8Apparatus for forming a dielectric material consisting of a mixture of perfluorinated poly (para-xylylene) and non-perfluorinated poly (para-xylylene) on a substrate (88) comprising:a poly (para-xylylene) dimer source a sublimation chamber (68), arranged for sublimating said poly (para-xylylene) diner source;a dissociation furnace (70) coupled to the output of the sublimation chamber, the dissociation furnace configured to dissociate the poly (para-xylylene) dimers to poly (para-xylylene) monomers;and a condensation chamber (82) coupled to the output of the furnace, the condensation chamber being configured to condense the poly (para-xylylene) monomers from the furnace output onto the substrate;characterised in that it further includes: a fluoride source (71,72) arranged for fluoridation of said poly (para-xylylene) monomers prior to condensing, such that a mixture of perfluorinated poly (para-xylylene) and non-perfluorinated poly (para-xylylene) is obtained.
- 9The apparatus of Claim 8:wherein the fluoride source is a solid fluoride source situated in the furnace.
- 10The apparatus of Claim 9, wherein the solid fluoride source comprises cobalt fluoride or potassium fluoride.
- 12The apparatus of Claim 11, wherein the gaseous fluoridating agent comprises hydrogen fluoride.
- 16A method of forming a semiconductor device comprising the steps of:forming on a substrate first (22) and second (24) conductive elements spaced apart one from the other;and depositing an intermetal dielectric material (46) between the first and second conductive elements consisting of a mixture of per-fluorinated poly (para-xylylene) and non-fluorinated poly (para-xylylene).
- 17The method of Claim 16, wherein the step of depositing the intermetal dielectric further comprises:sublimating a poly (para-xylylene) dimer vapor from a poly (para-xylylene) dimer source;heating the poly (para-xylylene) dimer vapor to disassociate the poly (para-xylylene) monomers within the poly (para-xylylene) dimer;introducing a fluoridating agent into the disassociated poly (para-xylylene) monomers;and condensing the mixture of the fluoridating agent and the disassociated poly (para-xylylene) monomers onto the surface between the first and second conductive elements to form said intermetal dielectric material (46).
- 18The method of Claim 17, wherein the step of introducing a fluoridating agent comprises the step of introducing a potassium fluoride source.
- 19The method of Claim 17, wherein the step of introducing a fluoridating agent comprises the step of introducing a hydrogen fluoride source.
Independent claims19
20 paragraphs in 5 sections, as filed
TECHNICAL FIELD OF THE INVENTION
0001This invention relates in general to the field of electronic devices and more particularly to semiconductor devices having an improved intermetal dielectric and method of formation.
BACKGROUND OF THE INVENTION
0002As the features sizes of ULSI technology continue to shrink, the intrinsic semiconductor gate performance improves through a higher drive current and lower junction capacitance. However, the interconnect RC time constant increases rapidly because the resistance of metal leads increases with decreasing line width and the interconnect capacitance increases with decreasing spacing between the lines. When minimum feature size is scaled below 0.3 micron, the interconnect delay becomes a major limiting factor of circuit performance.
0003The replacement of silicon dioxide as an intermetal dielectric with an insulator of lower dielectric constant is a particularly attractive solution since it provides immediate performance improvement through a reduction in capacitance. Prior techniques have used an imbedded polymer integration scheme to improve the interconnect performance through line-to-line capacitance reduction by using polymer only between tightly spaced lines. These gap-filled polymeric materials do not degrade the electromigration performance of standard multilayered titanium nitride and aluminum interconnects.
0004There are a variety of dielectric materials including pure polymer, spin-on glasses, and porous materials that offer lower values of permittivity than traditional silicon dioxide. One particularly useful polymer which exhibits extremely low permittivity values and yet exhibits thermal stability is fluorinated poly (para-xylylene), commonly referred to as fluorinated parylene or parylene-F. Parylene-F exhibits a dielectric constant on the order of 2.3. This is in comparison to a dielectric constant of on the order of 2.7 for non-fluorinated parylene, commonly referred to as parylene-N, and a dielectric constant of the order of 4.5 for undoped silicon dioxide. In the paper DABRAL S ET AL: 'AA'A"A" ' POLY-TERTRAFLUORO-P-XYLYLENE AS ANINTERLAYER DIELECTRIC FOR THIN FILM MULTICHIP MODULES AND INTEGRATED CIRCUITS' JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, vol. 11, no. 5, 1 September 1993, pages 1825-1832, XP000403660. The characteristics of these materials are individually analysed by disposition of each separately to a separate substrate for electrical and thermal characterization.
0005Each of documents US-A-3 332 891 and GB-1 146 005 discloses obtaining perfluorinated poly(para-xylylene) for semiconductor devices.
0006Although parylene-F performs as an excellent intermetal dielectric, it is extremely difficult to work with because of the difficulty in forming the precursor dimer AF4 which is the reactant needed to the formation of parylene-F. Methods of forming the necessary precursor dimer are extremely difficult to control and have correspondingly low yield rates. As such, the precursor dimer for parylene-F is not commercially available and the use of parylene-F as an intermetal dielectric is not commercially feasible.
SUMMARY OF THE INVENTION
0007Accordingly, a need has arisen for an improved intermetal dielectric which is commercially practical and provides for a low permittivity constant while remaining compatible with other processes within a semiconductor device formation.
0008According to the teachings of the present invention, an intermetal dielectric material is provided that substantially eliminates or reduces problems associated with prior materials and techniques of formation.
0009The invention is defined in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
0010A more complete understanding of the teachings of the present invention may be acquired by referring to the accompanying FIGUREs in which like reference numbers indicate like features and wherein: <ul id="ul0001" list-style="none"><li>FIGURE 1 is an enlarged cross-sectional schematic diagram of a portion of a semiconductor device constructed according to the teachings of the present invention;</li><li>FIGURE 2 is a diagram illustrating the chemical processes used to create the intermetal dielectric used in the structures and methods of the present invention; and</li><li>FIGURE 3 is a schematic illustration of a chemical vapor deposition system which may be used to construct the semiconductor devices according to the teachings of the present invention.</li></ul>
DETAILED DESCRIPTION OF THE INVENTION
0011Referring to FIGURE 1, a semiconductor structure indicated generally at 10 is shown which is formed on the outer surface of a semiconductor substrate 12 which may comprise any suitable semiconductor material such as silicon or gallium arsenide. Semiconductor structure 10 comprises a first level of conductive interconnects indicated generally at 14 and a second level of conductive interconnects indicated generally at 16. Level 14 and level 16 are interconnected by conductive vias represented by via 18 shown in FIGURE 1. Level 14 comprises a network of conductive elements represented by conductive elements 20, 22, 24 and 26. Each of the conductive elements 20, 22, 24 and 26 comprise a composite structure of metal and nitride. For example, conductive element 20 comprises a first level of titanium nitride 28. A layer of aluminum 30 is disposed outwardly from layer 28. Finally, an outer layer of titanium nitride 32 is disposed outwardly from layer 30. Each of conductive elements 20, 22, 24 and 26 are constructed of such a composite formation.
0012Similarly, layer 16 is comprised of a network of conductors represented by conductive elements 34, 36', and 38. Level 16 may be connected to other outer layers of conductors or devices by conductive via 40. Conductive elements 34, 36 and 38 are each comprised of composite structures similar to that described with reference to element 20 previously.
0013Level 14 is separated from level 16 and some elements within level 14 are separated from one another by a silicon dioxide layer 42. Similarly, level 16 is separated from layers formed outwardly from level 16 and certain of the elements within layer 16 or separated from one another by a second silicon dioxide layer 44.
0014According to the teachings of the present invention, conductive elements which are spaced apart by the minimum geometric spacing are not separated by silicon dioxide. For example, conductive elements 22 and 24 are spaced apart by an elongate polymer body 46 shown in FIGURE 1. Similarly, conductive elements 24 and 26 are spaced apart by an elongate polymer body 48. Finally, conductive elements 36 and 38 are spaced apart by an elongate polymer body 50. Polymer bodies 46, 48 and 50 comprise the intermetal dielectric materials, the formation of which will be described herein.
0015In general, bodies 46, 48 and 50 are formed of a mixture of perfluorinated and non-fluorinated parylene which exhibits a dielectric constant of the order of 2.3. This dielectric constant and the overall performance of the mixed polymeric material is comparable to a fluorinated parylene, commonly referred to as parylene-F. As will be described herein, the mixed polymer material is much easier to form and, as such, is a commercially feasible intermetal dielectric.
0016The polymer bodies 46, 48 and 50 and formed by a conformal deposition of the mixed polymeric material. This deposition process is followed by an etch-back process. These processes may result in the residual sidewall bodies shown in FIGURE 1 and exemplified by residual sidewall bodies 50 and 52 disposed outwardly from conductive elements 22 and 26 respectively.
0017FIGURE 2 is a diagram which illustrates the chemical processes that are used to form the mixed polymeric material used in the present invention. Referring to FIGURE 2, a conventional parylene-N, parylene-C or parylene-D dimer indicated at 60 is decomposed to create the reactive monomers indicated generally at 62. These reactive monomers are subjected to an environment which includes fluoride-carrying agents. These fluoride-carrying agents may comprise, for example, cobalt fluoride (CoF<sub>3</sub>), potassium fluoride (KF), or hydrogen fluoride (HF). When the monomers associate polymer in the flouride-rich environment, the resulting polymer is a mixture of per-fluorinated and non-fluorinated parylene. This mixture is indicated at 64 in FIGURE 2.
0018Referring to FIGURE 3, a processing system indicated generally at 66 is shown. System 66 is under vacuum base pressure of less than 10 millitor. System 66 comprises a dimer source 68 which is connected to a furnace 70. Furnace 70 also comprises a solid fluoride source 71, which introduces into furnace 70 a solid source of fluoride which may comprise, for example, cobalt fluoride or potassium fluoride. In the alternative, a gaseous fluoridating agent such as hydrogen fluoride may introduced from an HF source 72 through a valve 73 to a mix chamber 74. The dimer source 68 supplies the parylene-N, parylene-C or parylene-D dimer vapor by subliming the dimer by heating the dimer to on the order of 120° - 150°C. Furnace 70 is heated to the order of 500-580°C to disassociate the dimers and create the mixture of monomers and reactive fluoride compounds. This mixture is then passed to mixing chamber 74 through a valve 76. Other materials, such as dopants or other reactive or non-reactive agents may be supplied to the mix chamber 74 from a source 78 through a valve 80. As discussed previously, if a gaseous fluoride source such as HF source 72 is used, the mixing chamber 74 is used to fluoridate the reactive monomers.
0019The mixing chamber 74 is connected to a chamber 82. The entire system 66 is kept at a base pressure of less than 10 millitor. The pressure within chamber 82 increases during the deposition process but does not exceed 100 millitor. This pressure can be controlled by the temperature of dimer source 68 or by controlling the mass flow of the vapor entering the chamber 82. A chuck 83 within chamber 82 is capable of being temperature controlled between -80°C and 80°C. The chuck 83 inside the chamber 82 is cooled or heated to between -40° and 10°C to enable the monomers and fluoride to condense on the surface of a semiconductor wafer 88 placed on the chuck 83 within chamber 82.
0020The dimer source 68 provides an environment where the solid dimer can sublimate to a vapor state before being passed into furnace 70. The furnace 70 then disassociates the vapor dimer to the required reactive monomers. The fluoride source 72 then introduces the fluorinating agent into the furnace 70. The resulting reactive mixture is then condensed to form a mixture of per-fluorinated and non-fluorinated parylene on the outer surface of wafer 88 within CVD chamber 82. This mixed polymeric material exhibits a dielectric constant of the order of 2.3. It is thus comparable to the expensive and impractical parylene-F material. In addition, the mixed polymer intermetal dielectric of the present invention maintains good dimensional stability, high thermal stability, ease of pattern and etch for sub-micron features, low moisture absorption and permeation, good adhesion, low stress, good etch selectivity to metal, high thermal conductivity, high dielectric strength/low leakage current and good gap filling and planarization capability.
Contents5
2 sheets
Sheet 1 Sheet 2
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| GB1146005A | Cites | United Kingdom | Examiner |
| US3332891A | Cites | United States of America | Examiner |
| GB1146005A | Cites | United Kingdom | – |
| US3332891A | Cites | United States of America | – |
| DABRAL S ET AL: "A A' A'' A''' POLY-TERTRAFLUORO-P-XYLYLENE AS AN INTERLAYER DIELECTRIC FOR THIN FILM MULTICHIP MODULES AND INTEGRATED CIRCUITS" JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, vol. 11, no. 5, 1 September 1993, pages 1825-1832, XP000403660 | Non-patent | – | – |
8 members in 5 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 13892 | United States of America | – | |
| 1389296 | United States of America | P |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| KR970067387A | Republic of Korea | A | |
| EP0809291A2 | European Patent Office (EPO) | A2 | |
| JPH1041473A | Japan | A | |
| EP0809291A3 | European Patent Office (EPO) | A3 | |
| TW346660B | Taiwan Province of China | B | |
| EP0809291B1This record | European Patent Office (EPO) | B1 | |
| DE69737542D1 | Germany | D1 | |
| DE69737542T2 | Germany | T2 |
28 legal events, as 4 offices reported them to INPADOC
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Numbers
- Publication
- 0809291
- Application
- 971037288
Titles3
- German
- Halbleiterschaltung mit dielektrischer Schicht zwischen zwei Metallebenen und Verfahren zur Herstellung
- English
- Semiconductor device with intermetal dielectric and method of making
- French
- Dispositif semi-conducteur diélectrique entre deux couches de métallisation et procédé de fabrication
Classification
- CPC, 4
- H10W20/071
- H10W20/48
- H10W20/495
- H10W20/01
- IPC, 7
- H01L23 532
- H01L21 768
- C08L47 00
- H01B3 30
- H01L21 822
- H01L23 522
- H01L27 04
Designated states5
- Contracting states, 5
- Germany
- France
- United Kingdom
- Italy
- Netherlands (Kingdom of the)
