Method of manufacturing a thin semiconductor layer

p0001The present invention relates to a method of producing a thin layer of semiconductor material. Realized thin layer may optionally be provided with electronic components.

p0002The invention allows the production of thin layers of semiconductor monocrystalline as well as polycrystalline and amorphous and even for example the production of silicon type substrates On Insulator, achieving self-supporting thin layers of single-crystal semiconductor. Electronic circuits and / or microstructures can be achieved completely or in part in these layers or in these substrates.

p0003It is known that implanting ions of a rare gas or hydrogen in a semiconductor material induces the formation of microcavities to a depth close to the average penetration depth of the ions. The document<patcit id="pcit0001" dnum="FR2681472A"><text>FR-A-2681472</text></patcit> discloses a method which uses this property to obtain a thin film of semiconductor material. This method comprises subjecting a wafer of the desired semiconductor material and having a flat face with the following steps:<ul><li>a first stage of implantation by bombardment of the planar face of the wafer by means of ions creating, in the volume of the wafer and to a depth close to the depth of penetration of ions, a layer of microcavities separating the wafer into a lower region constituting the mass of the substrate and an upper region constituting the thin film, the ions being chosen among ions of rare gases or of hydrogen gas and the wafer temperature is maintained below the temperature at which the implanted ions can escape from the semiconductor by diffusion;</li><li>a second intimate contact step of the planar face of the wafer with a support consisting of at least one rigid material layer. This intimate contact may be achieved for example using an adhesive or by the effect of a prior preparation of the surfaces and optionally a thermal and / or electrostatic treatment to favor interatomic bonds between the support and the wafer;</li><li>a third heat treatment step of the wafer assembly and support at a temperature higher than the temperature for which the implantation was carried out and sufficient to create a crystalline rearrangement effect in the wafer and pressure microcavities a separation between the film thin and the substrate mass. This temperature is for example 500 ° C for silicon.</li></ul>

p0004This implementation is suitable for creating a layer of gaseous microbubbles. This layer thus created microbubbles in the volume of the wafer at a depth close to the average penetration depth of ions, delimits the volume of the wafer two regions separated by this layer: a region intended to form the thin film and a region forming the remainder of the substrate.

p0005Following the implantation conditions, after implantation of a gas such as hydrogen, cavities or microbubbles are observable or not in transmission electron microscopy. In the case of silicon, there may be microcavities whose size can vary from a few nm to a few hundred nm. Thus, in particular when the implantation temperature is low, these cavities can only be observed that during the heat treatment step, in which step is then carried nucleation to allow to reach the end of heat treatment to the coalescence of the microcavities.

p0006The method disclosed in <patcit id="pcit0002" dnum="FR2681472A"><text>FR-A-2681472</text></patcit> does not allow to produce electronic circuits in and on the surface of the planar face of the wafer after the ion implantation step. In fact, the realization of such circuits involves perform certain common operations microelectronics (diffusion annealing, deposition, etc.) that require additional steps of heat treatment (typically 400 ° C to 700 ° C) according to the steps for silicon. However, at these temperatures, forms blisters on the surface of the planar face of the implanted wafer. For example, for an implantation of hydrogen ions at a dose of 5.10¹⁶ protons / cm² and 100 keV into a silicon wafer, a heat treatment performed at 500 ° C for 30 min led to a degradation of 50% of the surface of the planar face of the wafer, degradation resulting from the appearance of and blisters burst. It is then no longer possible to properly ensure the intimate contacting the planar face of the wafer with the carrier (which will be called applicator in the following description) to peel off the semiconductor layer from the rest of the wafer.

p0007This phenomenon of formation of blisters and craters in the surface of a silicon wafer implanted with hydrogen ions after annealing has been discussed in the article "<nplcit id="ncit0001" npl-type="s"><text>Investigation of the bubble formation mechanism in a-Si: H film by Fourier-transform infrared microspectroscopy "Y. Mishima and T. Yagishita, published in J. Appl.Phys 64 (8), October 15, 1988, pages 3972-3974.</text></nplcit>.

p0008The present invention was designed to improve the method disclosed in <patcit id="pcit0003" dnum="FR2681472A"><text>FR-A-2681472</text></patcit>. It allows, after an ion implantation step in a range of appropriate doses and before the separation step, performing a heat treatment of the portion of the wafer corresponding to the future thin layer, in particular between 400 ° C and 700 ° C for silicon, without degrading the surface condition of the flat face of the wafer and without separation of the thin layer. This intermediate heat treatment may be part of the development operations of electronic components or be imposed for other reasons.

p0009The invention also applies to the case where the thickness of the thin layer is sufficient to impart good mechanical strength, in which case it is not necessary to use an applicator to obtain separation of the thin layer from the remainder of the wafer, but where it is desired nonetheless avoiding surface defects in the flat face.

p0010The invention therefore relates to a method of producing a thin layer of semiconductor material from a wafer of said material having a plane face, comprising an ionic implantation step consisting in bombarding said plane face with ions selected from the ions of rare gases or hydrogen, according to a determined temperature and a determined dose to create, in said plane reference plane and located at a depth close to the average penetration depth of ions, microcavities, the method further comprising a subsequent heat treatment step at a temperature sufficient to obtain a separation of the wafer into two parts, on either side of said reference plane, the portion situated on the side of the plane face constituting the thin layer, characterized in that:<ul><li>the ionic implantation step is conducted with a dose of ions between a minimum dose and a maximum dose, the minimum dose being that from which there will be a sufficient creation of microcavities to obtain the embrittlement of the next wafer the reference plane, the maximum dose, or critical dose, being that above which, during the heat treating step, there is separation of the wafer,</li><li>a step of separating the wafer into two parts, on either side of the reference plane is provided after or during the heat treatment step, this separation step comprising the application of mechanical forces between the two parts of the wafer.</li></ul>

p0011These mechanical forces may be tensile, shear and bending applied alone or in combination.

p0012We hear in the application by microcavities, cavities can be in any form; for example, the cavities may be of flattened shape, that is to say of low height (a few interatomic distances) or of substantially spherical shape or other different shape. These cavities may contain a free gaseous phase and / or gas atoms from the implanted ions attached to atoms of the material forming the walls of the cavities. These cavities are generally known in English terminology "platelets", "microblisters" or even "bubbles".

p0013The heat treatment carried out for obtaining the separation of the thin layer from the remainder of the wafer, makes it possible to bring the micro-cavities in a stable state. Indeed, under the effect of temperature, microcavities coalesce to reach a final statement. The temperature is therefore chosen so as to obtain this condition.

p0014According to the document <patcit id="pcit0004" dnum="FR2681472A"><text>FR-A-2681472</text></patcit>, The implanted dose is such which is obtained under the effect of heat treatment, a layer of microcavities which allows to obtain directly the separation.

p0015According to the present invention, the implanted dose is insufficient to obtain during the heat treatment a separation, the implanted doses only allow embrittlement of the wafer at the reference plane, the separation requires an extra step by application of mechanical forces. In addition, the critical dose as defined in the invention is less than the dose at which the course of ion implantation steps and heat treatment, there are blisters on the flat surface of the wafer. The blistering problem does not therefore arise in the invention.

p0016The method according to the invention may comprise, between the heat treatment step and the separating step, a step of performing at least all or part of an electronic component in the portion of the wafer to constitute the thin layer.

p0017If the realization of this electronic component requires heat treatment phases, the latter are preferably conducted at a temperature lower than the heat treatment.

p0018If necessary just before the separating step, there is provided a further step of intimately contacting and securing the said plate, on the side of said flat surface, with a support through which mechanical forces such as tensile forces and / or shear will be applied.

p0019This support can be a flexible support, such as a Kapton sheet^®. It may be a rigid support such as a silicon wafer oxidized.

p0020The invention will be better understood and other advantages and features will appear on reading the following description given by way of example, in which:<ul><li>the <figref idrefs="f0001">figure 1</figref> represents, schematically, a wafer of semiconductor material of which one side thereof is subjected to ion bombardment by applying the method of the present invention,</li><li>the <figref idrefs="f0001">2</figref> represents, schematically, the previous wafer after the heat treatment step for coalescing the micro-cavities, according to the present invention,</li><li>the <figref idrefs="f0002">3</figref> represents, schematically, the previous wafer after formation of electronic components in the portion corresponding to the desired thin layer,</li><li>the <figref idrefs="f0002">4</figref> represents, schematically, the separation step of the previous wafer into two parts, in accordance with the present invention.</li></ul>

p0021An important point of the present invention is the hydrogen ion implantation, or a rare gas, in a lower dose or equal to the dose above which there would separation during thermal processing. The dose used is such that it allows a weakening of the material to a depth Rp corresponding to the average path of the ions in the material, but the board remains mechanically strong enough to withstand all thermal processing steps necessary for the implementation of electronic circuits. In other words, the wafer implanted present in the microcavity area, solid bridges connecting the part of the plate intended to form the thin layer on the remaining portion of the wafer.

p0022The description will now focus on the realization of a thin layer of semiconductor material from a thick substrate having a flat face. The starting substrate can be coated or not on this plane face of one or more layers of materials, such as encapsulant materials such as a dielectric.

p0023The <figref idrefs="f0001">figure 1</figref> illustrates the ion implantation step of a wafer 1 of semiconductor material. The flat face 2 of the wafer receives ion bombardment which is represented by arrows. In the case where the flat face 2 of the wafer is covered with one or more non-semiconductor materials, the ion energy is chosen to be sufficient so that they penetrate into the bulk of semiconductor material.

p0024Where appropriate, the thickness of implanted semiconductor material must be such that one can achieve all or some of electronic components and / or microstructures in the thin layer. For example the average penetration of the hydrogen ions is 2 .mu.m to 200 keV in silicon.

p0025Ion implantation of these types of ions in the semiconductor substrate formed in depth in the vicinity of the depth corresponding to Rp medium path of the ions along a perpendicular to the plane face, an area 3 with high atom concentration giving rise to microcavities. For example, the maximum hydrogen concentration is 10²¹ H⁺/ cm³ for an implantation dose of 2.10¹⁶ H⁺/ cm² 100 keV. This ion implantation step must be performed at a temperature such that the implanted gas ions do not diffuse the As (during the implantation step) at long range. This would disrupt or completely rule out the formation of microcavities. For example, in the case of hydrogen ion implantation in silicon ion implantation will be realized at a temperature below 350 ° C.

p0026The implantation dose (number of ions per unit area received during the period of implantation) is selected so that the dose is less than or equal to one dose, said critical dose, such that, above this critical dose, during the subsequent heat treatment step, there is separation of the thin layer from the remainder of the wafer. In the case of hydrogen ion implantation, the critical dose is of the order of 4.10¹⁶ H⁺/ cm² for an energy of 160 keV.

p0027The implantation dose is also chosen to be above a minimum dose at which, during the subsequent heat treatment step, the formation of microcavities and the interaction therebetween is sufficient, that is to say it helps to weaken the implanted material in the microcavity zone 3. This means that there are still strong bridges of semiconductor material between the microcavities. In the case of a hydrogen gas ion implantation into a silicon substrate, the minimum dose is of the order of 1.10¹⁶/ cm² at an energy of 100 kev.

p0028The next step of the method according to the invention consists of a heat treatment of the wafer at a temperature sufficient to allow coalescence of the microcavities after the reference plane. In the case of implantation, at a temperature below 350 ° C, of ​​ions of hydrogen gas in a silicon substrate and a dose of 3.10¹⁶ H⁺/ cm² at an energy of 100 keV, after a heat treatment for thirty minutes at 550 ° C, is observed by electron microscopy in transmission in section, of the height of cavities equal to fractions of nanometers and several extension along the reference plane nanometers or even several tens of nanometers. This heat treatment allows both the precipitation and stabilization of gas atoms implanted in the form of microcavities.

p0029Microcavities 4 (see <figref idrefs="f0001">2</figref>) Occupy, depending on the reference plane, a surface area substantially equal to the implanted surface. The cavities 4 are not located exactly in the same plane. They are located in planes parallel to the reference plane to a few nanometers or tens of nanometers to this reference plane. Therefore, the upper portion of the substrate located between the reference plane and the plane surface 2 is not completely separated from the mass of the substrate, the substrate mass being defined as the remainder of the substrate between the reference plane and the faces of the substrate other than the flat face. The remaining bonds are strong enough to withstand handling steps and annealing due to technological steps in the realization of integrated circuits. However, the connection between the upper portion and the mass of the substrate is weakened since this connection is carried out only through semiconductor material bridges between the cavities.

p0030then carry on the plane face can one 2 (surface and subsurface) or all of the electronic components, circuits and microstructures.

p0031The ion implantation energy of the hydrogen ions or rare gas of the first step was chosen so that the depth of the microcavity zone is sufficient for it is not disturbed by the production of components, electronic circuits and / or microstructures during this step. In addition, all thermal annealing operations that requires the development of integrated circuits, electronic circuits or microcircuits is selected so as to minimize any diffusion of the implanted ions. For example, in the case of a monocrystalline silicon wafer, preferably it will limit the maximum temperature of the various steps to 900 ° C.

p0032The <figref idrefs="f0002">3</figref> illustrates the case where one has developed several electronic components, referenced 5, on the planar face 2 and in the part of the plate intended to constitute the thin layer.

p0033The separation step is next. It consists of applying mechanical forces, for example traction, separating between the parts of the wafer or substrate located on either side of the reference plane so as to fracture the remaining solid bridges. This operation allows to obtain the thin layer of semiconductor material, equipped with electronic components in the case described. The<figref idrefs="f0002">4</figref> illustrates this separation step in which the thin layer 6 is separated from the remaining mass of the substrate 7 by the action forces exerting their actions in opposite directions and figured by arrows.

p0034Experience shows that the tensile force required to separate the upper part of the mass of the substrate is low particularly when one exerts a shear force between the upper part and the mass of the substrate, that is, say when the forces exerted have a component in the reference plane. This is simply due to the fact that the shear stress promotes the propagation of fractures and cavities in the reference plane.

p0035The upper substrate is thin by nature, tensile stress and / or shear can not, in many cases, be conveniently applied directly thereon. It is preferable, before the separation step, to make the wafer integral, by its flat face 2 of a carrier or applicator through which the mechanical forces will be applied to the upper part of the wafer. This applicator is shown under reference 8 to the<figref idrefs="f0002">4</figref>.

p0036The applicator can be a rigid or flexible media. here means securing the applicator on the board any paste operation or surface preparation and contacting, to ensure a sufficient energy link between the applicator and the flat side of the plate to resist the pulling operation and / or shear and / or bending of the separating step.

p0037The applicator may for example be a sheet of plastic material such as Kapton^® which was made adherent to the planar face of the substrate. In this example, after applying the process according to the invention there is provided a thin layer of monocrystalline semiconductor on Kapton sheet^®.

p0038In order to properly transmit the forces to the entire upper thin film circuits made in and on the surface of the upper layer may have been covered with a planarizing optionally protective layer during the developing step electronic components. The applicator is then secured to the upper thin film of the wafer through this protective layer.

p0039The applicator may also be a rigid support, for example a silicon wafer, the surface may be covered with a dielectric layer. Is carried out for example a suitable physico-chemical treatment of the planar face of the wafer and / or the surface of the applicator (unsubstituted or a dielectric layer) for contacting associated with a possible heat treatment secures the face plane of the wafer and the applicator.

p0040In the case cited as an example where the applicator is a silicon wafer carrying on its surface an oxide layer and wherein the semiconductor substrate is a monocrystalline silicon wafer, after application of the method according to the invention, one obtains a silicon on insulator wafer wherein the surface silicon layer is the thin layer provided by the upper substrate.

p0041Additionally, after separation of the thin layer from the remainder of the plate, the free surface of this layer can allow the transfer of a further substrate can be fitted with electronic components produced completely or partially on the substrate. Such a stack assembly allows a "three-dimensional" electronic circuits, the stiffener may or may not include itself electronic components.