Control method and apparatus for a production line

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to control method and apparatus of a line and a line system, in which, for example, a work is processed and is sequentially transported to downstream steps, thereby processing the work.

Related Background Art

A construction of a conventional manufacturing line system will now be described with reference to Fig. 18.

A processing device unit 111 and a transport device unit 112 of a station 101 are managed by a first line controller PLC1. Similarly, a processing device unit 121 and a transport device unit 122 of a station 102 are managed by a second line controller PLC2 and a processing device unit 131 and a transport device unit 132 of a station 103 are managed by a third line controller PLC3. The first, second, and third line controllers PLC1, PLC2, and PLC3 are connected to a host computer 150 through corresponding lines of communication lines K1 to K3, respectively. The host computer 150 collects and manages tracking data and quality data of each work at certain timings through the first, second, and third line controllers PLC1, PLC2, and PLC3, respectively. The host computer 150 supplies the tracking data of the works to the respective equipment via the first, second, and third line controllers PLC1, PLC2, and PLC3 in accordance with a transporting state of the work, respectively.

In such a conventional system construction, when the number of devices and equipment to be managed increases, a higher processing ability is required for the host computer 150. A frequency of communication which is executed between the host computer 150 and each line controller also increases. Moreover, when a cycle time of each step per work is short, it is very difficult to unitarily manage by the host computer 150. Since a collection of the tracking data, a start of working of the equipment, and completion signals are concentrated to the host computer 150, in order to preferentially transmit information, a dedicated line or the like is necessary between the host computer 150 and each line controller and processes in association with them are also fairly troublesome.

The EP-A-0 156 921 relates to a numerical control equipment which is provided with a single main processor and a plurality of sub-processors. In order to improve control speed and accuracy, means are proposed which allow direct data transmission and reception between the sub-processors as well as the data transmission and reception between the main processor and the sub-processors. When the necessity arises that CPUs of the processors read out data from or write data in the RAM of the processor of the counterpart, they issue requests for use of a system bus to a bus arbiter via bus control circuits and request-for-use-of-bus lines. The CPU of the processor which has received a permission-for-use-of-bus signal from the bus arbiter reads data from or writes data in the RAM of the counterpart via the system bus and the bus switching circuit of the counterpart.

<u>SUMMARY OF THE INVENTION</u>

It is an object of the present invention to provide a synchronization of control units connected to processing devices at reduced communication requirements.

According to a first aspect of the present invention, this object is achieved by a line system according to claim 1. According to a second aspect of the present invention, the above-mentioned object is achieved by a line control apparatus according to claim 13. According to a third aspect of the present invention, the above-mentioned object is achieved by a line control method according to claim 15.

The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1 is a block diagram showing a construction of a manufacturing line system according to a first embodiment of the invention;</li><li>Fig. 2 is a block diagram showing a construction of a control unit which is used in a network according to the first embodiment;</li><li>Figs. 3A and 3B are diagrams showing data structures in a common memory, in which Fig. 3A shows an area to store the data on a bit unit basis and Fig. 3B shows an area to store the data on a word unit basis;</li><li>Fig. 4 is a diagram for explaining link bit information which is managed by a control unit (PLC) 4-1 according to the first embodiment;</li><li>Fig. 5 is a diagram for explaining link word information which is managed by the control unit (PLC) 4-1 according to the first embodiment;</li><li>Fig. 6 is a diagram for explaining link bit information which is managed by a control unit (PLC) 4-2 according to the first embodiment;</li><li>Fig. 7 is a diagram for explaining link word information which is managed by the control unit (PLC) 4-2 according to the first embodiment;</li><li>Fig. 8 is a diagram for explaining link bit information which is managed by a line controller according to the first embodiment;</li><li>Fig. 9 is a diagram showing a refreshing process of the data in the common memory;</li><li>Fig. 10 is a timing chart for explaining transmission and reception of data between the control unit and the line controller according to the first embodiment;</li><li>Figs. 11A, 11B and 11C are diagrams for explaining a transportation of a board between the control units 4-1 and 4-2 according to the first embodiment;</li><li>Fig. 12 is a flowchart showing processes in the control unit 4-1 according to the first embodiment;</li><li>Fig. 13 is a flowchart showing processes in the control unit 4-2 according to the first embodiment;</li><li>Fig. 14 is a flowchart showing processes in the line controller according to the first embodiment;</li><li>Fig. 15 is a block diagram showing a construction of a manufacturing line system according to a second embodiment of the invention;</li><li>Fig. 16 is a diagram for explaining ID tag information according to the second embodiment;</li><li>Fig. 17 is a flowchart showing processes in the control unit 4-1 according to the second embodiment; and</li><li>Fig. 18 is a schematic diagram showing a construction of a conventional manufacturing line system.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention will now be described in detail hereinbelow with reference to the drawings. In the embodiments, a tracking control method in a manufacturing line will be described.

Fig. 1 is a block diagram showing a construction of a manufacturing line system according to the first embodiment of the invention.

In the manufacturing line system of Fig. 1, a line controller 1 and station control units (PLC) 4 (4-1, 4-2, ..., 4-n) are connected by a sequencer network 3. Reference numeral 2 denotes a storage device such as a hard disk or the like connected to the line controller 1. Each station 10 (10-1, 10-2, ..., 10-n) has a processing device (5-1, 5-2, ..., 5-n) for processing a work, a transport device 6 (6-1, 6-2, ..., 6-n) to transport the work to the next station, and the like.

The sequencer network 3 is based on a common memory system of a ring type which is frequently used hitherto. The sequencer network 3 can write data from each station control unit 4 connected to the network 3 into a specified area in a common memory of its own control unit, can read all areas in the common memories of the other control units, and can write and read data into/from the specified area in the common memory of each control unit even by the line controller 1 serving as a parent station. As a network 3, a bus type connection network can be also used so long as it is based on a common memory system.

Fig. 2 is a block diagram showing a construction of the control unit 4 according to the first embodiment. It is assumed that the control units 4-1 to 4-n in Fig. 1 have the same construction.

In Fig. 2, reference numeral 201 denotes a CPU such as a microprocessor or the like to control the whole control unit 4 and 202 indicates a program memory in which a control program that is executed by the CPU 201 has been stored. The program memory 202 is ordinarily constructed of an ROM. Reference numeral 203 denotes an RAM having a common memory area 204 which is used as a work area to store various data at the time of execution of various controls by the CPU 201 and can be also accessed from the other control units through the network 3 and a line interface (I/F unit) 206. Reference numeral 205 denotes an input/output interface unit (I/O•I/F). The processing device 5 and transport device 6 are connected through the I/O•I/F 205 and their operations are controlled by the CPU 201. Reference numeral 207 denotes an operation panel. Various key switches which are operated by the operator, an LED, a display, and the like are arranged on the operation panel 207. Reference numeral 208 denotes a sensor which is connected to the control unit 4 through the I/O•I/F 205 and detects a position and a state of the work in the processing device 5 and transport device 6 and generates a corresponding signal. The sensor 208 includes a positioning and delivery sensor 902 of a board and an acceptance sensor 903, which will be explained hereinlater. The processing device 5 has a buffer for receiving and temporarily holding the work from the transport device 6 and for temporarily holding the processed work before it is delivered to the transport device 6. The foregoing component elements are connected to a bus 200. In the above construction, although the CPU 201, program memory 202, and RAM 203 are connected to the bus 200, they can be also constructed as a one-chip IC.

As a common memory area (hereinafter, referred to as a "common memory") 204, each station control unit 4 connected to the network 3 has an area for storing data on a word (16 bits) unit basis and an area for storing the data on a bit (1 bit) unit basis in order to transmit and receive information to/from the other station control units. Each control unit further has an internal register to store and hold tracking data.

A data structure in the common memory 204 will now be described in detail. Figs. 3A and 3B show the data structures in the common memory 204. Fig. 3A shows the area (hereinafter, referred to as a "bit map") to store the data on a bit unit basis. Fig. 3B shows the area (hereinafter, referred to as a "word map") to store the data on a word unit basis.

Each of the bit map and the word map stores each information of the control units 4-1 to 4-n serving as child stations and information which is transmitted from the line controller 1 serving as a parent station to each of the control units 4-1 to 4-n. The line controller 1 and control units 4-1 to 4-n have the common memories 204 in which the common data has been stored. Therefore, the data formats on the common memories 204 in the line controller 1 and control units 4-1 to 4-n are the same and an address of each data is shifted in the same memory space by an amount of an address corresponding to a base address and is allocated every station. A specific example of the data stored will now be described.

Figs. 4 and 5 are diagrams showing specific data structures of the control unit 4-1 of the common memory 204 according to the first embodiment. Fig. 4 shows the data structure of link bit information in which data has been stored on a bit unit basis. Fig. 5 shows the data structure of link word information in which data has been stored on a word unit basis.

In the control unit 4-1, base addresses ("WOOOH" and "BOOOH") are allocated as shown in Figs. 4 and 5. "H" indicates a hexadecimal number.

For example, as shown in Fig. 4, in the control unit 4-1, "auto" in operation panel information is set to the third bit from address "BOOOH" in the common memory 204 and an address of "auto" is set to "B003H". As shown in Fig. 5, "delivery board ID" of the link word information is stored in addresses "W000H" to "W003H" in the common memory 204.

Figs. 6 and 7 are diagrams showing the data structure of the control unit 4-2 in the common memory 204. In the control unit 4-2, a base address in the data area of the word unit is set to "W030H" and a base address in the bit unit area is allocated to "B050H", so that it will be understood that their data structures are quite the same.

Further, Fig. 8 is a diagram showing a construction of a data area of a bit unit for the control unit 4-1 of the line controller (parent station) 1 in the common memory 204.

When referring to a data format of Fig. 8, a base address is set to "B400H".

The refreshing operation of the data in the common memory 204 mentioned above will now be described with reference to Fig. 9.

Each common memory 204 has a data memory storing area 204a and a link area storing area 204b and those areas have the same data structures as those shown in Figs. 3A and 3B. The data memory storing area 204a is a storing area of data for use in operation control in each station. The link area storing area 204b is provided to make the contents in the data memory storing area 204a of each control unit coincide without exerting an influence on each operation control.

In child stations, namely, in the control units 4-1 to 4-n, when there is a change in a state in each station, portions in the relevant addresses of the corresponding self control unit are rewritten in the data memory storing area 204a. When considering the control unit 4-1, in the data regarding the changed state in the station 10-1, the portions in the relevant addresses of B000H to B04FH regarding the control unit 4-1 are rewritten.

The data memory storing area 204a is refreshed as follows. First, the data stored in the link area storing area 204b is transmitted to the data memory storing area 204a and the data on the data memory storing area 204a side excluding the data about the self control unit 4 is overwritten. That is, in the control unit 4-1, the data in the data memory storing area 204a is overwritten by the data stored in the link area storing area 204b excluding the portions of B000H to B04FH regarding the control unit 4-1. On the other hand, with respect to the portions of B000H to B04FH regarding the control unit 4-1, the data stored on the link area storing area 204b is overwritten by the data in the data memory storing area 204a. When the processes for all addresses are finished, the data in the data memory storing area 204a is refreshed. After that, the refreshed data is returned to the link area storing area 204b and the data in the data memory storing area 204a and the data in the link area storing area 204b coincide.

Although the above description has been made for the control unit 4 of the child station, the above processes are also similarly performed with respect to the data refreshing operation in the line controller 1 serving as a parent station.

The above description has been made with respect to the refreshing operation of the data in one common memory 204. A data refreshing process between the control units will now be described.

First, the line controller 1 reads out the data regarding each control unit 4 from the control unit 4. Specifically speaking, the line controller 1 reads out the data from each link area storing area 204b. The data in the link area storing area 204b of the line controller 1 is rewritten by the read-out data.

The rewritten data in the link area storing area 204b of the line controller 1 is transmitted to the control units 4-1 to 4-n serving as child stations. The data in the link area storing area 204b in each of the control units 4-1 to 4-n is rewritten, so that the data in the line controller 1 and the data in the common memories 204 in the control units 4-1 to 4-n are held to the same contents. Therefore, since each control unit 4 can know the states of the other stations by the own common memory 204, there is no need to transmit and receive data between the control units at the time of each operation control.

In the above example, the contents in the memories provided for all control units which are connected to the line are shared by all of the control units. However, if the work can be processed by the data of only the processing devices arranged before and after on the line, as for the control units with such a relation, it is sufficient to share the data possessed by the control units arranged before and after.

A procedure for the signal transmission and reception between the control units using the link information as mentioned above will now be described with reference to a timing chart of Fig. 10 and diagrams of Figs. 11A to 11C showing the movement of a board 901 between the control units 4-1 and 4-2.

First, at the beginning of the sequence, quality data and peculiar data of the board are outputted to the network 3 and are stored into predetermined addresses in the common memory 204 which is managed by each control unit. Namely, information regarding a board quality (temperature and humidity etc. in processing) which is processed by the processing device 5 and is sequentially transported to the next station by the transport device 6 is stored into, for example, an area of 12 words in a range from address "WOOAH" to address "W015H" in the control unit 4-1. ID information such as a board number or the like is stored into four words from address "W00H". Further, bit information indicative of the kind (product, monitor, dummy, between lots, etc.) of board is stored into an area from address "B030H" to "B035H". Similarly, even in the other control units, those data is stored from the base address corresponding to each unit of the common memory 204.

As shown in Fig. 11A, in a state in which the board 901 exists in the station which is managed by the control unit 4-1, the control unit 4-2 sets a "transportable" signal (address "B070H") indicating that the board 901 can be received at timing T1 shown in Fig. 10. The control unit 4-1 writes sampling data of the board 901 under processing in the processing device 5-1 into addresses (W012H to W015H) in the common memory 204 any time and finishes the processing in the processing device 5-1. In a state in which the board 901 can be delivered, the board ID of the board 901 is written into W000H to W003H, sheet processing quality information is written into W00AH to W011H, and further, the board kind information is set into B030H to B035H. After that, a transporting motor for delivery and the like of the transport device 6-1 is driven, thereby starting the delivery of the board 901.

As shown in Fig. 11B, when the board 901 is not detected by the positioning and delivery sensor 902 of the board and the completion of the delivery of the board 901 is detected, the control unit 4-1 sets a "delivery" signal (bit in address "B011H") of the apparatus state/board transfer and reception at timing T2, thereby informing of a fact that the delivery of the board 901 is completed.

The line controller 1 collects the data at a preset sampling time from the control units 4-1 to 4-n. For example, if the sampling time is set to one minute, after the board 901 entered the processing device 5-1 which is managed by the control unit 4-1 for the first time, the line controller 1 samples the data in one minute.

The line controller 1 fetches the board ID (W00H to W003H), processing quality information (W00AH to W014H), and board kind information (B030H to B035H) at a timing when the "delivery" signal of the control unit 4-1 is set and sets a "reading-completion" signal (bit in address "B411H") at a time point corresponding to the completion of the collection of those data (timing T3).

At next timing T4, when the acceptance of the board 901 by the acceptance sensor 903 (state of Fig. 11C) is detected, the control unit 4-2 fetches the board ID (W00H to W003H) and board kind information (B030H to B035H). After that, the "acceptance" signal (bit in address "B061H" is set, thereby informing the control unit 4-1 of a fact that the transportation has been completed. Timing T5 now follows and when the "acceptance" signal from the control unit 4-2 is set and it is confirmed that the reading operation of the line controller 1 has been completed, namely, when it is confirmed that the transportation of the board 901 and the fetching of the quality information of the line controller 1 were finished, the control unit 4-1 resets the "delivery" signal (resets address "B011H").

At timing T6, the control unit 4-2 resets the "transportable" signal (bit in address "B070H") at a time point when the "delivery" signal of the control unit 4-1 is reset. The control unit 4-2 resets the "acceptance" signal (bit in address "B061H") at timing T7. When it is confirmed at timing T8 that the "delivery" signal of the control unit 4-1 has been reset, the line controller 1 resets the "reading-completion" signal.

Fig. 12 is a flowchart showing processes by the control unit 4-1 according to the embodiment 1.

First in step S1, the board 901 as a processing target is received. In step S2, the board 901 is processed by the processing device 5-1. In step S3, in the control unit 4-2 on the downstream side, a check is made to see if the "transportable" signal has been set in address "B070H" in the common memory 204. If YES, the processing routine advances from step S3 to step S4 and the sampling data regarding the board during the processing or after completion of the processing is written into addresses "W012H" to "W015H" in the common memory 204. The processing is finished. If the board can be delivered, the board ID of the board 901 to be delivered is written into addresses "W000H" to "W003H", the sheet processing quality information is stored into addresses "W00AH" to "W011H", and the board kind information is stored into addresses "B030H" to "B035H".

The processing routine advances to step S5. A transporting motor of the transport device 6-1 is driven and the transportation of the board 901 is started. When the board 901 is not detected by the sensor 902 in step S6, step S7 follows. The "delivery" signal in address "B011H" in the common memory 204 is set, thereby informing the control unit on the downstream side of a fact that the delivery of the board has been completed.

In step S8, the "acceptance" signal is set by the control unit on the downstream side. When the "reading-completion" signal of the line controller 1 is set in step S9, step S10 follows. The "delivery" signal set in step S7 is reset. Step S11 follows and a check is made to see if a preparation for reception of the next board 901 to be processed has been completed. If YES, step S12 follows and the "transportable" signal is set, thereby informing the control unit on the upstream side of a fact of the completion of the preparation. When the next board is inserted and conveyed from the upstream side, the processes from step S1 are repetitively executed.

Fig. 13 is a flowchart showing processes by the control unit 4-2 locating on the downstream side of the control unit 4-1.

First in step S21, a check is made to see if the preparation for reception of the board 901 has been completed. If YES, step S22 follows and the "transportable" signal (bit in address "B070H") is set, thereby informing the control unit 4-1 on the upstream side of a fact of the completion of the preparation. In the control unit 4-1, thus, the processing routine advances from step S3 to step S4 in Fig. 12.

The delivery of the board in the control unit 4-1 on the upstream side is started. When the "delivery" signal (bit in address "B0111H") in the control unit 4-1 is set (step S7 in Fig. 12), step S24 follows. A check is made by the sensor 903 in step S24 to see if the board 901 has reached. When the acceptance of the board 901 is detected by the sensor 903, step S25 follows. The board ID (W00H to W003H) and the board kind information (B030H to B035H) stored in the common memory 204 are fetched. After that, step S26 follows and the "acceptance" signal (bit in address "B061H") is set, thereby informing the control unit 4-1 of a fact that the conveyance has been completed. Thus, the processing routine in the control unit 4-1 advances from step S8 in Fig. 12 mentioned above to step S9.

The processing routine subsequently advances to step S27, the "delivery" signal (bit in address "B061H") is reset. In step S28, the "acceptance" signal in address "B061H" and the "transportable" signal in address "B070H" is reset. Step S29 follows and the conveyed board is processed. Subsequent processes are similar to those in step S3 and subsequent steps in Fig. 12 mentioned above.

Fig. 14 is a flowchart showing processes by the line controller 1 of the embodiment 1.

The line controller 1 reads out the data from the common memory 204 of the control unit which is processing the board 901 and samples the read-out data at a predetermined sampling timing (steps S31 and S32). When the timing is not the sampling timing, the processing routine advances from step S31 to step S33. A check is made to see if the "delivery" signal (bit in address "BXX1H": XX can be set to any one of "01", "06", "0B", "10", "15", and the like) of the control unit which is processing the board has been set. If YES, step S34 follows and the board ID (W00H to W003H), processing quality information (W00AH to W014H), and board kind information (B030H to B035H) are fetched. At a time point when the collection of those data is completed, step S35 follows and the "reading-completion" signal (bit in address "B411H") is set.

Step S36 follows and a check is made to see if the "delivery" signal of the control unit (for instance, control unit 4-1) as a target is OFF. If NO, step S38 follows and a check is made to see if the timing is the sampling timing in a manner similar to steps S31 and S32. When the sampling timing comes, step S39 follows and the data from the control unit which is processing the board is collected. When the "delivery" signal is reset in step S36, step S37 follows and the "reading-completion" signal (bit in address "B411H") is reset, thereby notifying each control unit of a fact that the reading operation of various data of the common memory 204 has been completed. Thus, for example, as shown in the flowchart of Fig. 12, the processing routine advances from step S9 to step S10 and the "delivery" signal of the control unit as a target is reset.

A selecting and housing processes when a defect occurs in the step (for example, inspecting step or the like) during the processing in the line will now be described.

For example, when a defect occurs in the step in the control unit 4-1, its career is stored into a register of the CPU 201. Quality information (bit in address "B034H" or "B035H") of the board shown in Fig. 4 is set to "NG" (the bit is set) at the time of the delivery of the board. The information is tracked to the control unit on the downstream side in accordance with the procedure of the flowchart mentioned above.

For example, now assuming that two boards are taken out, when one side is defective, the quality information of the relevant board is rewritten to "NG" (for example, the board information on the head side is set to "B034H" and the board information on the rear side is set to "B035H", thereby rewriting). In case of taking out a number of boards, the invention can similarly cope with such a case by writing the quality information of each board into the relevant area in addresses "B036H" to "B03FH".

The information regarding the quality of the board which is generated in the line as mentioned above is stored as board information in the control unit of each station, the board and the board information are tracked, and the processes are sequentially executed. In the final step, on the basis of the board ID, board information, and the like of the board which was tracked, a good product and a defective product of the boards are discriminated and they can be enclosed into different cassettes or the like. The information stored in the memory including those information effectively functions with respect to the management for ISO9000 or ISO14000. In the line controller 1, since the same contents as those in each control unit 4 have been also stored in the common memory, it is also possible to easily perform the management regarding ISO9000 or ISO14000.

The second embodiment of the invention will now be described.

Fig. 15 is a diagram showing a construction of a manufacturing line system according to the second embodiment of the invention. Portions common to those in the foregoing first embodiment are designated by the same reference numerals and their descriptions are omitted.

In Fig. 15, reference numeral 7 denotes a cassette enclosing a plurality of boards. The cassette 7 has a readable/writable ID tag 8 in which information shown in Fig. 16 has been stored.

As shown in Fig. 16, the ID tag 8 has "cassette ID", "cassette empty/mounting classification" indicating whether the cassette is empty or a board has been mounted, "product lot No.", "lot division classification", "product kind code", "completed process number", "next process number", "date of process", "time of delivery from process", and the like. Further, in the second embodiment, assuming that every two boards are taken out, each board ID and the information indicative of "OK" or "NG" of the boards A and B have been stored.

According to a tracking control method in a manufacturing line in the second embodiment of the invention, in a manufacturing processing line in which processing devices are connected by a network, when the board is delivered out by a board inserting station (corresponding to the station of the control unit 4-1) at the line head, namely, when the board is delivered to the station to be processed by the control unit 4-2 existing on the downstream side and is processed, it is confirmed that the "transportable" signal from the control unit 4-2 on the downstream side has been set. In this instance, the information such as a board ID and the like stored in the ID tag 8 attached to the cassette 7, namely, the individual board ID, board information, and the like of every enclosing stage are read and stored into the common memory 204. After that, the board is delivered to the control unit 4-2 on the downstream side.

The control unit 4-2 on the downstream side reads out the tracking information about the relevant board from a specific area in the common memory 204 at the timing for transportation mentioned above, fetches the read-out tracking information into a register (RAM) of the CPU of the control unit 4-2, and manages it. After completion of the process by the control of the control unit 4-2, the "transportable" signal from the control unit on the downstream side is examined. If "transportable", the processed board is delivered to the step on the downstream side. Prior to the delivery of the board, the tracking information regarding the board to be delivered is set into a predetermined area in the common memory 204. On the basis of the information on the ID tag 8 attached to the cassette 7, an interlock and signal transmission and reception among the control units (stations) are executed by using the network 3.

When a defect occurs in the inspecting step during the board processing line by each station or upon processing, such information is added to the tracking information by the relevant station and the resultant tracking information is tracked to the station on the downstream side. On the basis of such information, a quality of the board to be enclosed are selected in the enclosing station at the final stage of the line. The tracking information is written into the ID tag 8 attached to the enclosing cassette 7. Thus, even when the cassette 7 is transported to another line and is processed, the tracking process can be performed by using the information of the ID tag 8 attached to the cassette 7. Thus, the tracking can be carried out among a plurality of lines.

Fig. 17 is a flowchart showing processes in the control unit 4-1 according to the second embodiment of the invention.

The processes shown in the flowchart are almost similar to those in the flowchart of Fig. 12 except that in step S43, when the "transportable" signal of the control unit on the downstream side is received, the ID tag information attached to the cassette 7 is read and the board information is stored into a specific area in the common memory 204. The individual board ID of every enclosing stage of the cassette 7 and the board information are stored into specific addresses in the common memory 204.

Thus, in the control unit on the downstream side, the information stored in the common memory is read and the information regarding the board can be obtained. In steps S45 to S52, the processed board is delivered to the station on the downstream side as shown in steps S5 to S12 in Fig. 12 mentioned above. In step S53, when the board which was finally processed is transported to the station 10-n, the board quality is discriminated with reference to the board information stored in a predetermined address in the common memory 204. On the basis of the discrimination result, the board information is written into the ID tag of the cassette in step S54. The processes in steps S53 and S54 described here are executed by the control unit 4-n.

Thus, the cassette 7 is set to another line and even when the board is processed in this line, the board information in the preceding line can be referred, so that the board can be transported and processed while tacking among a plurality of independent lines.

According to the embodiments described above, there are the following effects. <ul id="ul0002" list-style="none" compact="compact"><li>(1) By setting in the host station, the sampling data of different sampling times can be individually collected every station. The sheet data of the board can be also collected synchronously with the tracking in the line.</li><li>(2) The procedures for the interlocking and signal transmission and reception among the stations in the line can be unified and a debugging and a maintenance at the time of leading of the line can be easily performed.</li><li>(3) All of the interlocking, signal transmission and reception, and transmission of board information among the stations can be executed by one network and the procedure can be simplified.</li><li>(4) Since the tracking data can be managed synchronously with the transportation of the transporting board among the stations, the host computer for tracking control is unnecessary.</li><li>(5) As compared with the system using the conventional host computer, a time necessary to transfer the tracking data is short and it is possible to cope with a short line cycle time.</li><li>(6) A processing instruction, selection, and enclosing of the processing boards can be performed by the addition and rewriting of the tracking information during the processing step and the utilization of the data.</li></ul>

The object of the invention is also accomplished by supplying a storing medium in which program codes of software to realize the functions of the foregoing embodiments have been recorded to a system or apparatus and by reading out and executing the program codes stored in the storing medium by a computer (or CPU or MPU) of the system or apparatus.

In this case, the program codes themselves read out from the storing medium realize the functions of the embodiments mentioned above and the storing medium in which the program codes have been stored constructs the present invention.

As a storing medium to supply the program codes, for example, it is also possible to use any one of a floppy disk, a hard disk, an optical disk, a magnetooptic disk, a CD-ROM, a CD-R, a magnetic tape, a non-volatile memory card, an ROM, and the like.

Not only a case where the functions of the embodiments mentioned above are realized by executing the read-out program codes by the computer but also a case where an OS (operating system) or the like which is working on the computer executes a part or all of the actual processes on the basis of an instruction of the program codes and the functions of the embodiments mentioned above are realized by the processes are included in the invention.

Further, a case where after the program codes read out from the storing medium were written into a memory equipped for a function expansion board inserted into the computer or a function expansion unit connected to the computer, a CPU or the like equipped for the function expansion board or function expansion unit executes a part or all of the actual processes on the basis of an instruction of the program codes and the functions of the embodiments mentioned above are realized by the processes is also included in the invention.

According to the embodiments described above, the synchronization among the control units connected to the processing devices can be established by using the common memories.

According to the embodiments, there is an effect such that while sharing the information regarding the work to be processed among a plurality of control units, the work can be processed by synchronizing the processes among the processing devices by a simple construction.

Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

A line system in which control units each of which is connected to a processing device of a work are connected through a network has a memory which has data for processing the work by the processing device and which is provided for each control unit and makes the contents in the memories provided for the control units coincide.