Architecture and interconnect scheme for programmable logic circuits

A programmable logic circuit comprising: an input/output interface for inputting signals to the programmable logic circuit;a plurality of cells coupled to the input/output interface, each of said cells capable of performing digital processing on signals;a first set of routing lines for coupling a plurality of cells to form logical clusters of cells, said first set of routing lines further providing programmable couplings to cells or other logical clusters;a second set of routing lines for coupling a plurality of logical clusters to form a logical block of logical clusters of cells, wherein each cell is programmably coupled to the second set of routing lines; anda plurality of sets of higher level global routing lines, each set of global routing lines spanning a plurality of logical blocks, wherein each set of higher level global routing lines can be programmably coupled to the second set of routing lines, said first set of routing lines and cells through the second set of routing lines.