Synchronous dma transfer protocol

Field of the Invention

The present invention relates to data transfer between a host device and a peripheral drive device via a bus. More particularly, the invention relates to a method for performing synchronous direct memory access, DMA, data transfers at an increased data rate.

Background

Data transfer rates between a host device and peripheral drive devices within a personal computer, PC, system are limited by the bus architecture interconnecting the devices. One type of bus commonly used to interconnect or interface the peripheral drive device to a system bus of a PC is an ATA bus, which is a disk drive interface originally designed for the ISA bus of the IBM PC/AT. The ATA bus was first configured using LS-TTL (Low-power Schottky transistor-transistor logic) gates to drive an 18 inch cable. The slow edges of the LS-TTL gates and the short cable length worked adequately in the then existing systems. However, as PC systems have become faster and more complex, the definition of the ATA bus has been expanded to include operating modes performing faster data transfer rates, and hardware designers have often extended the ATA cable length to well over 18 inches. For example, PIO (programmed I/O) modes now include PIO modes 0 - 4. Modes 0, 1 and 2 correspond to the ATA interface as originally defined, while PIO Mode 3 defines a maximum data transfer rate of 11.1 MBytes/sec and PIO Mode 4 defines a maximum transfer rate of 16.7 MBytes/sec. Similarly, new DMA modes have been defined. Multiword DMA Mode 0 corresponds to the original interface, while DMA Modes 1 and 2 provide faster data transfer rates. Multiword DMA Mode 2 has the same maximum transfer rate as the new PIO Mode 4.

These new operating modes require higher performance from the ATA bus, resulting in an effort to increase data transfer rates by reducing cycle times. The effort to reduce cycle times has been accomplished by increasing edge rates. The increased edge rates together with the increase in ATA cable length have in turn led to the emergence of weaknesses in the original ATA cabling configuration. These weaknesses affect the integrity of the signals transmitted over the cable, Of particular concern are excessive ringing and crosstalk between signals, and timing/propagation delays which can lead to system failure and/or data loss. Increased edge rates and excessive cable length cause these problems. Thus, the data transfer rate of valid usable data is restricted by limitations inherent to the structure of the ATA bus.

The increased edge rates and excessive cable length are problematic to the ATA bus because it is a poorly terminated bus structure design. The standard 18 inch ATA bus cable is generally modeled as a single-ended transmission line with a characteristic impedance typically of about 110 ohms and a propagation velocity typically of about 60% c. According to transmission line theory, ringing occurs when the termination impedance does not match the characteristic impedance of the cable. The amplitude of ringing is increased with a greater mismatch of impedances. Ringing of sufficient amplitude on signal and data lines of the ATA bus can cause false triggering and excessive settling delays which can lead to system failure and/or data loss.

The occurrence of ringing is especially problematic for data transfers over an ATA bus in PC systems because digital information is being transferred over a transmission line. According to another aspect of transmission line theory, information to be transmitted over the transmission line is input as a waveform. Due to the characteristic impedance and length of the transmission line, the waveform output from the transmission line has some distortion. In analog transmissions where the input waveforms are generally sine waves, the output waveform is typically distorted by a phase shift which can be corrected with relative ease. However, in digital transmissions, the input waveforms are generally some type of square wave, since recognition of an edge transistion is what is important due to the fact that information transmitted is in the form of 1's and 0's. Distortion of these square waves is evident as ringing, which results in a waveform in which the edge transistions cannot be clearly recognized. Thus, chances for false triggering, as mentioned above, are likely and symptomatic of digital transmissions.

The problem of increased ringing has become more prevalent recently because the bus architecture of the modem PC has changed to accommodate increased processor and drive speeds. As processor bus speeds have increased from 8 MHz to 33 MHz and disk drives have increased in speed, it has become necessary to update the ATA standard to allow for faster data transfer rates. To reduce propagation delay, some manufacturers have increased the output drive of the host in order to slew the output signal faster with the capacitive load of the cable. This has been accomplished by implementing the ATA interface chips with fast CMOS processes instead of the low speed TTL devices used in the first ATA buses. As a result, the output impedance has decreased, and the edge rates on the ATA bus have decreased to 1 to 2 ns or less, as opposed to a 5 to 6 ns range of the TTL devices. These fast edges without sufficient terminations have aggravated the ringing on the bus to the point that many system/drive combinations fail to work.

Crosstalk occurs when switching on one signal line causes induced signals in an adjacent or nearby line. A signal couples into an adjacent line by two mechanisms: coupling capacitance and mutual inductance. As a switching signal wavefront propagates down a cable, it couples energy into the adjacent line. Once the energy is in the second line, it propagates in both directions: toward the receiver and toward the source. The magnitude of the coupled signal is proportional to the rate of change of the signal in the primary line. Additionally, the amplitude of the coupled signal is proportional to the total amount of coupling capacitance and mutual inductance, and is therefore proportional to cable length. These crosstalk characteristics make it important to control the slew rate and cable length of newer ATA bus drivers because fast edge rates and resulting ringing on the data lines can couple by crosstalk into adjacent control lines, and cable lengths over 18 inches increase the probability of crosstalk.

An additional concern associated with the poor termination and cable length of an ATA bus design is propagation delay which is further aggravated by cable length violations. As discussed above, the ATA bus was originally defined to have a maximum length of 18 inches. However, today, system designers are hard pressed to design a system in which a host device can be connected to a peripheral drive device within 18 inches. Moreover, some systems are being implemented with dual-ATA interface ports for sharing two ATA cables. These ports are not completely independent of each other, and dual-porting results in an ATA cable which is effectively 36 inches long. These increased cable lengths impose propagation delays associated with the host and peripheral drive devices sending control and data signals back and forth to each other. These propagation delays ultimately affect the data transfer rate and overall performance of the bus.

A further concern related to data transfers over the ATA bus is data integrity. It is important that the data transferred over the bus is valid, and thus there is a desire to provide error detection capability which is reliable and which can be easily implemented. Since words made up of data bits are being transferred over the ATA bus, a bit oriented error detection approach is more practical than a symbol oriented error detection approach. However, conventional bit oriented error detection is impractical for data transfers occurring over the ATA bus, because the conventional bit oriented error detection is a bit-serial approach. The conventional bit error detection procedure generates a cyclic redundancy code (CRC) value by logically manipulating a stream of input data bits using a generator polynomial:<maths id="math0001" num=""><math display="block"><mrow><msup><mrow><mtext>G(X) = X</mtext></mrow><mrow><mtext>16</mtext></mrow></msup><msup><mrow><mtext> + X</mtext></mrow><mrow><mtext>12</mtext></mrow></msup><msup><mrow><mtext> + X</mtext></mrow><mrow><mtext>5</mtext></mrow></msup><mtext> + 1.</mtext></mrow></math><img file="EP0804764B1_D0001.tif" /></maths> Each bit of the data stream is shifted sequentially into a CRC logic encoder/decoder by a bit clock operating at a bit cell timing rate. Since the data transfers occurring over the ATA bus are transferring 16-bit words of data, each word is transferred at a clock period equal to 16 times the bit clock. Thus, using the existing bit serial approach operated by a bit clock would require clocking at the frequency of the bit clock, or 16 times the word clock. A further problem of the bit-serial approach is that since the data is being transferred in word units, there is no bit clock available at this part of the ATA interface circuit structure. Thus, the existing bit oriented error detection procedure is not a practical method of providing data integrity for data transfers over the ATA bus.

The above discussed limitations of the ATA bus design have restricted the data transfer capability between a host device and a peripheral drive device to the rates as described above. With the emergence of still faster processors and peripheral devices it is desirous to obtain still faster and accurate data transfer rates between the host and peripheral drive devices. Thus, there exists a hitherto unsolved need for an improved, simple and cost effective method for performing data transfers between a host device and a peripheral drive device over a bus interface having certain operational limitations, at an increased data transfer rate without violating the operational limitations of the bus interface.

US 5,280,623 describes a bus communication system capable of transition between addressed data transfers and handshake data transfers without reconfiguration steps. In a synchronous data transfer addressed write sequence, the system uses a request - acknowledge - data transfer - strobe sequence of events.

Summary

The method of the present invention satisfies these needs.

The present invention is directed to a method for performing a synchronous DMA burst in a computer system which includes a host device connected to at least one peripheral drive device by a bus, where the bus has an associated control signal transmission strobe rate and is used for data transfers between the peripheral drive device and the host device in response to a host device read or write command. The data transfers for each command are carried out through a series of the synchronous DMA bursts over the bus.

In response to a host device read command, the peripheral drive device asserts a DMA request signal to initiate the synchronous DMA burst, and when the host device is ready to begin the synchronous DMA burst, the host device asserts a DMA acknowledge signal in response to the DMA request signal. Within a certain predetermined time period after the host device asserts the DMA acknowledge signal, the peripheral drive device places a first data word on the bus, then after a second predetermined time period has elapsed since placing the data word on the bus, the peripheral drive device toggles a strobe signal from a high state to a low state to latch the first data word into the host device. In the method of the present invention, the peripheral drive device is always in control of initiating the synchronous DMA burst, and the device which is sending the data is in control of both the data and the strobe signal which latches the data into the device receiving the data. The control of both the data and the strobe signal by one device minimizes effects of propagation delay, cable settling and setup time associated with the DMA bursts and thus increases a rate at which data can be transferred over the bus.

An additional word can be transferred during the DMA burst by the peripheral drive device placing the additional word on the bus; then, after the second predetermined time period has elapsed, the peripheral drive device toggles the strobe signal from the low state to the high state to latch the additional word into the host device. These steps of placing the additional word on the bus and toggling the strobe signal from one state to the other state can be repeated until the peripheral drive device has finished sending all data words to be transferred. When the peripheral drive device has finished sending all the data, the peripheral drive device deasserts its DMA request signal to terminate the synchronous DMA burst. If the strobe signal is not at the high state after the peripheral drive device has finished sending the data, the peripheral drive device returns the strobe signal back to the high state.

Additionally, the method can include steps to perform parallel bit oriented error detection to ensure that the data transferred during the synchronous DMA burst is valid. During the data transfer, both the peripheral drive device and the host device calculate a 16-bit CRC value. After the peripheral drive device has sent a complete DMA burst, the host device sends its calculated CRC value to the peripheral drive device and the peripheral drive device performs a comparison of the received CRC value with its calculated CRC value to check for any errors.

When the host device command is a write command, the synchronous DMA burst is still initiated by the peripheral drive device asserting a DMA request signal. When the host device is ready to begin the burst, the host device asserts a DMA acknowledge signal and places a first data word on the bus . Responding to the DMA acknowledge signal, the peripheral drive device asserts a ready signal within a predetermined time period after the DMA acknowledge signal is asserted. The host device then toggles the strobe signal from the high state to the low state within the predetermined time period after the ready signal was asserted by the peripheral drive device. The toggling of the strobe signal latches the data word into the peripheral drive device. Additional data words are transferred by the host device placing the additional data words on the bus and toggling the strobe signal to latch the data word into the peripheral drive device. Steps to perform a parallel bit oriented error detection during a write command synchronous DMA burst are similar to the steps performed during the read command synchronous DMA burst.

Preferably, the synchronous DMA burst is performed over an ATA bus having a control signal transmission strobe rate of approximately 8.3 MHz, and the data transfer rate is increased to approximately 33.3 MBytes/sec.

The method of the present invention provides many advantages over prior transfer protocols. In particular, the synchronous DMA burst transfer protocol provides a significantly increased data transfer rate between a host device and a peripheral drive device and is operable within existing bus system architectures. The present method is therefore an inexpensive way to increase the rate of data transfer between a host device and a peripheral drive device. Furthermore, the present method provides the increased data transfer rate and improved data integrity, without increasing the control signal transmission strobe rate on the bus, therefore eliminating problems of system integrity associated with increased control signal transmission frequencies. A further advantage of the present method is that backward compatibility with existing transfer protocols is provided so that the method is operable without substantial hardware modifications in systems including other peripheral drive devices which use the existing strobed transfer protocols.

Brief Description of the Drawings

These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where: <ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1a shows a block diagram of a PC architecture in which the present invention can be implemented;</li><li>Fig. 1b shows a partial schematic circuit representation for existing ATA cables;</li><li>Fig. 2 shows a simplified component and timing diagram for a prior art data transfer protocol;</li><li>Fig. 3 shows a simplified component and timing diagram for a synchronous DMA burst according to a version of the present invention;</li><li>Fig. 4a shows a detailed timing diagram illustrating the data and control signals exchanged during drive initiation of a synchronous DMA burst for a read command implemented according to aspects of the present invention;</li><li>Fig. 4b shows a detailed timing diagram illustrating the data and control signals exchanged during drive initiation of a synchronous DMA burst for a write command implemented according to further aspects of the present invention;</li><li>Fig. 5 shows a detailed timing diagram illustrating the data and control signals exchanged during a sustained synchronous DMA burst according to further aspects of the present invention;</li><li>Fig. 6a shows a detailed timing diagram illustrating the data and control signals exchanged during drive termination of a synchronous DMA burst for a read command implemented according to further aspects of the present invention;</li><li>Fig 6b shows a detailed timing diagram illustrating the data and control signals exchanged during drive termination of a synchronous DMA burst for a write command implemented according to further aspects of the present invention;</li><li>Fig 7a shows a detailed timing diagram illustrating the data and control signals exchanged during host termination of a synchronous DMA burst for a read command implemented according to further aspects of the present invention;</li><li>Fig 7b shows a detailed timing diagram illustrating the data and control signals exchanged during host termination of a synchronous DMA burst for a write command implemented according to further aspects of the present invention;</li><li>Fig. 8a shows a simplified logic circuit for implementing error detection according to an embodiment of the present invention;</li><li>Fig. 8b shows a more detailed diagram of the logic circuit shown in Fig. 8a; and</li><li>Fig. 9 shows a simplified flow chart illustrating a version of the present invention.</li></ul>

Description

Fig. 1a shows an example of a conventional PC architecture in which a method embodying aspects of the present invention can be implemented. The PC system <b>10</b> typically includes a CPU <b>12</b> connected to a RAM <b>14</b> and a ROM <b>16</b> by a processor bus <b>18.</b> A bus interface <b>20</b> connects the processor bus <b>18</b> to an ISA bus <b>22</b> which can include a plurality of card slots <b>24</b>. Additionally, a local bus interface <b>26</b> connects the processor bus <b>18</b> to a local bus <b>28</b> which can also include a number of local bus card slots <b>30.</b> A peripheral drive device <b>32</b> is connected to the local bus <b>28</b> via an ATA bus <b>34</b> and ATA interface <b>36.</b>

Fig. 1b shows a partial schematic electrical circuit diagram for one signal path of a conventional ATA bus <b>34</b> cable. The line <b>33</b> of the ATA bus <b>34</b> has a source or input impedance Z_in and a resulting termination or output impedance Z_out which is a function of the input impedance Z_in, the characteristic impedance Z_char of the ATA bus line <b>33,</b> and the distance d of the ATA bus line <b>33.</b> As discussed above in the Background section, the ATA bus <b>34</b> was not designed to be terminated. Thus, in the ATA bus <b>34</b> definition these impedance values for each signal line are such that Z_in &lt; Z_char and Z_char &lt; Z_out, resulting in the problem of ringing.

For simplicity, the following discussion describes a disk drive connected to a host by an ATA bus. However, as those skilled in the art will recognize, the present invention is capable of being implemented in a system having other peripheral devices on the ATA bus. Additionally, the term host device generally refers to the host end of the ATA bus, which one skilled in the art will recognize to include, for example, the CPU 12 and the ATA bridge/interface <b>36</b>. The present invention can also be realized in a system having plural drive devices (not shown) connected to the ATA bus <b>34.</b>

Referring to Fig. 2, the prior art DMA transfer protocol is a strobed, asynchronous transfer protocol where an ATA host <b>35</b> is always in charge of when events are to take place. Fig. 2 shows the strobe signal from the perspective of the host <b>35,</b> and the data from the perspective of the disk drive <b>32.</b> When the ATA host <b>35</b> wants to read data from an attached disk drive <b>32,</b> it sends a strobe to the disk drive <b>32</b> at time to. The disk drive <b>32</b> does not know when it has to transfer data until it sees the falling edge of the strobe. Prior to receiving the strobe signal, the disk drive <b>32</b> is just waiting for the "last minute" notification that it needs to get data ready to send to the host <b>35.</b> The strobe takes time to travel from the host <b>35</b> to the disk drive <b>32,</b> so the disk drive <b>32</b> receives the request later than when the host <b>35</b> asks for the data. The disk drive <b>32</b> finally sees the strobe at some later time t₁. Then after some processing delay, the disk drive <b>32</b> puts the data out on the bus at time t₂, to be sent back to the host <b>35.</b> Another transit delay is associated with the data being sent back to the host <b>35,</b> so the data does not arrive at the host <b>35</b> until some later time t₃. Another processing delay is associated receiving the data, so the host finally latches the data at time t₄. The host must latch the data during the strobe interval, and since there is a certain maximum speed that can be achieved, the strobe interval must be long enough to make sure that the data is available to the host. Thus, in the prior art asynchronous transfer protocol, the strobe interval must take into account transit delays associated with both the host <b>35</b> to disk drive <b>32</b> transit time and the disk drive <b>32</b> to host <b>35</b> transit time, as well as processing delays associated with both the host <b>35</b> and the disk drive <b>32.</b> The necessity to account for these delays limits the data transfer rate to those currently obtained with DMA Mode 2 and PIO Mode 4.

The present invention overcomes the data transfer limits imposed in the prior art transfer protocol by eliminating the situation where the disk drive <b>32</b> is waiting for the "last minute" notification that it needs to do a data transfer. Instead, in the present invention, the device which is sending data (whether host <b>35</b> or drive <b>32</b>) is in charge of the controlling strobe signal. Fig. 3 shows a simplified timing diagram, from the perspective of the disk drive <b>32,</b> of a version of the present invention where the disk drive <b>32</b> is in charge of the strobe signal to transfer data for a read DMA burst. Once the host <b>35</b> has given a command that it wants to read data and preliminary handshaking to initiate the burst is performed, the disk drive <b>32</b> is in charge and determines the time when the data is to be transferred. As shown in Fig. 3, when the disk drive <b>32</b> is ready to send the data, it places the data on the bus at time t₀, then the disk drive <b>32</b> will wait until it knows the data has settled on the cable and the disk drive <b>32</b> will toggle the strobe signal at time t₁. The toggling of the strobe signal indicates to the host <b>35</b> that the data is available, and the data is latched into the host <b>35</b> when the strobe generated at time t₁ reaches the host.

The delay between the time the disk drive <b>32</b> places the data on the bus and the time it toggles the strobe signal is necessary because when data is placed on the ATA bus, there is associated ringing due to the poor termination of the bus, so it is necessary to let the data signal settle before latching it in the host <b>35</b>. However, the flight or propagation time to get from the disk drive 32 to the host 35 is substantially the same for both the data signal and the strobe signal, and the slew rate (time for a signal to change from "1" to "0" or "0" to "1") is substantially the same for both the data signal and the strobe signal. With the present invention, only the settling time of the data signal needs to be accounted for, since the data and the strobe are sent by one device and the slew rates and propagation delays of these signals are similar. If loading at the host end of the cable changes the slew rate of the data signal, the slew rate of the strobe signal will be changed by a similar amount, and the relative timing of the signals will still be similar. This provides a significant time improvement over the prior art transfer protocol where the host <b>35</b> is in charge of the strobe signal and the disk drive <b>32</b> is in charge of the data signal. In the prior art situation, time is lost sending the strobe to the disk drive <b>32,</b> time is lost sending the data to the host <b>35,</b> and the lost time can never be recovered.

According to aspects of the present invention, very short strobe intervals can be set up since the propagation delays and slew rates in both directions do not have to be accounted for. To ensure data transfer, the synchronous DMA transfer of the present invention only requires a latency for the data to settle before the strobe signal can reach the host <b>35.</b> Thus, the synchronous DMA burst method of the present invention provides an increased data transfer rate of up to 33.3 MBytes/sec which is double the fastest currently existing PIO Modes and Multiword DMA Modes.

Details discussing the initiation of the synchronous DMA transfer according to an embodiment of the present invention will now be described with reference to Figs. 4a and 4b. Referring to Fig. 4a, sometime after the host <b>35</b> has sent a read command requesting data and the disk drive <b>32</b> is ready to begin the data transfer, the disk drive <b>32</b> will initiate the synchronous DMA burst by asserting a DMA request signal, DMARQ (indicated as event 1), to the host <b>35.</b> In response to DMARQ being asserted, when the host <b>35</b> is ready to receive the requested data, the host <b>35</b> indicates it is ready by asserting a DMA acknowledge signal, -DMACK (indicated as event 2), and must keep - DMACK asserted until the end of the burst. The disk drive <b>32</b> can drive or place data on the ATA bus <b>34</b> after a minimum time delay T_za, from assertion of -DMACK, allowing for output drivers to turn on. Typically, the minimum time T_za required for the output drivers to turn on is approximately 20 ns. Before the disk drive <b>32</b> can toggle the strobe signal which latches the data into the host <b>35,</b> the disk drive must also wait for the host <b>35</b> to deassert a stop signal, STOP, and assert a ready signal, -DMARDY, after the host asserts -DMACK. The deassertion of STOP and assertion of -DMARDY (indicated as events 3) are performed within a standard time envelope for all control signal transitions from the assertion of -DMACK. This time envelope is preferably within a range of approximately 20 to 70 ns.

After the host <b>35</b> has deasserted STOP and asserted -DMARDY, the disk drive <b>32</b> can send the first strobe signal and must do so within a limited time period T_li, after seeing the STOP and -DMARDY signals. Preferably, this limited time period T_li is within a range of approximately 0 to 150 ns. Additionally, the disk drive <b>32</b> must wait a minimum predetermined setup time period T_dvs, measured from when the disk drive <b>32</b> placed the data word on the ATA bus <b>34,</b> before it can send the first strobe signal. This time period being the time it takes the data to become valid on the ATA bus <b>34.</b> Preferably, the minimum setup time T_dvs is within a range of from about 38 to about <b>75</b> ns, depending on the speed selected.

The disk drive <b>32</b> sends the first strobe signal to the host <b>35</b> by toggling the strobe signal from a high state to a low state (indicated as event 4). The toggling of the strobe signal from the high state to the low state defines a first edge of the strobe signal which is recognized by the host <b>35</b> as an indication that valid data is available on the ATA bus <b>34.</b> When the host <b>35</b> sees the edge, it takes the data off of the ATA bus <b>34</b>. Thus, the toggling of the strobe signal is used to latch the data in the host <b>35</b> during a read burst.

Referring now to Fig. 4b, the initiation of the synchronous DMA burst for a write command will be described according to principles of the present invention. As in the case with a read command, the synchronous DMA burst is initiated by the disk drive <b>32</b> asserting DMARQ when it is ready to begin the synchronous DMA burst (event 1). In response to DMARQ being asserted, when the host <b>35</b> is ready to write its data, the host <b>35</b> indicates it is ready by asserting -DMACK (indicated as event 2) and deasserts STOP (indicated as event 3) within the standard time envelope of -DMACK. Additionally, the host <b>35</b> drives data on the ATA bus <b>34.</b> The host <b>35</b> then waits for the disk drive <b>32</b> to assert -DMARDY which indicates that the disk drive 32 is ready to receive data from the host <b>35.</b> The disk drive <b>32</b> must assert -DMARDY (indicated as event 4) within the limited time period T_li after seeing -DMACK asserted and STOP deasserted. Since the host <b>35</b> is now sending data, the host <b>35</b> is now also in charge of the strobe signal, but before the host <b>35</b> can toggle the strobe signal, it must wait for - DMARDY to be asserted by the disk drive <b>32</b> as described above.

Once the disk drive <b>32</b> asserts -DMARDY, the host <b>35</b> may toggle the first strobe signal (indicated as event 5) anytime after seeing -DMARDY. However, the host <b>35</b> must wait the minimum predetermined setup time period T_dvs, measured from when the host <b>35</b> placed the data word on the ATA bus <b>34,</b> before it can send the first strobe signal, to allow for the data to become valid. Similar to the read case, when the disk drive <b>32</b> sees the first edge of the strobe signal, it knows to take valid data off of the ATA bus <b>34.</b> Thus, the toggling of the strobe signal is used to latch the data in the disk drive <b>32</b> during the write burst.

After the synchronous DMA burst is initiated and the first data word is latched into the host <b>35,</b> in the case of a read command, or into the disk drive <b>32,</b> in the case of a write command, additional data words can be transferred during the synchronous DMA burst. Fig. 5 shows a timing diagram of the control and data signals during a sustained synchronous DMA burst transferring plural data words. The figure generically depicts the data bus as seen by a sender and a receiver, rather than the host and disk drive, to be applicable to both the case of a read burst and a write burst. As described above, a first data word which was driven on the ATA bus <b>34</b> at some earlier time t₁ (not shown) is latched into the receiver by the toggling of the strobe from the high state to the low state (event 1). At a second later time t₂, a next data word is driven on the ATA bus <b>34.</b> This next data word is latched into the receiver by toggling the strobe signal from the low state to the high state (event 2). The toggling of the strobe signal from the low state back to the high state defines a second edge of the strobe signal. Further additional words can be driven on the ATA bus <b>34</b> by the sender and latched into the receiver by toggling of the strobe signal back and forth between the high and low states. From the receiver's viewpoint, whenever an edge of the strobe signal is seen, the receiver knows to take data off of the ATA bus <b>34.</b> Thus, both edges of the strobe signal are utilized in the synchronous DMA burst to transfer data.

As shown in Fig. 5 and described above, during the synchronous DMA burst, the sender always drives data onto the ATA bus <b>34</b> and after the minimum predetermined setup time period T_dvs allowing for cable settling and setup time, the sender will toggle the strobe signal. Using both edges of the strobe signal in the manner described above enables the frequency of the strobe signal to match the frequency of the data. On the ATA bus the highest fundamental control signal frequency on the cable should be no greater than approximately 8.33 MHz, so that signal integrity is maintained.

Furthermore, the data is shown differently at the sender and the receiver to emphasize that cable settling time will not allow the data to be considered stable at the receiver until long after it is driven at the sender. The minimum predetermined setup time that data is required valid at the sender T_dvs, and the minimum time that the data may go invalid after the sender toggles the strobe signal T_dvh, form a wider window than the data setup time T_ds and the data hold time T_dh guaranteed to the receiver.

Termination of a synchronous DMA burst will now be discussed with reference to Figs. 6a, 6b, 7a and 7b. After the strobe signal has been toggled for the first time, both the sender and the receiver can take actions to terminate the burst. Certain conditions must first be met before the synchronous DMA burst is terminated. When the receiver wishes to terminate the burst, it must first ensure that the pending transfer is fully paused. Likewise, when the sender wishes to terminate the burst, it must wait a minimum time period T_ss after toggling the strobe signal before it can assert a stop signal or deassert DMARQ to terminate the pending transfer. Preferably, the minimum time period T_ss is approximately 50 ns.

Fig. 6a shows the control and data signals exchanged when the disk drive <b>32</b> terminates the synchronous DMA burst during a read command. The disk drive <b>32</b> indicates its desire to terminate the burst by deasserting the DMARQ signal (event 1), and the host <b>35</b> acknowledges the deassertion by asserting STOP and deasserting - DMARDY within the limited time period T_li (event 2). Once the disk drive <b>32</b> sees that the host <b>35</b> has asserted STOP, the disk drive <b>32</b> must return the strobe signal to the high state, if it isn't already in the high state (event 3). The returning of the strobe signal to the high state must be done within the limited time period T_li after seeing the STOP signal. After the host <b>35</b> sees that DMARQ is deasserted, STOP is asserted, -DMARDY is deasserted, and the strobe signal is high, the host <b>35</b> can deassert -DMACK (event 4), and must do so within a minimum limited predetermined time period T_mli after all the listed conditions are met Preferably, the minimum limited predetermined time period T_mli is a range of from about 20 to about 150 ns. Additionally, the disk drive <b>32</b> tri-states the strobe signal after a pull-up time T_irdyz, allowing for a control signal to go to high impedance, as measured from the deassertion of -DMACK by the host <b>35.</b> Typically, the pull-up time T_irdyz, is approximately 20 ns.

Upon termination of the synchronous DMA burst, the strobe signal is required to be returned to the high state so that the strobe signal is ready for a next synchronous DMA burst. This "strobe clean-up" is necessary since the first strobe signal in any synchronous DMA burst must be toggled from the high state to the low state to latch the first data word into the receiver. The strobe clean-up is also advantageous because it allows the present synchronous DMA burst method to be backwardly compatible with existing host-peripheral data transfer protocols which also use the strobe signal in an initial high state.

Fig. 6b shows the control and data signals exchanged when the disk drive <b>32</b> terminates the synchronous DMA burst during a write command. As in the case of the disk drive <b>32</b> terminating a read burst, the disk drive <b>32</b> indicates its desire to terminate the burst by deasserting the DMARQ signal (event 1). The host <b>35</b> acknowledges the deassertion of DMARQ by asserting STOP within the limited time period T_li (event 2), and by returning the strobe signal to the high state within the limited time period T_li (event 3). The host <b>35</b> can deassert -DMACK (event 4) once the above events have taken place, and within the minimum limited predetermined time limit T_mli. Finally, the disk drive <b>32</b> then tri-states -DMARDY (event 5) after the pull-up time T_irdyz, as measured from the deassertion of -DMACK by the host <b>35.</b>

Fig. 7a shows the control and data signals exchanged when the host <b>35</b> terminates the synchronous DMA burst during a read command. Here, the host <b>35</b> signals its desire to terminate the burst by asserting the STOP signal (event 1), and the disk drive <b>32</b> acknowledges the request by deasserting DMARQ (event 2) and returning the strobe signal to the high state (event 3) within the limited predetermined time period T_li after seeing STOP. Then, as in the cases when the disk drive <b>32</b> terminated the synchronous DMA burst, the host <b>35</b> deasserts -DMACK (event 4) within the minimum limited predetermined time period T_mli after the above events have occurred. Finally, the disk drive <b>32</b> tri-states the strobe signal after the pull-up time T_irdyz.

Fig. 7b shows the control and data signals exchanged when the host <b>35</b> terminates the synchronous DMA burst during a write command. As in the case of the host <b>35</b> terminating a read burst, the host 35 signals its desire to terminate the burst by asserting the STOP signal (event 1). The disk drive <b>32</b> acknowledges the request by deasserting DMARQ and deasserting -DMARDY (events 2) within the limited predetermined time period T_li after seeing STOP. The host <b>35</b> must then return the strobe signal to the high state (event 3) within the limited predetermined time period T_li after seeing DMARQ deasserted. Once the strobe signal has been returned to the high state, the host <b>35</b> must also deassert -DMACK (event 4) within the minimum limited predetermined time period T_mli after returning the strobe signal to the high state. Then the disk drive <b>32</b> tri-states -DMARDY after the pull-up time T_irdyz.

The method of the present invention further includes steps for performing error detection for data integrity of the data being transferred over the ATA bus <b>34.</b> In a preferred embodiment, a bit-error detection code is implemented since the synchronous DMA bursts are transferring data words over the ATA bus <b>34,</b> and thus a bit oriented error detection approach is more practical than a symbol oriented error detection approach. However, as discussed above in the Background section, conventional bit oriented error detection is impractical since the conventional bit error detection is a bit serial approach.

A novel 16-bit parallel CRC approach is implemented using a parallel CRC logic encoder/decoder <b>40,</b> shown in Figs. 8a and 8b. The parallel CRC logic encoder/decoder <b>40</b> uses the same generator polynomial as the conventional bit-serial approach, but a word clock <b>44</b> is used instead of the bit clock. A 16-bit CRC value is cyclically calculated by both the host <b>35</b> and the disk drive <b>32</b> as each data word is being transferred over the ATA bus <b>34.</b> At the end of the data transfer, the host device <b>35</b> sends its generated 16-bit CRC value over the ATA bus <b>34</b> to the disk drive <b>32,</b> and the disk drive <b>32</b> exclusive-or's the received 16-bit CRC value with its calculated 16-bit CRC value, to check for an error. If an error is detected, the disk drive <b>32</b> sets an error bit of an error register to report the error to the host <b>35</b> at the end of the command.

In a preferred version of the invention, the CRC value is calculated in the following manner. Fig. 8a shows a simplified logic circuit for the CRC logic encoder/decoder <b>40</b> performing error detection for a version of the present invention. Both the host <b>35</b> and the disk drive <b>32</b> include the circuitry for the CRC logic encoder/decoder <b>40.</b> At the beginning of each synchronous DMA burst transfer, the CRC logic encoder/decoder <b>40</b> is set to a predetermined value. Preferably the value is 516dh. A stream of 16-bit data words enters the CRC logic encoder/decoder <b>40,</b> the CRC logic encoder/decoder <b>40</b> performs logic operations on the input data bits, and the CRC value is output from the CRC logic encoder/decoder <b>40.</b> If "d" represents the stream of data words entering the CRC logic encoder/decoder <b>40,</b> the entire stream of data bits is represented as follows: <ul id="ul0002" list-style="none" compact="compact"><li>d15₀, d14₀, d13₀, ..., d1₀, d0₀ :   first word</li><li>d15₁, d14₁, d13₁, ..., d1₁, d0₁ :   second word ...</li><li>d15_i, d14_i, d13_i, ..., d1_i, d0_i : ith word,</li></ul> where d15 is the most significant bit of a data word, and d0 is the least significant bit of a data word. The 16 data bits d0_j - d15_i<b>42</b> of each ith word being transferred is shifted into the CRC logic encoder/decoder <b>40</b> using a clock signal WCLK from a word clock <b>44,</b> the CRC calculation is performed, and a calculated 16-bit CRC value is output as X0(q) - X15(^q) <b>46.</b>

Referring to Fig. 8b, a more detailed schematic of the CRC logic encoder/decoder 40 is shown. The CRC logic encoder/decoder 40 includes 16 1-bit registers X0 - X15 <b>48a - 48p,</b> which serve as place holders for the 16-bit CRC value being calculated, and 16 corresponding combinational logic components Y0 - Y15 <b>50a - 50p</b> performing logic operations on the data bits. As shown in Fig. 8b, the combinational logic components Y0 - Y15 <b>50a - 50p</b> include an input from its corresponding register X0 - X15 <b>48a - 48p.</b> The combinational logic components Y0 - Y15 <b>50a - 50p</b> include additional inputs from the various components of the CRC logic encoder/decoder <b>40.</b> However, for clarity and simplicity, these operative connections with the other components are not shown. The output of the combinational logic components <b>50a - 50p</b> is then fed back to the registers X0 - X15 <b>48a - 48p</b> as input. Representing inputs to the registers of the CRC logic encoder/decoder as (d) and outputs from the registers as (q), the CRC value is cyclically calculated using the following equations: <tables id="tabl0001" num="0001"><table frame="all"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">X0(d) = f16;</entry><entry namest="col2" nameend="col2" align="left">X8(d) = f8 xor f13;</entry></row><row><entry namest="col1" nameend="col1" align="left">X1(d) = f15;</entry><entry namest="col2" nameend="col2" align="left">X9(d) = f7 xor f12;</entry></row><row><entry namest="col1" nameend="col1" align="left">X2(d) = f14;</entry><entry namest="col2" nameend="col2" align="left">X10(d) = f6 xor f11;</entry></row><row><entry namest="col1" nameend="col1" align="left">X3(d) = f13;</entry><entry namest="col2" nameend="col2" align="left">X11(d) = f5 xor f10;</entry></row><row><entry namest="col1" nameend="col1" align="left">X4(d) = f12;</entry><entry namest="col2" nameend="col2" align="left">X12(d) = f4 xor f9 xor f16;</entry></row><row><entry namest="col1" nameend="col1" align="left">X5(d) = f11 xor f16;</entry><entry namest="col2" nameend="col2" align="left">X13(d) = f3 xor f8 xor f15;</entry></row><row><entry namest="col1" nameend="col1" align="left">X6(d) = f10 xor f15;</entry><entry namest="col2" nameend="col2" align="left">X14(d) = f2 xor f7 xor f14;</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">X7(d) = f9 xor f14;</entry><entry namest="col2" nameend="col2" align="left">X15(d) = f1 xor f6 xor f13;</entry></row></tbody></tgroup></table></tables>    where <tables id="tabl0002" num="0002"><table frame="all"><tgroup cols="2" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="78.75mm" /><colspec colnum="2" colname="col2" colwidth="78.75mm" /><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">f1 = d0_i xor X15(q);</entry><entry namest="col2" nameend="col2" align="left">f9 = d8_i xor X7(q) xor f5;</entry></row><row><entry namest="col1" nameend="col1" align="left">f2 = d1_i xor X14(q);</entry><entry namest="col2" nameend="col2" align="left">f10 = d9_i xor X6(q) xor f6;</entry></row><row><entry namest="col1" nameend="col1" align="left">f3 = d2_i xor X13(q);</entry><entry namest="col2" nameend="col2" align="left">f11 = d10_i xor X5(q) xor f7;</entry></row><row><entry namest="col1" nameend="col1" align="left">f4 = d3_i xor X12(q);</entry><entry namest="col2" nameend="col2" align="left">f12 = d11_i xor X4(q) xor f1 xor f8;</entry></row><row><entry namest="col1" nameend="col1" align="left">f5 = d4_i xor X11(q) xor f1;</entry><entry namest="col2" nameend="col2" align="left">f13 = d12_i xor X3(q) xor f2 xor f9;</entry></row><row><entry namest="col1" nameend="col1" align="left">f6 = d5_i xor X10(q) xor f2;</entry><entry namest="col2" nameend="col2" align="left">f14 = d13_i xor X2(q) xor f3 xor f10;</entry></row><row><entry namest="col1" nameend="col1" align="left">f7 = d6_i xor X9(q) xor f3;</entry><entry namest="col2" nameend="col2" align="left">f15 = d14_i xor X1(q) xor f4 xor f11;</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">f8 = d7i xor X8(q) xor f4;</entry><entry namest="col2" nameend="col2" align="left">f16 = d15_i xor X0(q) xor f5 xor f12.</entry></row></tbody></tgroup></table></tables>

During a synchronous DMA burst for a write command, as the host <b>35</b> sends each data word, it also calculates its 16-bit CRC value in the manner described above. Similarly, as the disk drive <b>32</b> receives each data word, it calculates its 16-bit CRC value. When the host <b>35</b> is finished transferring data words at the end of the synchronous DMA burst, the host <b>35</b> sends its calculated CRC value over the ATA bus <b>34.</b> Upon receipt of the host's CRC value, the disk drive <b>32</b> exclusive-or's the received CRC value with its own calculated CRC value, and checks to see if the result is zero. If a zero result is obtained, no error is reported. A non-zero result however, indicates an error, which is reported to the host by setting of an error bit in an error register at the disk drive <b>32.</b>

A similar procedure is carried out during a synchronous burst for a read command. As the disk drive <b>32</b> sends each data word over the ATA bus <b>34</b> to the host <b>35,</b> the disk drive <b>32</b> calculates its CRC value. Similarly, as the host <b>35</b> receives each data word, it calculates its CRC value. However, at the end of the synchronous DMA burst when the disk drive <b>32</b> is finished transferring data words, it does not send its calculated CRC value to the host <b>35.</b> Instead, as in the case of the write command, the host <b>35</b> sends its calculated CRC value over the ATA bus <b>34</b> to the disk drive <b>32,</b> which then performs the exclusive-or and zero check described above.

Preferably, the parallel CRC check performed during the synchronous DMA burst is transparent to software drivers for peripheral drive devices of existing ATA systems. When a synchronous DMA burst bit error is detected using the parallel CRC approach, bits 2 and 7 of the current ATA Error Register are set. Bit 7 is currently a reserved bit of the ATA Error Register and is redefined as an Interface Error bit under the present synchronous DMA burst protocol. Bit 2 is an Aborted Command bit and is set so that the current ATA software drivers will detect and respond to this "new" error. Thus, the parallel CRC check performed during the synchronous DMA burst protocol of the present invention is backwardly compatible with existing software drivers.

Those skilled in the art would recognize that other error detection approaches can be implemented using a 16-bit register in a similar fashion. For example, if it were desired to detect symbol oriented burst errors, a 16-bit symbol Reed-Solomon ECC can be calculated in a known manner. Another approach for checking data integrity, can be to implement a parity check at the termination of each synchronous DMA burst.

Operation of an embodiment of the synchronous DMA burst transfer method of the present invention will now be discussed with reference to Fig. 9 which shows a simplified flowchart for performing a synchronous DMA burst transfer. Each of the steps shown in the flowchart of Fig. 9 is carried out according to the timing restrictions detailed above with reference to the individual steps of the method. A synchronous DMA burst is initiated in response to receipt and decoding of a host read or write command <b>901</b> by the disk drive. The disk drive always initiates the synchronous DMA burst by asserting DMARQ <b>902</b> when it is ready to start the burst. The host must be ready to proceed with the synchronous DMA burst before the burst can be carried out, so a determination whether the host is ready <b>903</b> is made. If the host is not ready, the burst is not started and the disk must continue to check if the host is ready. If the host is ready, as indicated by assertion of -DMACK, the method proceeds along path A or B depending on whether a host write or read command was decoded. For a write command, the host deasserts STOP <b>905</b> to indicate that the transfer can proceed. In response to the host's deassertion of STOP, the disk drive asserts -DMARDY <b>907</b> to indicate to the host that it is ready to accept data. After the host sees -DMARDY, the host drives a data word on the bus, and calculates a 16-bit CRC value <b>909.</b> The host then toggles the strobe signal 911 after driving the data word on the bus and seeing that the disk drive is ready. After the data is latched by the toggling of the strobe signal, the disk drive calculates its 16-bit CRC value 913. Then, it is determined whether the burst is to be terminated <b>915</b>. If there is still more data to be transferred, the method loops back to the steps of the host driving data and calculating the CRC value <b>909,</b> the host toggling the strobe signal <b>911,</b> the disk drive calculating its CRC value <b>913,</b> then determining whether the burst is to be terminated <b>915.</b> This loop is repeated until it is determined that the burst is to be terminated. Termination is performed in the manner described above with reference to Figs. 6a, 6b, 7a and 7b. Once termination is detected, the host sends its calculated CRC value <b>916</b> to the disk drive and the disk drive compares the received CRC value with its calculated CRC value <b>917,</b> in the manner detailed above. The completion of the CRC comparison indicates the end of the synchronous DMA burst <b>918.</b>

Referring back to when it is determined that the host is ready <b>903</b> to proceed with the synchronous DMA burst, path B is followed if the host command was a read command. The host deasserts STOP <b>904</b> to indicate that the transfer is to proceed, and also asserts -DMARDY <b>906</b> to indicate that it is ready to accept data. After the disk drive sees STOP and -DMARDY from the host, the disk drive drives the data word on the bus, and calculates a 16-bit CRC value. Then the disk drive toggles the strobe signal <b>910.</b> After latching the data word in the host by the toggling of the strobe signal, the host calculates its 16-bit CRC value. After the calculation of the 16-bit CRC value by the host, the method proceeds in a manner similar to that for the case of a write command, where it is determined whether the burst is to be terminated <b>914,</b> the disk drive continues to drive data, calculates the CRC value <b>908,</b> and toggle the strobe signal <b>910,</b> and the host calculates its CRC value until a termination is detected. Once termination is detected, the same steps that were described with reference to a write command termination are performed. That is, the host sends its calculated CRC value <b>916</b> to the disk drive and the disk drive performs a CRC comparison <b>917,</b> and the completion of the CRC comparison indicates the end of the synchronous DMA burst <b>918.</b>

The versions of the present invention have been described with reference to performing a single synchronous DMA burst for transferring one or more data words. However, since a host read or write command can require the performance of a series of synchronous DMA bursts, those skilled in the art will recognize that the above described versions of performing the synchronous DMA burst are repeated until the host read or write command is completed. The disk drive <b>32</b> must initiate the second/additional synchronous DMA burst, the host <b>35</b> must indicate that it is ready to start the burst, and so on, as described above.

The versions of the present invention described above are easily implemented in existing systems with an ATA interface without the need for additional signal lines or electrical changes to the ATA bus. The synchronous DMA burst transfer can be carried out in existing systems by using the current signal lines and redefining some of the current ATA signal lines to provide new functions. In particular, the IORDY signal used for PIO flow control and the -DIOR used for read commands in the prior art transfer protocols have been redefined. For write bursts, -DIOR is used as the STROBE signal and IORDY is used as the -DMARDY signal in the synchronous DMA protocol. For read bursts, -DIOR is used as -DMARDY signal and IORDY is used as the STROBE signal in the synchronous DMA protocol. Lastly, the -DIOW signal of the prior art transfer protocols has been redefined as the STOP signal in the present method. Additionally, the DMARQ and -DMACK signals remain unchanged to ensure backward compatibility with the existing transfer protocols.

Furthermore, very few hardware components are needed for proper termination of existing ATA bus configurations to enable implementation of the synchronous DMA burst transfer protocol of the present invention. Typically, the disk drive end of the ATA bus should be terminated with a series resistor in the range of about 47 to about 100 ohms. Preferably a series resistor of about 82 ohms should be used. Additionally, capacitors of less than about 10 pF can be added to ground on these lines. For any bidirectional lines and data driven lines, a series resistor in the range of about 22 to about 47 ohms is typically included. Similarly, on the host end of the ATA cable, a series resistor in the range of about 47 to about 100 ohms is included, and lines driven by the host are typically terminated with a series resistor in the range of about 22 to about 47 ohms. For both the disk drive end and the host end of the cable, the resistors are preferably placed as close to the ATA connector as possible. Additionally, the terminations are preferably chosen such that the capacitance received through the termination circuits is less than about 25 pF, and such that the rise and fall times of the signal lines are about 5 or more ns. These values are consistent with those currently recommended for ATA systems today.

Additionally, hardware required for the described 16-bit parallel CRC error detection logic can also be easily implemented using conventional circuitry. Preferably, the 16 1-bit registers used for holding the CRC value as it is being calculated can be implemented with 16 conventional flip-flops operatively connected in parallel. Further, the combinational logic components or blocks of the CRC logic encoder/decoder <b>40</b> can be constructed using conventional logic gates which implement the exclusive-or'ing operations as described above.

The synchronous DMA burst transfer method of the present invention provides several advantages over the prior art transfer methods. The present method provides an inexpensive way to get around the inadequate cabling structure and unreasonable termination inherent to the ATA bus <b>34</b> to obtain an increased data transfer rate of approximately 33.3 MBytes/sec. The present method can be implemented in existing ATA bus <b>34</b> configurations with a small number of additional gates. Additionally, the synchronous DMA burst transfer method is implemented using existing signal lines of the ATA bus <b>34</b> and redefining existing signal lines such that the present method is backwardly compatible with existing transfer protocols. A further advantage of the present method is that the synchronous DMA burst protocol provides an increased data transfer rate without increasing the control signal transmission strobe rate of the ATA bus <b>34,</b> so that signal integrity is maintained. A still further advantage of the present invention is that it includes a procedure for parallel bit error detection which is transparent to existing software drivers of the ATA system, so that the present invention is backwardly compatible with the existing software drivers, but with greater data integrity.

Having thus described the invention in considerable detail with reference to certain preferred embodiments thereof, it will be appreciated that other embodiments are possible. It will be understood by those skilled in the art that many changes in construction and circuitry and applications of the invention will suggest themselves without departing from the scope of the invention as defined in the appended claims.