EP0803997A2

A method and arrangement for producing a clock frequency in a radio device

Abstract

In a radio device, which contains a radio frequency part (1) for transmitting or receiving on several optionally selectable radio channels, each being assigned a frequency band, and a control part or similar part (2, 3) that requires at least one clock frequency for its operation, according to the present invention, for each radio channel, a corresponding frequency is assigned having no harmonic frequency within the frequency band of said radio channel, and said assigned corresponding clock frequency is produced as a response to the selection of a radio channel. An arrangement according to the present invention includes means (5) for producing a clock frequency from several optionally selectable clock frequencies that are selected so that for each radio channel there exists at least one clock frequency having no harmonic frequency that coincides with the frequency band of said radio channel, means (6) for assigning such a clock frequency corresponding to each radio channel and means (3, 6) for controlling the means (5) for producing a clock frequency as a response to the selection of a radio channel, to produce said assigned corresponding clock frequency. The optionally selectable clock frequencies are advantageously produced by means of a programmable phase-locked synthesizer (5), in which a synthesized frequency (CLK) divided by a first divisor (N) is locked to a reference frequency (fref) divided by a second divisor (R), and into which the stored divisors corresponding to the radio channels can be programmed to produce the assigned clock frequency.

EP0803997A2, drawing sheet 1
Sheet 1 of 4

Term

Term ended

Projected expiry passed 22 April 2017, 9.4 years ago.

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10 claims: 4 independent, 6 dependent

  1. 1
    A method for producing a clock frequency in a radio device, which includes:a radio frequency part (1) for transmitting or receiving on several optionally selectable radio channels, each of which is assigned a frequency band, a base frequency part (2) that requires a clock frequency for timing of its operation, characterized in that, in said method: corresponding to each radio channel a clock frequency is assigned having no harmonic frequency that is within the frequency band of said radio channel, and in response to the selection of a radio channel said assigned corresponding clock frequency is produced.
  2. 5
    An arrangement for producing a clock frequency in a radio device, which includes:a radio frequency part (1) for transmitting or receiving on several optionally selectable radio channels, each of which is assigned a frequency band, a base frequency part (2) that requires a clock frequency for timing of its operation, characterized in that, said arrangement includes: means (5) for producing a clock frequency from several optionally selectable clock frequencies that are selected so that a clock frequency corresponding to each radio channel exists that has no harmonic frequency within the frequency band of said radio channel, means (6) for assigning a clock frequency for each radio channel that has no harmonic frequency within the frequency band of said radio channel, and means (3, 6) for controlling the means (5) for producing a clock frequency in response to the selection of the radio channel, to produce the clock frequency assigned for the radio channel.
  3. 8
    The arrangement according to one of the claims 5 - 7, characterized in that the means (5) for producing a clock frequency include a frequency synthesizer based on a phase-locked loop, which receives a reference frequency (f ref ) and outputs a synthesized clock frequency (CLK) and includes:a first programmable frequency divider (13), that has a first programmable divisor (R), a second programmable frequency divider (12), that has a second programmable divisor (N), and a phase comparator (14), and in which the reference frequency (f ref ) is connected to the phase comparator (14) via the first programmable frequency divider (13) and the synthesized clock frequency (CLK) is connected to the phase comparator (14) via the second frequency divider (12).
  4. 10
    The arrangement according to claims 8 or 9, characterized in that it includes stored information (6) by which corresponding divisors (N, R) are connected to one or more radio channels (CHn), which divisors are programmed into the dividers (12, 13) of the synthesizer to produce the assigned clock frequency.