Viterbi decoding method and circuit therefor

0001The present invention relates to a Viterbi decoding method and a circuit therefor, and more particularly, to a Viterbi decoding method which is applied for high-speed and high-density recording/reproducing of digital information and a circuit with a simple hardware therefor.

0002Recently, a recording/reproducing apparatus adopting a digital mode has been widely used. In the apparatus, analog video and audio signals are converted into digital signals, and recorded on a magnetic recording medium through source encoding and channel encoding processes. The digital signal recorded on the magnetic recording medium is reproduced through channel decoding and source decoding processes.

0003Figure 1 is a block diagram of a signal processing system in a digital videocassette recorder.

0004In Figure 1, analog video and audio signals are converted into digital signals in first and second analog-to-digital (A/D) converters 110 and 120, respectively. The video data are compressed by a high-efficiency code in a video data encoder 130 and then output to an error-correction encoder 140. The error-correction encoder 140 synthesizes the video data output from the video data encoder 130 and the audio data passed through the second A/D converter 120, and adds a parity to the data using an error correction code such as a Reed Solomon (RS) code to output the result to a recording encoder 150. The configuration of the recording encoder 150 is shown in Figure 2.

0005A channel modulator 151 shown in Figure 2 modulates the error-correction-coded data output from the error-correction encoder 140 shown in Figure 1, using an 8-to-14 or 24-to-25 modulation scheme. A precoder 152 converts the channel-modulated data into a non-return-to-zero inversion (NRZI) code. A recording compensation circuit 153 including a recording equalizer equalizes the NRZI code so as to compensate for the deterioration of recording characteristics and outputs the result to a recording amplifier 160 shown in Figure 1. Here, the recording equalizer may not be included in the recording compensation circuit 153.

0006The recording amplifier 160 amplifies the output signal of the recording encoder 150, and a recording magnetic head (HD1) records the amplified signal on a magnetic tape (T).

0007On the other hand, the signal recorded on the magnetic tape is read out by a playback magnetic head (HD2) and amplified by a playback amplifier 210. Then, a data detector 220 detects video and audio data from the amplified signal. The internal structure of the data detector 220 having a reproduction equalizer is shown in Figure 3.

0008An automatic gain control (AGC) amplifier 221 shown in Figure 3 adjusts the amplitude of the signal amplified by the playback amplifier 210 shown in Figure 1. A low-pass filter 222 filters the signal output from the AGC amplifier 221 to remove any high-frequency noise. Then, an A/D converter 223 converts the low-pass-filtered signal into digital data, and an equalizer 224 compensates for distortion in the waveform and level of the digital data and outputs the result to a Viterbi decoding circuit 226. A timing detector 225 detects a predetermined frequency of the equalized signal output from the equalizer 224 and a timing of the reproduced signal using a phase-locked loop (PLL) circuit (not shown) included therein, and outputs a sampling clock for the A/D converter 223 and a driving clock (not shown) for each portion of the reproducing circuit. The Viterbi decoding circuit 226 Viterbi-decodes the equalized data. A channel decoder 227 decodes the Viterbi-decoded data based on the abovementioned modulation scheme and outputs the result to an error-correction decoder 230 shown in Figure 1.

0009The error-correction decoder 230 corrects the errors of the video and audio data output from the data detector 220, and a video data decoder 240 decodes the video data output from the error-correction decoder 230. Then, the video and audio signals are restored in first and second digital-to-analog converters 250 and 260, respectively.

0010Meanwhile, for increasing the recording density of a signal without a significant change in the characteristics of the conventional recording/reproducing system, technologies related with partial response maximum likelihood, including a Viterbi decoding process, has been advanced, and a lot of specific circuits have been suggested.

0011An application example of the Viterbi decoding process using the NRZI code having two states is shown in Figure 4A. In Figure 4A, reference numerals 152 and 226 represent a precoder and Viterbi decoding circuit, respectively, wherein the reference numerals are the same as those given to the precoder and Viterbi decoding circuit shown in Figures 2 and 3.

0012In Figure 4A, the precoder 152 is constituted of a delay 11 and a modulo-2 adder 12 which consists of an exclusive OR gate, and converts the input data into the NRZI code. This precoder 152 is called "1T precoder" or "PR(1,-1) type system."

0013A magnetic recording/reproducing channel 200 has a differential characteristic (1-D). An adder 201 is included for mathematical modelling of additive Gausian noise introduced in the channel. A channel output y_k overlapped with noise n_k can be represented by equation (1), and the channel output y_k is input to the Viterbi decoding circuit 226 to obtain decoded output c_k.<maths id="math0001" num="(1)"><math display="block"><mrow><msub><mrow><mtext>y</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext> = z</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext> + n</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext> (if n</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>=0, y</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>=z</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0802634B1_D0001.tif" /></maths>

0014Thus, in Figure 4A, a_k is input data (binary coded information which is -1 or 1) at time <i>k</i>, D is a delay operator for 1-bit delay, b_k is output data of the precoder 152 at time <i>k</i>, z_k is output data of the magnetic recording/reproducing channel 200 which introduces no noise, (1-D) is the differential characteristic of the magnetic recording/reproducing channel 200, n_k is a noise which is being overlapped to the data in the channel, y_k is an input signal of receiving port of a Viterbi decoding circuit 220, and c_k is the decoded data.

0015Figure 4B is a state diagram for the precoder 152, wherein arrows represent allowable transition from one state to another or to itself. And, <i>S</i> indicates a state of the precoder.

0016The process of obtaining the decoded data, when the data a_k (-1 or 1) is being input to the precoder 152, is summarized in Figure 5A.

0017Figure 5B schematically shows the channel output y_k input to the receiving port of the Viterbi decoder when no noise is overlapped in the channel and Figure 5C is a trellis diagram showing the state transition of y_k.

0018However, some noise is overlapped in the output signal of the equalizer 224 which is input to the Viterbi decoding circuit 226 shown in Figure 3. Here, the noise results primarily from the granularity of the particles on a tape, a head impedance and an initial bias resistance of a playback amplifier and the like. Since the reproduced signal overlapped with noise pass through various devices such as playback head HD2, playback amplifier 210, equalizer 224, etc., the spectra of the input signal and overlapped noise are varied when they reach the Viterbi decoding circuit 226.

0019As shown in Figure 6A, the actual waveform of input signal to the Viterbi decoding circuit is an analog waveform in which the input data and the overlapped noise cannot be completely separated and identified from one another.

0020Thus, positive direction amplitude of the normalized inputs (+1, 0, -1) is quantized as one of two values "H" and "L" by an H_n detecting comparator (not shown). Here, the output H_n of the H_n detecting comparator outputs "H" when the input signal is above the threshold "+1", and the output H_n of the H_n detecting comparator outputs "L" when the input signal is below the threshold "+1".

0021In the same manner, negative direction amplitude of the normalized inputs (+1, 0, -1) is quantized as one of two values "H" and "L" by L_n detecting comparator (not shown). Here, the L_n is "H" when the input signal is below the threshold "-1", and the L_n is "L" when the input signal is above the threshold "-1".

0022Here, due to the differential characteristic (1-D) of the magnetic recording/reproducing channel and the decoding circuit of the partial response type PR(1,-1), "0"(H_n=L) or "-1"(L_n=H) is read out after "+1"(H_n=H) if no noise is overlapped. That is, "+1" is never read out after "+1". Similarly, "0"(L_n=L) or "+1"(H_n=H), not "-1"(L_n=H), is read out after "-1"(L_n=H).

0023Figure 6B is a trellis diagram of binary states illustrating operation of the Viterbi decoding circuit which receives the signal shown in Figure 6A.

0024On the contrary, as shown in Figure 7A, when noise is overlapped in the channel output which is input to the Viterbi decoding circuit, the above described principle may not be satisfied.

0025Figure 7A shows an example of error due to the noise, in the sense that "+1" is detected again at k=5 after "+1" is detected at k=3.

0026Since the decoding circuit is of the partial response type PR(1, -1), it can be said, based on the above-described principle, that the signal is corrupted by noise when "+1" is read out after "+1" or "-1" is read out after "-1" regardless of zeros therebetween.

0027Here, during the Viterbi decoding process, as an index for determining what the detected data is precisely or which pass through the trellis diagram is most probable, metrics for each path are calculated to select a surviving path, and information of the surviving path is stored in a memory. As a result, the input data is decoded by reading data of a final surviving path from the memory. For this process, devices such as an A/D converter, a microprocessor, an adder, etc., are required.

0028However, if the states are binary, a peak value of the signal in the positive direction (hereinafter, simply "positive peak") and a peak value of the signal in the negative direction (hereinafter, simply "negative peak") basically correspond to the metrics. Thus, it is preferable to design a circuit which can detect the positive peak of the signal for maintaining the level of that value as a new threshold to detect consecutive positive peaks, and for updating a threshold for detecting the negative peak.

0029Here, the new threshold for detecting the negative peak should be lower than the threshold for detecting the positive peak by a predetermined value A.

0030If a circuit is constituted as above, the minimum distance of the metric is determined when the negative peak is detected after the detection of the positive peak. Further, a path, on the trellis diagram, to a time point of the previous positive peak which is the nearest from the negative peak, is determined at that moment. That is, a path having the minimum metric value is selected.

0031Similarly, the negative peak is detected and maintained. The detected value is set as a new threshold for detecting "-1" and simultaneously used to correct the "+1" detection threshold which is higher than "-1" detection threshold by the offset value A, for preparing the detection of the next positive peak or the next negative peak of the input signal.

0032A research for the interlocking of peak-to-peak value of the input signal with a predetermined offset value between the "-1" and "+1" threshold values is described in an article entitled <i>"signal processing method PRML, achieving large capacity memory device of</i> the next <i>generation"</i> in <i>Japan Nikkei Electronics</i>, No. 599, pp. 72-97, Jan., 1994.

0033An article "Dynamic threshold implementation of the maximum - likelihood detector for the EPR4 channel" by K.J. Knudson, J.K. Wolf and L.B. Milstein presented at IEEE Global Telecommunications Conference 1991; Vol 3, pp. 2135-2139, Dec., 1991 describes a dynamic threshold method for Viterbi detection using eight thresholds. the thresholds are grouped into four threshold pairs, where the distance between the thresholds in each pair is constant, and the article gives an algorithm for updating the thresholds and their interdependence based on three parameters. The threshold updating depends on the current thresholds and the current received sample, and on part thresholds and part received samples. The three parameters are defined in terms of state metrics.

0034An article "A block processing method for designing high-speed Viterbi detectors"" by H.K. Tahpar and J.M. Cioff; presented at IEEE International Conference on Communications 1989, Vol. 2, pp. 1096-1100, June, 1989 describes a block processing method for the Viterbi algorithm, and an implementations for such a block processing method including a modular layered architecture requiring replication and suitable interconnection of a plurality of add-compare-select modules for backward recursion. The achievable data rate may be increased by adding more layers of modules at the cost of increased hardware requirements.

0035Referring to Figure 8, the structure of the conventional Viterbi decoding circuit will be described. Figure 8 shows a typical Viterbi decoding circuit which is described in articles entitled <i>"Optimal Reception for Binary Partial</i> Response <i>Channels"</i> by <i>M.J.Ferguson</i> in <i>Journal of Bell Syst. Tech. J</i>., 51(2), pp. 493-505, Feb., 1972, and <i>"Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel"</i> by <i>R.W.Wood</i> and <i>D.A.Petersen</i> in <i>IEEE Trans. Comm</i>., Vol. Com-34, No. 5, pp. 454-461, May, 1986.

0036In Figure 8, the input signal, which is quantized in an analog-to-digital (A/D) converter (not shown), is input to an adder 232 as data of -2, 0 or +2. A sample-hold device 231 updates or holds the input data depending on a signal output from an exclusive OR gate 235. That is, when the state of the input data is changed, the input data is updated, however, when the input data is not changed, the input data is held without change.

0037When the exclusive OR gate 235 outputs "1", which represents a change in state of the input data, the output of an exclusive OR gate 236 is written in a point address of a RAM 243 as "+1(H)", the point address being counted by an address counter 240 via a point register 241. Also, when the output of the exclusive OR gate 235 is "0", "-1(L)" is written in an address of the RAM 243, the address being counted by the address counter 240. Thus, the decoded data is accumulated in the RAM 243.

0038Here, it is preferable that an original input data a_k and a decoded data c_k of the NRZI are decoded as "+1(H)" and "-1(L)" when the state S is changed and unchanged on the trellis diagram, respectively, as shown in Figure 7B. Thus, in the latter case, the decoded result is written in the RAM 243 as "-1(L)" unconditionally.

0039On the other hand, as each new divergent point is established, one of the two existing paths is terminated. That is, each divergent point represents a new ambiguous bit as well as a point where some preceding ambiguity is settled. Thus, if the path diverges at time P, a final surviving path from the previous time p is determined at the next divergent point. Here, a transition of the state S at time p is known and then "+1(H)" or "-1(L)" is written in the address p of the RAM 243 in response to the state transition.

0040Also, when performing the Viterbi decoding on the trellis diagrams, it is required to compute the metric at each divergent point using a microprocessor and to store the result.

0041Thus, an A/D converter and a microprocessor (CPU) which are not shown here as well as the RAM and the address counter are needed for the above structure.

0042As described above, when constructing the Viterbi decoding circuit using a RAM, an A/D converter and a digital signal processor including a microprocessor, a digital adder, etc. are required.

0043When the Viterbi decoding circuit is made into an integrated circuit (IC), chip size increases due to the addition of the A/D converter and the digital signal processor and the manufacturing cost increases as well. Particularly, 64 comparators should be installed in a 6-bit flash type A/D converter adopted in a conventional Viterbi decoding circuit, thereby increasing the chip area.

0044With a view to solving or reducing the above problem, it is an aim of preferred embodiments of the present invention to provide a Viterbi decoding method in which a Viterbi decoding is performed from right to left (reverse direction) in the trellis diagram, so that the Viterbi decoding can be performed simply without the complicated operations which are performed at every divergent point in the conventional method.

0045It is another aim of embodiments of the present invention to provide a Viterbi decoding circuit with a simple hardware by adopting a shift register memory (shift register) as a main circuit component instead of an A/D converter and microprocessor for a metric operation.

0046According to a first aspect of the invention, there is provided a Viterbi decoding method for decoding an input signal comprising the steps of: (a) detecting instantaneous values of negative and positive peak data as alternatives of metrics from the input signal; (b) grouping the detected instantaneous values by a predetermined time and outputting grouped positive and negative peak data; (c) converting the grouped positive and negative peak data in the reverse direction and outputting reverse positive and negative data; (d) Viterbi-decoding the positive and negative peak data with respect to initial states of a predetermined number and outputting the reverse decoded data of a predetermined number of channels; (e) converting the reverse decoded data of each channel into forward direction and outputting the forward decoded data of channels of a predetermined number; and (f) selecting one of the forward decoded data of the channels based on the states of initial decoded data of the next group and outputting the selected data as a final decoded data.

0047Preferably, said step (f) comprises the step of delaying forward decoded data of a predetermined number of channels until the state of the initial decoded data of the next group is determined.

0048Said predetermined number of channels may be two.

0049Preferably, the number of bits in each group is determined by a digital modulation method.

0050According to a second aspect of the invention, there is provided a Viterbi decoding method for demodulating a reproduced signal in a magnetic recording/reproducing apparatus comprising the steps of: <ul id="ul0001" list-style="none"><li>(a) comparing the reproduced signal with each of positive and negative peak thresholds to obtain binary encoded data in the positive (positive peak data) and negative (negative peak data) amplitude directions;</li><li>(b) grouping the positive and negative peak data by a predetermined time and outputting grouped positive and negative peak data;</li><li>(c) Viterbi-decoding the grouped positive and negative peak data and outputting the Viterbi-decoded data; and</li><li>(d) concatenating final decoded data of the present group and initial decoded data of the next group to de-group the decoded data.</li></ul>

0051Said step (c) may comprise the steps of: <ul id="ul0002" list-style="none"><li>(c1) converting the grouped positive and negative peak data in the reverse direction and outputting reverse positive and negative peak data;</li><li>(c2) Viterbi-decoding the reverse positive and negative peak data with respect to two initial states and outputting reverse decoded data of two channels; and</li><li>(c3) converting the reverse decoded data of two channels in the forward direction and outputting forward decoded data of two channels.</li></ul>

0052Said step (d) may comprise the steps of: <ul id="ul0003" list-style="none"><li>(d1) determining a state of initial decoded data of the next group connected to the final decoded data of the present group; and</li><li>(d2) selecting one of the forward decoded data of two channels based on the determined state value to de-group the decoded data.</li></ul>

0053Said step (c) may further comprise the step of (c4) delaying the forward decoded data of two channels until the state value of first decoded data of the next group is determined.

0054The number of bits in each group is preferably determined by a digital modulation method.

0055According to a third aspect, there is provided a Viterbi decoding circuit for decoding an input signal comprising: <ul id="ul0004" list-style="none"><li>detecting means for detecting instantaneous values of positive and negative peaks as alternatives of metrics from the input signal;</li><li>first converting means for grouping the detected instantaneous data by a predetermined time and converting grouped positive and negative peak data in the reverse direction to output reverse positive and negative peak data;</li><li>Viterbi decoding means for Viterbi-decoding the reverse positive and negative peak data with respect to initial states of a predetermined number to output reverse decoded data of a predetermined number of channels, and for outputting a selection control signal based on the state of initial decoded data of the next group connected to final decoded data of the present group;</li><li>second converting means for converting the reverse decoded data of the predetermined number of channels in the forward direction and outputting forward decoded data of the predetermined number of channels; and</li><li>selecting means for selecting one of forward decoded data of the predetermined number of channels responding to the selection control signal and outputting a final decoded data.</li></ul>

0056The number of channels is preferably two.

0057Said first converting means preferably comprises a serial-input/parallel-output type shift register memory and a parallel-input/serial-output type shift register memory.

0058Said second converting means preferably comprises a serial-input/parallel-output type shift register memory and a parallel-input/serial-output type shift register memory.

0059Said Viterbi decoding means preferably comprises: <ul id="ul0005" list-style="none"><li>an initial state setting circuit for setting first and second initial states for each group;</li><li>a first decoding logic circuit for performing a logic operation with respect to the first initial state and the reverse positive and negative peak data, respectively, to output a first reverse decoded data Viterbi-decoded with respect to the first initial state;</li><li>a second decoding logic circuit for performing a logic operation with respect to the second initial state and the reverse positive and negative peak data, respectively, to output a second reverse decoded data Viterbi-decoded with respect to the second initial state; and</li><li>a selection control signal generating circuit for generating a selection control signal based on the decoded value of the initial decoded data of the next group connected to the final decoded data of the group output from said first decoding logic circuit.</li></ul>

0060Said selecting means may comprise: <ul id="ul0006" list-style="none"><li>first and second shift registers for delaying the forward decoded data of two channels until the selection control signal is generated; and</li><li>a switching device for selecting one of the outputs of said first and second shift registers according to the selection control signal.</li></ul>

0061Preferably, the number of bits in each group is determined by a digital modulation method.

0062According to a further aspect of the invention, there is provided a Viterbi decoding circuit for demodulating a reproduced signal in a magnetic recording/reproducing apparatus comprising: <ul id="ul0007" list-style="none"><li>peak detecting means for interlocking positive and negative peak detecting thresholds to maintain the difference between two thresholds as a predetermined offset value and detecting instantaneous values of positive and negative peaks of the reproduced signal to output positive and negative peak data;</li><li>first reverse converting means for grouping positive peak data output from said peak detecting means by a predetermined time and converting the grouped positive peak data in the reverse direction to output a reverse positive peak data;</li><li>second reverse converting means for grouping negative peak data output from said peak detecting means by a predetermined time and converting the grouped negative peak data in the reverse direction to output a reverse negative peak data;</li><li>Viterbi decoding means for Viterbi-decoding the reverse positive and negative peak data output from said first and second reverse converting means with respect to the first and second initial state values to output reverse decoded data of two channels, and for outputting a selection control signal based on the state of the initial decoded data of the next group connected to the final decoded data of the present group;</li><li>first forward converting means for converting reverse decoded data which is decoded with respect to the first initial state in the forward direction to output a first forward decoded data;</li><li>second forward converting means for converting a second reverse decoded data which is decoded with respect to the second initial state value in the forward direction to output second forward decoded data; and</li><li>selecting means for selecting one of first and second forward decoded data responding to the selection control signal to output the selected decoded data.</li></ul>

0063The circuit may further comprise an amplifier for amplifying the reproduced signal to output the amplified signal to said peak detecting means.

0064Said peak detecting means preferably comprises two comparators for comparing the reproduced signal with positive and negative peak thresholds, respectively, to output encoded binary data in the positive (positive peak data) and negative (negative peak data) amplitude directions.

0065Said first and second reverse converting means may comprise a serial-input/parallel-output type shift register memory and a parallel-input/serial-output type shift register memory.

0066Said first and second forward converting means may comprise a serial-input/parallel-output type shift register memory and a parallel-input/serial-output type shift register memory.

0067Said Viterbi decoding means may comprise: <ul id="ul0008" list-style="none"><li>an initial state setting circuit for setting first and second initial states for each group;</li><li>a first decoding logic circuit for performing a logic operation with respect to the first initial state and the reverse positive and negative peak data, respectively, to output a first reverse decoded data Viterbi-decoded with respect to the first initial state;</li><li>a second decoding logic circuit for performing a logic operation with respect to the second initial state and the reverse positive and negative peak data, respectively, to output a second reverse decoded data Viterbi-decoded with respect to the second initial state; and</li><li>a selection control signal generating circuit for generating a selection control signal based on the decoded value of the initial decoded data of the next group connected to the final decoded data of the group output from said first decoding logic circuit.</li></ul>

0068Said selecting means preferably comprises: <ul id="ul0009" list-style="none" compact="compact"><li>first and second shift registers for delaying the first and second forward decoded data until the selection control signal is generated; and</li><li>a switching device for selecting one of the outputs of said first and second shift registers responding to the selection control signal.</li></ul>

0069For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: <ul id="ul0010" list-style="none"><li>Figure 1 is a block diagram of a signal processing system in a digital videocassette recorder;</li><li>Figure 2 is a diagram showing an example of the internal structure of a recording encoder shown in Figure 1;</li><li>Figure 3 is a diagram showing an example of the internal structure of a data detector shown in Figure 1;</li><li>Figure 4A is a diagram showing an example of the Viterbi decoding process using the NRZI code and Figure 4B is a state diagram of the precoder in Figure 4A;</li><li>Figure 5A is a table showing the decoding process, Figure 5B is a channel output diagram and Figure 5C is a trellis diagram in which the state transition of channel output is shown;</li><li>Figure 6A is a diagram showing the input signal of the Viterbi encoding circuit shown in Figure 3, and Figure 6B is a trellis diagram for the Viterbi decoding circuit;</li><li>Figure 7A is a diagram illustrating the input signal of the Viterbi encoding circuit and a correction process of the detection data when noise is overlapped, and Figure 7B is a trellis diagram for the Viterbi decoding circuit;</li><li>Figure 8 is a circuit diagram of a conventional Viterbi decoding circuit;</li><li>Figure 9 is a diagram showing an example of the internal structure of a data detector without the A/D converter;</li><li>Figure 10 is a block diagram of a Viterbi decoding circuit according to embodiments of the present invention;</li><li>Figure 11 is a detailed circuit diagram of the Viterbi decoding circuit shown in Figure 10; and</li><li>Figure 12 is a detailed circuit diagram of an initial state value setting and Viterbi decoder shown in Figure 11.</li></ul>

0070First, according to a Viterbi decoding method of the present invention, the Viterbi decoding is performed in the reverse direction of a state transition diagram, so that paths are joined at each divergent point. As a result, there is no reason for storing metric operation results in a memory according to each state. That is, the operation by the microprocessor and the memory for storing the result are not necessary. Also, the path on the state transition diagram can be determined by an instantaneous value obtained from the detection of a positive or negative peak.

0071The input signal is divided by a predetermined time and grouped. For decoding in the reverse direction, positive and negative peaks of the input signal by a group are detected instead of calculating the metrics and then processed in the reverse direction. The reverse Viterbi-decoded data of two channels are generated at the same time in consideration of the state of initial decoded data of the next group connected to the final decoded data of the present group, and then converted into the forward Viterbi-decoded data. Then, the forward Viterbi-decoded data of the two channels are delayed in parallel until the state of initial decoded data of the next group is determined. When the state of the initial decoded data of the next group is determined, one of the delayed forward Viterbi-decoded data of the two channels is selected to output the decoded data.

0072Figure 9 is a block diagram of the data detector adopting the Viterbi decoding circuit of the present invention. The A/D converter is not employed in the data detector. However, the present invention can be applied to the data detector 220 shown in Figure 3.

0073In Figure 9, an equalizer 310 equalizes the data reproduced from a playback amplifier and outputs the result to a Viterbi decoding circuit 320. A timing detector 330 detects the timing of the reproduced signal from the output of the equalizer 310 and outputs driving clocks required for the equalizer 310 and Viterbi decoding circuit 320 and for other portions which are not shown in Figure 9. The Viterbi decoding circuit 320 performs the Viterbi decoding of the equalized data. A channel demodulator 340 demodulates the Viterbi-decoded data based on the modulation scheme and outputs the result to an error-correction decoder. Here, the equalizer 310 may be either a fixed or adaptive type.

0074Figure 10 is a block diagram of the Viterbi decoding circuit 320 shown in Figure 9 which adopts a shift register as a main component.

0075In Figure 10, an amplifier 321 amplifies the equalized signal output from the equalizer 310 shown in Figure 9.

0076A peak detector 322 interlocks the positive and negative peak detection thresholds to maintain the difference between the above two thresholds as an offset value A. While maintaining the difference, the peak detector 322 detects the positive and negative peaks of the signal amplified from the amplifier 321.

0077A first reverse direction converter 323 groups positive peak data H_n output from the peak detector 322 by a predetermined number of bits (here, 8 bits), and then performs the reverse direction converting for the grouped data to detect the positive peak data in the reverse direction.

0078A second reverse direction converter 324 groups negative peak data L_n output from the peak detector 322 by a predetermined number of bits (here, 8 bits), and then performs the reverse direction converting for the grouped data to detect the negative peak data in the reverse direction.

0079An initial state setting and Viterbi decoding circuit (hereinafter referred to as only "decoder") 325 receives the reverse positive and negative peak data H_n' and L_n' output from the first and second reverse direction converters 323 and 324, decodes the data under the initial condition of two states (S₁=1 and S₀=-1), and then outputs decoded data c_k1' and C_k2' to two separate channels. Further, the decoder 325 outputs a selection control signal SEL based on the state of the initial decoded data of the next group following the final decoded data of the present group.

0080A first forward direction converter 326 converts the positive peak data in the reverse direction c_k1' which was decoded under the initial condition of S₁=1 and output from the decoder 325, into the forward direction to output a forward decoded data c_k1.

0081A second forward direction converter 327 converts the negative peak data in the reverse direction c_k0' which was decoded under the initial condition of S_o=-1 and output from the decoder 325, into the forward direction to output a forward decoded data c_k0.

0082A selector 328 delays the forward decoded data c_k1 and c_k0, output from the first and second forward direction converters 326 and 327, until the state of the initial decoded data of the next group is determined. And then, the selector 328 selects one of the delayed forward decoded data c_k1 and c_k0 which is correct, responding to the selection control signal (SEL) output from the decoder 325, wherein the selection control signal reflects the determined state of the initial decoded data of the next group, to output a decoded data c_k.

0083This block diagram constituted as above addresses the following problems.

0084As can be seen in the trellis diagram shown in Figure 5C, when the signal is decoded from left to right (forward direction) on the trellis diagram, it is necessary to calculate the metric for determining the surviving path at divergent point. Thus, the microprocessor should compute the metrics of various paths at each divergent point. However, when the Viterbi decoding is performed in the reverse direction, that is, from right to left, on the trellis diagram of Figure 5C having two states, the decision made at each state is obviated since there is only one path.

0085For example, as shown in the trellis diagram of Figure 7B, if the signal is decoded from the time k=7 to k=0 in sequence, the correct data can be precisely detected.

0086In this case, it is necessary to check the metric at each state. However, if the positive and negative peaks of the input signal are detected, it is not required to compute the metric by the microprocessor since the positive and negative peak detections correspond to the calculation of the metrics in nature.

0087Thus, if the positive and negative instantaneous peaks are detected as the values corresponding to the metrics and the result is stored as the positive and negative peak data H_n and L_n, the path on the trellis diagram can be determined. For example, when the decoding process starts from the time point where k=7, the state S(7) at k=7 is determined depending on the state <i>S</i>(8) at k=8. Therefore, the decoder 325 generates the reverse Viterbi-decoded data c_k1' and c_k2' in parallel under the assumption that <i>S</i>(8)=<i>S</i>₁=1 and <i>S</i>(8)=<i>S</i>₀=-1, respectively.

0088The reverse decoded data c_k1' based on the initial state S₁ and the reverse decoded data c_k0' based on the initial state S₀ are input to a shift register for alternative conversion to the forward direction in sequence, and then aligned in the forward direction to output the forward decoded data c_k1 and c_k0 processed through the alternative conversion process.

0089Thereafter, until the state <i>S</i>(8) is determined by the decoder 325, the selector 328 delays the forward decoded data c_k1 and c_k0 in parallel. When the state <i>S</i>(8), which is S₁ or S₂, is determined, the selector 328 selects one of the delayed forward decoded data c_k1 and c_k0 to output the decoded data c_k.

0090The Viterbi decoding circuit shown in Figure 10 will be described in detail in relation with Figure 11.

0091In Figure 10, the amplifier 321 is a buffering amplifier that amplifies the input signal to a predetermined signal level required for the peak detector 322.

0092The peak detector 322 includes a comparator COMP1 for detecting the positive peak data H_n and a comparator COMP2 for detecting the negative peak data L_n. The non-inverting port of the comparator COMP1 is commonly connected to a capacitor C1 which is also connected to the output port of the amplifier 321, and to the anode of a diode D1. One port of a capacitor C2 is connected to the cathode of the diode D1 and the other port thereof is commonly connected to a grounded capacitor C3 and the inverting port of the comparator COMP1. The inverting port of the comparator COMP2 is commonly connected to a capacitor C4 which is also connected to the output port of the amplifier 321 and the cathode of the diode D2. One port of a capacitor C5 is connected to the anode of the diode D2 and the other end thereof is commonly connected to a grounded capacitor C6 and the non-inverting port of the comparator COMP2.

0093The peak detector 322 interlocks the thresholds for detection of positive and negative peaks, and maintains the difference between two thresholds at a predetermined offset value A, to stabilize both positive and negative peaks.

0094The first and second reverse direction converters 323 and 324 are formed of a combination of two 8-bit shift registers, i.e., one serial-input/parallel-output type and one parallel input/serial output type, for converting the positive peak data H_n and the negative peak data L_n, respectively.

0095Figure 12 is a detailed circuit diagram of the decoder 325. As shown in Figure 12, in order to set the output Q_A of a RS flip-flop F/F <i>A</i> to "H" corresponding to an initial state <i>S</i>₁, an initial setting pulse is applied to the set input <i>S</i>_A via an OR gate G2. Similarly, to set the output Q_B of a RS flip-flop F/F <i>B</i> to "L" corresponding to an initial state <i>S</i>₀, the initial setting pulse is applied to the reset input R_B via an OR gate G5.

0096Here, the initial set pulse corresponds to a byte pulse generated by 8-bit period. An inverter G7 is provided to invert the initial setting pulse, so that logic high state is not applied to <i>S</i> and <i>R</i> inputs simultaneously.

0097Also, the reverse positive peak data H_n' is applied to the set inputs S_A and S_B of each RS flip-flop F/F A and F/F <i>B</i> via AND gates G1 and G6 according to the clock. Similarly, the reverse negative peak data L_n is applied to the reset inputs R_A and R_B via AND gates G3 and G4 according to the clock.

0098An AND gate G8 performs a logic AND operation of the reverse positive peak data H_n' and the output Q_A of the flip-flop F/F A, and an AND gate G9 performs a logic AND operation of the reverse negative peak data L_n' and the inverting output <maths id="math0002" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">Q</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0802634B1_D0002.tif" /></maths>_<i>A</i>1 of the flip-flop F/F A. An OR gate G10 performs a logic OR operation of the outputs of the AND gates G8 and G9.

0099An AND gate G11 performs a logic AND operation of the reverse positive peak data H_n' and the inverting output <maths id="math0003" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">Q</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0802634B1_D0003.tif" /></maths>_<i>B</i>2 of the flip-flop F/F <i>B</i>, and an AND gate G12 performs a logic AND operation of the reverse negative peak data L_n' and the output Q_B of the flip-flop F/F <i>B</i>. An OR gate G13 performs a logic OR operation of the outputs of the AND gates G11 and G12.

0100Thus, the reverse decoded data c_k1' based on the initial state <i>S</i>₁ is output from the OR gate G10, and the reverse decoded data c_k0' based on the initial state <i>S</i>₀ is output from the OR gate G13.

0101Here, reference numeral 325.1 denotes an initial state setting circuit, reference numeral 325.2 denotes a first Viterbi logic circuit, reference numeral 325.3 denotes a second Viterbi logic circuit, and reference numeral 325.4 denotes a selection control signal generating circuit consisting of a D flip-flop.

0102The first forward direction converter 326 and the second forward direction converter 327 shown in Figure 11 are formed of the combination of two 8-bit shift registers, i.e., one serial-input/parallel output type and one parallel-input/serial-output type, respectively. The reverse decoded data c_k1' and c_k0' based on the initial states S₁ and S₀, respectively, are stored in respective serial-input/parallel-output type shift registers, and transferred to the parallel-input/serial-output type shift registers. When the decoded data are output from the parallel-input/serial-output type registers, they are arranged in the forward direction.

0103The selector 328 is comprised of two shift registers of serial-input/parallel-output type which delay the decoded data c_k1 and c_k0, and a switch SW constituted of a logic circuit for selecting one of the decoded data c_k1 and c_k0 depending on the selection control signal SEL output from the decoder 325.

0104The selection control signal SEL provided to the selector 328 shown in Figure 11 is generated from the flip-flop 325.4 shown in Figure 12. The reverse decoded data c_k1' which are Viterbi-decoded in the initial state S₁ by the decoder 325 and output from the OR gate G10 are input to the input port D of the D F/F. And the initial setting pulse is input to the clock port of the D F/F. The selection control signal SEL controls a switch SW so that the first selection port is selected when the output port Q is logic high and the second selection port is selected when the inverted output <maths id="math0004" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">Q</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0802634B1_D0004.tif" /></maths>3 is logic high.

0105Here, the initial setting pulse and clock required by the decoder 325 are generated from a signal generator (not shown) which generates an intended timing signal by receiving the driving clock output from timing detector 330 shown in Figure 9, or may be generated from timing detector 330 itself.

0106In addition, in order to simplify understanding of the operation of portions shown in Figures 11 and 12, an example of the decoding process will be described referring to the input signal and trellis diagrams shown in Figures 7A and 7B.

0107The input signal y_k is divided by 8-bit and then processed in group units as follows: (y₀, y₁, y₂, y₃, y₄, y₅, y₆, y₇), (y₈, y₉, y₁₀, y₁₁, y₁₂, y₁₃, y₁₄, y₁₅), (y₁₆, y₁₇, y₁₈, y₁₉, y₂₀, y₂₁, y₂₂, y₂₃), ...

0108Thus, the data is input to the decoder 325 in the reverse direction for each group, and output in the reverse direction as follows: (y₇, y₆, y₅, y₄, y₃, y₂, y₁, y₀), (y₁₅, y₁₄, y₁₃, y₁₂, y₁₁, y₁₀, y₉, y₈), (y₂₃, y₂₂, y₂₁, y₂₀, y₁₉, y₁₈, y₁₇, y₁₆), ...

0109The state <i>S</i>(8) at k=8 is determined when a group of signals including the input signal y₈ is Viterbi-decoded by the decoder 325 and <i>S</i>(8) is input to the shift register of the serial-input/parallel output type of the first forward direction converter 326.

0110As a result, the time delay occurs during the Viterbi decoding process. That is, the time is delayed until the state of the final decoded data of the next group is determined. For example, in case that the data is divided by 8-bit and processed in the reverse direction, S(8) is determined in the last of third periods, the first forward decoded data under the initial state S₁ or the second forward decoded data under initial state S₀ is selected at the same time. Thus, a delay of 24 (8 bit×3) bits.

0111However, if the clock frequency for the shift registers of reverse direction and forward direction converters, is increased, the time delay may be reduced.

0112On the other hand, the number of bits of each group is determined according to the digital modulation scheme. Particularly, the number of bits of each group should be determined considering a runlength limit (RLL) value to be set.

0113As described above, when the states are binary (S=1 or S=-1) and the decoding circuit is a partial response type of PR(1, -1), PR(1, 1) or PR(1, 0, 1), it is preferable to design a decoding circuit by adopting a shift register as a main circuit component without an A/D converter or microprocessor, wherein the shift register receives the positive and negative peak data. As a result, the size of the integrated circuit can be minimized and the manufacturing costs are reduced.