A synchronous semiconductor memory integrated circuit, a method for accessing said memory and a system comprising such a memory

The invention relates to a synchronous semiconductor memory integrated circuit which operates by use of edges of an external clock signal, said memory comprising a memory block; an input for an external clock signal; an address input means providing a first address as an output in response to a first edge of said external clock signal, and a second address as an output in response to a second edge of said external clock signal; access means for accessing a location in said memory block corresponding to said first address and said second address; and control means for receiving an external control input indicating a read/write mode defining a read mode and/or a write mode, and for changing said read/write mode based on a difference of level of said external control input at two successive edges of said external clock signal. Furthermore the invention relates to a method for accessing such a memory and a system comprising such a memory.