MPEG signals decoding device

p0001The present invention relates to a digital signal decoding device encoded MPEG type comprising various modules, including at least an audio module and a video module, designed to communicate with an external random access memory via a module said arbiter and interface for managing the different types of access - in a line of pixels in a line of macroblock MPEG, or to a macroblock in the fields of opposite parity - to decoded images.

p0002The field of application referred concerns the storage of images decoded by an MPEG2 decoder in a DRAM type of external memory (in English, <u>D</u>ynamic <u>R</u>Andom <u>AT</u>ccess <u>M</u>emory). As illustrated in Figure 1 very schematically showing an MPEG2 decoder, in such a decoder modules (M₁M₂M₃...) Access an external DRAM via a single interface module called "arbiter" (or arbiter). This memory allows particularly temporary storage of the stream of compressed data, and the storage of the decoded images. The arbiter, noted ARB manages all decoder modules access to this external memory (access requested by picture blocks that have to read or write information in memory). The different modules M1, M2, M3 etc ... perform different types of access to the decoded images, and in particular, as illustrated in Figure 2 which shows three of these types of access:<ul><li>(Has <u>b</u>by alayages <u>l</u>ine of <u>p</u>Image anointed (denoted BLP);</li><li>(B) <u>b</u>by alayages <u>l</u>ine of <u>m</u>acrobloc MPEG (denoted BLM);</li><li>(C) <u>at</u>ching a macroblock in a field <u>p</u>arity determined and the corresponding macroblock in the opposite parity field, denoted APO (CP even field and odd field CI, Figure 2).</li></ul>

p0003The addressing of FPM DRAM type ( "Fast Page Mode"), mentioned for example in patent application WO 95/31874, is performed as follows. Data is stored in 64 bit words by separating the information of chrominance and luminance. In a DRAM memory page (= 512 words of 64 bits) are stored, as shown respectively in Figures 3 and 4:<ul><li>the luminance macroblock 4 MB1i, MB2i, MB3i, MB4i the odd field (denoted i) and the luminance of the corresponding macroblock 4 MB1p, MB2p, MB3p, MB4p in the even field (p noted);</li><li>8 chrominance macroblocks of the odd field and chrominance 8 corresponding macroblock in the even field.</li></ul>

p0004This organization without page breaks the following access:<ul><li>access to lines of macroblocks: 4 consecutive luminance macroblocks (8 for chrominance);</li><li>access to lines of pixels: 4 * 16 = 64 consecutive luminance pixels (64 for chrominance);</li><li>access to peer macroblock / odd: such access is possible, as they are by building on the same page of memory DRAM.</li></ul>

p0005This addressing however concerned that current DRAM. But other types of memory, SDRAM memory, for example described in the document "Synchronous Dynamic RAM", Prince B. et al., IEEE Spectrum, 29 (1992), October, No. 10, pp 44-49 ( these synchronous DRAM memories use a synchronous interface inputs and data outputs are synchronized to the clock), seem destined to gradually replace them, especially because of their higher transfer speed.

p0006The object of the invention to provide a decoding device in which is defined a memory address to have an arbiter module capable of supporting types of DRAM or SDRAM-FPM, that is to say always use the same methods of communication with other modules.

p0007To this end, the invention concerns a device as defined in the preamble of the description and which is further characterized in that said device is compatible with an arbiter for memories known synchronous DRAM, or SDRAM, organized into two independent banks of 2048 physical pages of 256 words of 16 bits, accessing said SDRAM being effected in bursts of four words of 16 bits and with an alternate addressing of each of the two banks, to a storage luminance and chrominance performed under conditions such the luminance of 4 macroblocks of the odd field (respectively even) of a DRAM-FPM memory page is in an SDRAM, equally distributed in both benches and, for each of them, in two successive pages of these banks and even the chroma 8 macroblocks of the odd field (respectively even) of a DRAM-FPM memory page is in an equally distributed in both SDRAM and benches, each bench in two successive pages.

p0008In the decoding device and proposed implementation addressing method is suitable for SDRAM, while ensuring compatibility with the memory-based DRAM solution, and not changing the communications between the arbitrator and other modules (to switch from one type of DRAM to another, just change the arbiter in the decoding device, the modules that communicate with him remaining unchanged). Moreover, operations in this arbiter modified to handle the conversion of address suitable for addressing said synchronous DRAM memories are very simple, and therefore inexpensive.

p0009The features of the invention will now become apparent in greater detail in the following description and with reference to the figures, exemplary data and wherein:<ul><li>1 shows, in an MPEG2 decoder, the memory interface role played by the arbiter module;</li><li>2 illustrates different types of access to the decoded images in the image memory, and Figures 3 and 4 relate respectively addressing the luminance and chrominance in a DRAM-FPM memory type page;</li><li>Figures 5 and 6 show, in the case of the implementation of the invention, storing the luminance and chrominance (respectively) of a memory page in DRAM-FPM four SDRAM memory pages;</li><li>7 is a flow chart of instructions for illustrating an SDRAM control of the bank change the arbiter, and Figure 8 shows a similar diagram in the case of current DRAM.</li></ul>

p0010In the decoding device according to the invention, the arbiter is now able to manage not only an external DRAM memory, but also a SDRAM memory type. Storing the luminance in the case of FPM DRAM page, illustrated, seen on Figure 3. It shows on the same page four luminance macroblocks of the odd field (MB1i, MB2i, MB3i, MB4i) followed by four corresponding macroblocks of the even field (MB1p, MB2p, MB3p, MB4p), the memory subset represented with the following dimensions: 512 x 64 x 1 bits. Storing the chrominance in the same case of FPM DRAM page is illustrated similarly in Figure 4: it shows, on the same page, the chrominance eight macroblocks of the odd field (MB1i to MB8i ) followed by the eight corresponding macroblocks of the even field (MB1p to MB8p), thus represented the subset having the same dimensions 512 x 64 x 1 bits for luminance.

p0011Compared to a DRAM, SDRAM memory consists of two independent banks A and B of 2048 physical pages each, and each physical page has a size of 256 words of 16 bits and is divided into two logical-memory pages (even and odd) 128 16-bit words, a quarter of a logical page of DRAM-FPM. Storing the luminance and chrominance is then carried out in a modified way as illustrated in Figures 5 and 6 respectively. For the four luminance macroblocks of the odd field and the four corresponding macroblocks of the odd field (Figure 5), there is now equal distribution in the two banks A and B of the SDRAM and, for each, in two pages successive N and (N + 1) of these banks. The four corresponding subassemblies now each have dimensions of 216 x 16 x 1 bits, and are grouped by the following provision:<ul><li>A bench, page N: odd and even macroblocks 1;</li><li>bench B, page N: odd and even macroblocks 2;</li><li>A bench, page (N + 1): 3 odd and even macroblocks;</li><li>bench B, page (N + 1): 4 odd and even macroblocks;</li></ul> And so on. Similarly, storage of the chrominance, for a SDRAM memory, is now carried out as shown in Figure 6, that is to say with the same layout distributed benches (A and B) and, for each bank by page (N, N + 1). If the SDRAM is used in a mode "bursty 4", it is possible to switch from bank A to bank B and vice versa without loss of time if the access in each of the banks concerned at least 8 words of 16 bits (4 words for the first and last access).

p0012To achieve similar performance to that of a standard DRAM, the organization of access is now as follows:<ul><li>macroblock line: Possible access to an unlimited number of linearly macroblock because each two successive macroblock is in two opposite benches, two successive accesses therefore being made without loss of time to do a page break;</li><li>line of pixels: in this case, reads 16 pixels per macroblock, it is possible to make changes without bench cycle loss, and can be accessed in an unlimited manner the rows of pixels;</li><li>macroblock even / odd: Possible access as a macroblock and its corresponding opposite parity are still in the same SDRAM page.</li></ul>

p0013These different access with automatic bench based on address changes to read or write are illustrated in the diagram of FIG 7. and transactions begin with the preload of the two banks (PCH-AB), followed by the first access or next port considered, noted ACS. According to the authority for access relates to a memory area of bank A or bank B, the correspondent bank (to the relevant page, eg N) is activated (ACT-AN, or ACT-BN) then reading or writing requested in this bench is made ​​(AN-RW or RW-BN), while the other bed is preloaded. The output of this operation, if access was performed last (Y1 connection), the operations are completed, and the end of access is denoted E in Figure 7. If access was not the last (connection N1), a new read or write in the same bench is performed with simultaneous activation of another bank (ACT-ACT-B or a). A test is then performed (T-ACS) to determine if there is a next access request, or if it was the last. In the first situation (Y2 connection), the bench B is ready and there may be looping, as appropriate, on the read / write operation in bank A or B, page N, with activation of the other bench . In the second situation (N2 connection), operations are complete (end access E). For the principle works well, it takes two consecutive accesses to the same bank, except for the last access or a single access.

p0014This control by the arbiter of access with bench changes in the SDRAM is compared with similar control in the case of a DRAM-FPM memory, illustrated in Figure 8 and including single following: preload (PCH) , activation of N page (PTCA), read / write this page (RWP), test (Y / N) of last access, with relocation if the answer is negative or end access (E) if positive .

p0015To be used in a manner consistent with a DRAM-FPM memory or SDRAM, the invention thus described must concern, in the MPEG decoder, the arbiter. For the selection of the actually used memory does indeed regard this module, it limits the size of access to the size of those possible with DRAM-FPM solution, and we keep internally, between the arbiter and the other modules, a linear addressing of 18-bit, the arbiter using the 18-bit internal address, in the case of access control to the DRAM, to give the page numbers and column, and in the case control access to the SDRAM, to select the bank, the page number, the parity of the field, and the word of 64 or 16 bits. The address profit between the modules and the arbiter is unchanged. The arbitrator makes this bus a treatment that is the type of memory connected DRAM:<ul><li>if for example A [17: 0] is the size of the address bus sent by the modules to the arbiter, it interprets the bus for a DRAM-FPM memory, as follows: A [17: 9] = page number, and A [8: 8] = column number;</li><li>for SDRAM, we have for example: A [5] = selection of the bench, A [17: 8.6] = page number, A [7] = selection / odd (or 0 to 127 columns, or columns 128 to 255, top or bottom part of the page) and A [4: 0] = selection of 64-bit word.</li></ul>