EP0781052A2

Universal MPEG decoder with scalable picture size

Abstract

A decoder is disclosed for decoding MPEG video bitstreams encoded in any color space encoding format and outputting the decoded video bitstream to different sized windows. Both MPEG decompression and color space decoding and conversion are performed on the bitstreams within the same decoder. The disclosed decoder may be programmed to output the decoded video bitstream in any of three primary color space formats comprising YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4. The decoder may also output the decoded bitstream to different sized windows using Discrete Cosine Transform (DCT) based image resizing.

EP0781052A2, drawing sheet 1
Sheet 1 of 28

Term

Term ended

Projected expiry passed 12 December 2016, 9.8 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

27 claims: 4 independent, 23 dependent

  1. 1
    A decoder circuit in a display controller, said decoder circuit for decoding a video data signal, said decoder circuit comprising:first transform means for receiving the video data signal, applying an inverse transform upon the video data signal, and outputting an inverse transformed video data signal;wherein said fun transform means further comprises an Inverse Discrete Cosine Transform means further comprising: a sampling means for receiving inverse quantized Discrete Cosine Transform coefficients and a first at least one set of coefficients, applying a predetermined sampling process upon the inverse quantized Discrete Cosine Transform coefficients, and outputting a second at least one set of coefficients;a filter means coupled to said sampling means for receiving the inverse quantized Discrete Cosine Transform coefficients and the second at least one set of coefficients, and applying a predetermined filter process upon the inverse quantized Discrete Cosine Transform coefficients, and outputting a third at least one set of coefficients;a second transform means coupled to said sampling means, said filter means, and another means and for receiving said second and said third at least one set of coefficients and a fourth at least one set of coefficients;and a register means coupled to said second transform means and said computer system for storing said fourth at least one set of coefficients.
  2. 2
    The decoder circuit of Claim 1 further comprising a decoder means coupled to said first transform means for receiving a video data signal, decoding the video data signal, and outputting a first decoded video data signal.
  3. 3
    The decoder circuit of Claim 2, wherein said decoder means further receives an MPEG encoded video data signal.
  4. 4
    The decoder circuit of Claim 3 further comprising scan means coupled to said decoder means for receiving the first decoded video data signal, applying an inverse scan upon the decoded video data, and outputting an inverse scanned video data signal.
  5. 5
    The decoder of Claim 4 further comprising an inverse quantizer means coupled to said scan means for receiving the inverse scanned video data signal, applying an inverse quantization upon the inverse scanned video data, and outputting an inverse quantized video data signal to said first transform means.
  6. 6
    The decoder circuit of Claim 5 further comprising a motion compensation means coupled to said first transform means for receiving the inverse transformed video data signal, compensating the inverse transformed video data signal for motion and outputting a second decoded video data signal.
  7. 7
    The decoder circuit of Claim 6 further comprising frame storage means coupled to said motion compensation means for receiving the second decoded video data signal, storing at least one frame of the second decoded video data signal in at least one color space format, and outputting a third decoded video data signal.
  8. 8
    A method, in a computer system of decoding an MPEG video stream in a display controller, said method comprising the steps of:interpolating an MPEG video stream and outputting an interpolated video data stream, upsampling the interpolated video data stream and outputting an upsampled video data stream, filtering the upsampled video data stream and outputting a filtered video data stream, and performing an Inverse Discrete Cosine Transform on the filtered video data stream and outputting an Inverse Discrete Cosine Transform video data stream;wherein said step of interpolating the MPEG video data stream further comprises interpolating the MPEG video data stream encoded in one of a plurality of color space formats composing YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4.
  9. 9
    The method of Claim 8 wherein said step of filtering the upsampled video data stream further comprises using a Remez Exchange symmetrical FIR filter.
  10. 10
    The method of Claim 9 wherein said Remez Exchange symmetrical FIR filter comprises at least two taps.
  11. 11
    The method of Claim 10 wherein said Remez Exchange symmetrical FIR filter comprises 32 taps.
  12. 12
    The method of Claim 10 wherein said Remez Exchange symmetrical FIR filter comprises any even number of taps between 2 and 32 taps.
  13. 13
    The method of Claim 11 wherein said step of performing and Inverse Discrete Cosine Transform further comprises outputting the Inverse Cosine Transform video stream to a motion compensation circuit.
  14. 14
    A method, in a computer system of decoding an MPEG video stream in a display controller, said method comprising the steps of:decimating an MPEG video stream and outputting a decimated video data stream, filtering the decimated video data stream and outputting a filtered video data stream, downsampling the filtered video data stream and outputting an downsampled video data stream, and performing an Inverse Discrete Cosine Transform on the filtered video data stream and outputting an Inverse Discrete Cosine Transform video data stream;wherein said step of decimating the MPEG video data stream further comprises decimating the inverse quantized MPEG video data stream encoded in one of a plurality of color space formats comprising YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4.
  15. 15
    The method of Claim 13 wherein said step of filtering the upsampled video data stream further comprises using a Remez Exchange symmetrical FIR filter.
  16. 16
    The method of Claim 14 wherein said Remez Exchange symmetrical FIR filter comprises at least two taps.
  17. 17
    The method of Claim 15 wherein said Remez Exchange symmetrical FIR filter comprises 32 taps.
  18. 18
    The method of Claim 16 wherein said step of performing and Inverse Discrete Cosine Transform further comprises outputting the Inverse Cosine Transform video stream to a motion compensation circuit.
  19. 19
    A computer comprising:a central processing unit for controlling the operation of said computer, a system bus coupled to said central processing unit for transferring data between system components including said central processing unit, at least one memory area coupled to said central processing unit and said system bus for storing data, a display coupled to said central processing unit, said system bus, and at least one memory area, said display for displaying information in said computer, and a decoder coupled to said central processing unit, said system bus, said at least one memory area and said display for decoding an incoming MPEG video data stream in a first color space format and outputting a decoded video stream in a second color space format;wherein said first transform means further comprises: a sampling means for receiving inverse quantized Discrete Cosine Transform coefficients and a first at least one set of coefficients, applying a predetermined sampling process upon the inverse quantized Discrete Cosine Transform coefficients, and outputting a second at least one set of coefficients;a filter means coupled to said sampling means for receiving the inverse quantized Discrete Cosine Transform coefficients and the second at least one set of coefficients, and applying a predetermined filter process upon the inverse quantized Discrete Cosine Transform coefficients, and outputting a third at least one set of coefficients;a second transform means coupled to said sampling means, said filter means, and another means and for receiving said second and said third at least one set of coefficients and a fourth at least one set of coefficients;and a register means coupled to said second transform means and said computer system for storing said fourth at least one set of coefficients.
  20. 20
    The computer of Claim 19, wherein said decoder further comprises:first transform means for receiving the video data signal, applying an inverse transform upon the video data signal, and outputting an inverse transformed video data signal.
  21. 21
    The computer of Claim 19, wherein said first transform means further comprises an Inverse Discrete Cosine Transform means.
  22. 22
    The computer of Claim 20, further comprising a decoder means coupled to said first transform means for receiving a video data signal, decoding the video data signal, and outputting a first decoded video data signal.
  23. 23
    The computer of Claim 21, wherein said decoder means further receives an MPEG encoded video data signal.
  24. 24
    The computer of Claim 22, further comprising scan means coupled to said decoder means for receiving the first decoded video data signal, applying an inverse scan upon the decoded video data, and outputting an inverse scanned video data signal.
  25. 25
    The computer of Claim 23, further comprising an inverse quantizer means coupled to said scan means for receiving the inverse scanned video data signal, applying an inverse quantization upon the inverse scanned video data, and outputting an inverse quantized video data signal to said first transform means.
  26. 26
    The computer of Claim 24, further comprising a motion compensation means coupled to said first transform means for receiving the inverse transformed video data signal, compensating the inverse transformed video data signal for motion and outputting a second decoded video data signal.
  27. 27
    The computer of Claim 25, further comprising frame storage means coupled to said motion compensation means for receiving the second decoded video data signal, storing at least one frame of the second decoded video data signal in at least one color space format, and outputting a third decoded video data signal.
Independent claims27