A magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data

FIELD OF INVENTION

0001The present invention relates to the control of magnetic disk storage systems for digital computers, particularly to a sampled amplitude read channel that employs interpolated timing recovery for synchronous detection of embedded servo data.

CROSS REFERENCE TO RELATED APPLICATIONS AND PATENTS

0002This application is related to other co-pending U.S. patent applications, namely application serial numbers 08/440,515 entitled "Sampled Amplitude Read Channel For Reading User Data and Embedded Servo Data From a Magnetic Medium," 08/341,251 entitled "Sampled Amplitude Read Channel Comprising Sample Estimation Equalization, Defect Scanning, Channel Quality, Digital Servo Demodulation, PID Filter for Timing Recovery, and DC Offset Control," 08/313,491 entitled "Improved Timing Recovery For Synchronous Partial Response Recording." This application is also related to several U.S. patents, namely U.S. Pat. No. 5,359,631 entitled "Timing Recovery Circuit for Synchronous Waveform Sampling," 5,291,499 entitled "Method and Apparatus for Reduced-Complexity Viterbi-Type Sequence Detectors," 5,297,184 entitled "Gain Control Circuit for Synchronous Waveform Sampling," 5,329,554 entitled "Digital Pulse Detector," and 5,424,881 entitled "Synchronous Read Channel." All of the above-named patent applications and patents are assigned to the same entity, and all are incorporated herein by reference.

BACKGROUND OF THE INVENTION

0003In magnetic storage systems for computers, digital data serves to modulate the current in a read/write head coil in order to write a sequence of corresponding magnetic flux transitions onto the surface of a magnetic medium in concentric, radially spaced tracks at a predetermined baud rate. When reading this recorded data, the read/write head again passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog signal that alternate in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.

0004Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.

0005There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).

0006In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is "segmented" into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a "1" bit, whereas the absence of a peak is detected as a "0" bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive "0" bits.

0007As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme that ensures a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of "0" bits between "1" bits, and to k the maximum number of consecutive "0" bits. A typical (1,7) RLL 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.

0008Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a low pass analog filter processes the read signal to attenuate aliasing noise. After sampling, a digital equalizing filter equalizes the sample values according to a desired partial response, and a discrete time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection MLSD). In this manner, a sampled amplitude read channel can take into account the effect of ISI and channel noise during the detection process, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.

0009The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", <i>IEEE Trans. Commun. Tech.</i>, Vol. COM-23, pp.921-934, Sept. 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G.D. Forney, Jr., "The Viterbi Algorithm", <i>Proc. IEEE</i>, Vol. 61, pp. 268-278, March 1973.

0010Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", <i>IEEE Journal on Selected Areas in Communications</i>, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", <i>IEEE Trans. Commun.</i>, Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", <i>IEEE Trans. on Magnetics</i>, Vol. 27, No. 6, Nov. 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", <i>Digest of The Magnetic Recording Conference</i>, August 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", <i>IEEE Trans. on Magnetics</i>, Vol. 30, No. 5, Sept. 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", <i>Globecom'90 IEEE Global Telecommunications Conference 1990</i>, San Diego, CA, Nov. 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", <i>IEEE Transactions on Magnetics</i>, Vol. 27, No. 1, Jan. 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-Disk Storage Channels", <i>IEEE Communication Magazine</i>, Feb. 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", <i>Intermag'90</i>.

0011Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In prior art sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.

0012A phase-locked-loop (PLL) normally implements the decision-directed feedback system to control timing recovery in sampled amplitude read channels. The PLL comprises a phase detector which generates a phase error based on the difference between the estimated samples and the read signal samples. A loop filter in the PLL filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate.

0013In prior art timing recovery methods, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the pulse samples to the baud rate.

0014Also in prior art timing recovery methods, it is helpful to first lock the PLL to a reference or nominal sampling frequency so that the desired sampling frequency, with respect to the analog pulses representing the digital data, can be acquired and tracked more efficiently. The nominal sampling frequency is the baud rate, the rate that data was written onto the medium. Therefore, one method to lock-to-reference is to generate a sinusoidal signal relative to the output of a write VFO (write clock) and inject this signal into the PLL. Once locked to the reference frequency, the PLL input switches from the write clock to the signal from the read head in order to synchronize the sampling of the waveform in response to a sinusoidal acquisition preamble recorded on the medium.

0015The acquisition and tracking modes for timing recovery are related to the data format of the magnetic disk. Figure 2A shows a magnetic disk comprising a plurality of concentric data tracks <b>13</b> wherein each data track <b>13</b> comprises a plurality of sectors <b>15</b>. Servo data in the form of wedges <b>17</b> are embedded into the sectors <b>15</b> and used to control and verify the track and sector position of the read/write head. Figure 2B shows the format of a sector <b>15</b> comprising an acquisition preamble <b>68</b>, a sync mark <b>70</b>, and user data <b>72</b>. The acquisition preamble is a predetermined sequence that allows timing recovery to acquire the desired sampling phase and frequency before reading the user data. After acquisition, the PLL switches to a tracking mode in order to track the desired sampling phase and frequency with respect to the analog pulses representing the user data. The sync mark signals the beginning of the user data. As illustrated in Figure 2B, a short acquisition preamble is desirable to allow more storage area for user data.

0016Zoned recording is a technique known in the art for increasing the storage density by recording the user data at different rates in predefined zones between the inner diameter and outer diameter tracks. The data rate can be increased at the outer diameter tracks due to the increase in circumferential recording area and the decrease in intersymbol interference. This allows more data to be stored in the outer diameter tracks as is illustrated in Figure 2A where the disk is partitioned into an outer zone <b>11</b> comprising fourteen data sectors per track, and an inner zone <b>27</b> comprising seven data sectors per track. In practice, the disk may actually be partitioned into several zones at varying data rates.

0017Prior techniques are known for acquiring and tracking the sampling frequency/phase based on the phase error computed from the actual signal samples and estimated signal samples obtained from symbol-by-symbol decisions. See "Timing Recovery in Digital Synchronous Receivers" by K. H. Mueller and M. Muller, IEEE Transactions on Communications, Vol. Com-24 (1976), pp. 516-531. Co-pending United States patent application serial number 08/313,491 entitled "Improved Timing Recovery for Synchronous Partial Response Recording" discloses an improvement to the Mueller and Muller stochastic gradient method. In this method of timing recovery a slicer, commonly employed in a d=0 PR4 partial response recording channel, estimates the sample values by comparing the signal sample values to predetermined thresholds. A stochastic gradient circuit, which minimizes the mean squared error between the signal sample values and the estimated sample values, generates the phase error to control the frequency of the sampling VFO.

0018U.S. Pat. No. 5,359,631 entitled "Timing Recovery Circuit for Synchronous Waveform Sampling" discloses yet another method for timing recovery in a sampled amplitude read channel. In this method a pulse detector, commonly employed in a d=1 EPR4 or EEPR4 partial response recording channel, operates to determine the estimated sample values. Again, a stochastic gradient circuit uses the estimated sample values, together with the signal sample values, to generate the phase error for adjusting the sampling clock in the decision-directed feedback system.

0019The timing recovery loop filter controls the dynamics of the decision-directed feedback system. Accordingly, the loop filter coefficients are adjusted to achieve a desired transient response and tracking quality. For good tracking quality, the loop bandwidth should be narrow in order to attenuat phase noise and gain variance. During acquisition, the loop bandwidth should be as wide as possible without being unstable to achieve a fast transient response. A fast transient response results in a shorter acquisition time which minimizes the necessary length of the acquisition preamble.

0020In the above mentioned prior art methods for timing recovery, the phase error operates to adjust the sampling rate of the sampling VFO relative to the data rate of a particular zone on the disk. That is, when the read head passes into a new zone (e.g., outer zone <b>11</b> to inner zone <b>27</b> of Figure 2A), the frequency of the sampling VFO is adjusted and eventually synchronized to the data rate of the new zone. This is normally accomplished by programming a center frequency setting of the sampling VFO to a value corresponding to the new zone, and then adjusting a fine frequency setting until the sampling VFO is synchronized to the data rate.

0021Several problems have been identified with the above prior art timing recovery methods that synchronize sampling of the pulses using a sampling VFO in a PLL.

0022For instance, the slight difference in operating frequencies between the write VFO and the sampling VFO can result in cross-talk that degrades the performance of timing recovery.

0023Further, synchronous detection of embedded servo data requires an additional servo VFO to generate the center operating frequency of the sampling VFO when reading the servo data (see the above referenced co-pending U.S. patent application Ser. No. 08/440,515, entitled "Sampled Amplitude Read Channel For Reading User Data and Embedded Servo Data From a Magnetic Medium").

0024Still further, adjusting the sampling rate relative to a particular zone requires a programmable analog filter to compensate for aliasing at the various data rates, a complex and expensive implementation that requires calibrating the analog filter to operate in each zone.

0025Yet another problem associated with conventional PLL timing recovery are the delays inherent in the sampling device and discrete time equalizing filter which cause the timing loop to be less stable. Thus, latency considerations can increase the cost and complexity of the sampling device and reduce the effectiveness of the equalizing filter. A more complex discrete time equalizing filter could equalize the samples before the timing loop, but this would require reconstruction at the filter's output from discrete-time back to continuous-time for processing by the sampling PLL.

0026There is, therefore, a need for a new timing recovery technique for sampled amplitude recording that does not exhibit the cross talk phenomena associated with a write VFO frequency being very near a sampling VFO frequency.

0027A further object is to avoid using a separate servo VFO for synchronous detection of embedded servo data.

0028Still another object is to obviate the expensive, programmable analog filter used for anti-aliasing in prior art zoned recording read channels.

0029Yet another object is to remove the sampling device and discrete time equalizing filter, and their associated latencies, from the timing recovery loop.

SUMMARY OF THE INVENTION

0030In a sampled amplitude read channel for magnetic disk recording, ansynchronously sampling the analog read signal at a fixed sample rate across the entire disk (i.e., a fixed sample rate over the various user data zones and the embedded servo wedges), extracting synchronous samples from the asynchronous samples using interpolated timing recovery rather than sampled timing recovery, and detecting the recorded digital data from the interpolated sample values. A write synthesizer generates a write clock for writing digital data to the magnetic disk at a predetermined baud rate for a selected zone, and upon read back, a read synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer diameter zone (i.e, slightly higher than the highest baud rate). A sampling device samples the analog read signal at this fixed sample rate across the various data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter having a fixed frequency response attenuates aliasing noise. After sampling, an equalizing filter equalizes the asynchronous channel samples according to a predetermined partial response (e.g., PR4, EPR4, EEPR4, DFE, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval τ and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The interpolated timing recovery circuit also generates a data clock for clocking a discrete time sequence detector and a discrete time peak detector for detecting the user and servo data from the interpolated sample values.

0031Since the interpolating timing recovery does not use a separate sampling VFO, cross talk between the write VFO is avoided. Further, a separate servo VFO is not needed for synchronous detection of embedded servo data because the interpolating timing recovery can be adjusted on-the-fly to the servo data rate. In addition, the analog anti-aliasing filter can be fixed, rather than programmable, since the sampling rate is fixed over the entire disk. Still further, the sampling device and discrete time equalizing filter have been removed from the timing recovery loop, thereby avoiding the associated latencies.

BRIEF DESCRIPTION OF THE DRAWINGS

0032The above and other aspects and advantages of the present invention will be better understood by reading the following detailed description of the invention in conjunction with the drawings, wherein: <ul id="ul0001" list-style="none" compact="compact"><li>Figure 1A is a block diagram of a conventional sampled amplitude recording channel.</li><li>Figure 1B shows a frequency spectrum of the sampled channel data according to the prior art method of adjusting the sampling rate relative to the data rate of the zone where the read head is positioned.</li><li>Figure 1C shows, according to the present invention, a frequency spectrum of the sampled channel data when the sampling rate is fixed at a frequency slightly higher than the data rate at the outer diameter zone and not adjusted when reading data from the inner diameter zones, or when reading the servo data.</li><li>Figure 2A shows an exemplary data format of a magnetic disk having a plurality of concentric tracks comprised of a plurality of user data sectors and embedded servo data sectors.</li><li>Figure 2B shows an exemplary format of a user data sector.</li><li>Figure B3 is a block diagram of the improved sampled amplitude read channel of the present invention comprising interpolated timing recovery for generating interpolated sample values and a synchronous data clock for clocking operation of a discrete time sequence detector and peak detector.</li><li>Figure B4A is a detailed block diagram of the prior art sampling timing recovery comprising a sampling VFO.</li><li>Figure B4B is a detailed block diagram of the interpolating timing recovery of the present invention comprising an interpolator.</li><li>Figure B5 illustrates the channels samples in relation to the interpolated baud rate samples for the acquisition preamble.</li><li>Figure B6 shows an FIR filter implementation for the timing recovery interpolator.</li><li>Figure B7 depicts a cost reduced implementation for the timing recovery interpolator.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Conventional Sampled Amplitude Read Channel

0033Referring now to Figure 1, shown is a detailed block diagram of a conventional sampled amplitude read channel. During a write operation, either user data <b>2</b> or preamble data from a data generator <b>4</b> (for example 2T preamble data) is written onto the media. An RLL encoder <b>6</b> encodes the user data <b>2</b> into a binary sequence b(n) <b>8</b> according to an RLL constraint. A precoder <b>10</b> precodes the binary sequence b(n) <b>8</b> in order to compensate for the transfer function of the recording channel <b>18</b> and equalizing filters to form a precoded sequence ∼b(n) <b>12</b>. The precoded sequence ∼b(n) <b>12</b> is converted into symbols a(n) <b>16</b> by translating <b>14</b> ∼b(N) = 0 into a(N) = -1, and ∼b(N) = 1 into a(N) = +1. Write circuitry <b>9</b>, responsive to the symbols a(n) <b>16</b>, modulates the current in the recording head coil at the baud rate 1/T to record the binary sequence onto the media. A frequency synthesizer <b>52</b> provides a baud rate write clock <b>54</b> to the write circuitry <b>9</b> and is adjusted by a channel data rate signal (CDR) <b>30</b> according to the zone the write head is over.

0034When reading the recorded binary sequence from the media, timing recovery <b>28</b> first locks to the write frequency by selecting, as the input to the read channel, the write clock <b>54</b> through a multiplexor <b>60</b>. Once locked to the write frequency, the multiplexor <b>60</b> selects the signal <b>19</b> from the read head as the input to the read channel in order to acquire an acquisition preamble. A variable gain amplifier <b>22</b> adjusts the amplitude of the analog read signal <b>58</b>, and an analog filter <b>20</b> provides initial equalization toward the desired response as well as attenuating aliasing noise. A sampling device <b>24</b> samples the analog read signal <b>62</b> from the analog filter <b>20</b>, and a discrete time filter <b>26</b> provides further equalization of the sample values <b>25</b> toward the desired response. In partial response recording, for example, the desired response is often selected from Table 1.

0035The equalized sample values <b>32</b> are applied to decision directed gain control <b>50</b> and timing recovery <b>28</b> for adjusting the amplitude of the read signal <b>58</b> and the frequency and phase of the sampling device <b>24</b>, respectively. Timing recovery adjusts the frequency of sampling device <b>24</b> over line <b>23</b> in order to synchronize the equalized samples <b>32</b> to the baud rate. Frequency synthesizer <b>52</b> provides a course center frequency setting to the timing recovery circuit <b>28</b> over line <b>64</b> in order to center the timing recovery frequency over temperature, voltage, and process variations. The channel data rate (CDR) <b>30</b> signal adjusts a frequency range of the synthesizer <b>52</b> according to the data rate for the current zone. Gain control <b>50</b> adjusts the gain of variable gain amplifier <b>22</b> over line <b>21</b>. The equalized samples Y(n) <b>32</b> are sent to a discrete time sequence detector <b>34</b>, such as a maximum likelihood (ML) Viterbi sequence detector, and to a discrete time peak detector <b>70</b> which detect an estimated binary sequence of user/servo data. An RLL decoder <b>36</b> decodes the estimated binary sequence ^{^}b(n) <b>33</b> from the sequence detector <b>34</b> into estimated user/servo data <b>37</b>. A data sync detector <b>66</b> detects the sync mark <b>70</b> (shown in Figure 2B) in the data sector <b>15</b> in order to frame the operation of the RLL decoder <b>36</b>. A multiplexor <b>72</b> selects the output <b>37</b> of the RLL decoder <b>36</b> or peak detector <b>70</b> as the estimated decoded servo data <b>74</b> output to a servo controller (not shown) for positioning the read/write head. In the absence of errors, the estimated binary sequence ^{^}b(n) <b>33</b> equals the recorded binary sequence b(n) <b>8</b>, and the decoded user data <b>37</b> equals the recorded user data <b>2</b>.

Data Format

0036Figure 2A shows an exemplary data format of a magnetic media comprising a series of concentric data tracks <b>13</b> wherein each data track <b>13</b> comprises a plurality of sectors <b>15</b> with embedded servo wedges <b>17</b>. A servo controller (not shown) processes the servo data in the servo wedges <b>17</b> and, in response thereto, positions the read/write head over a desired track. Additionally, the servo controller processes servo bursts within the servo wedges <b>17</b> to keep the head aligned over a centerline of the desired track while writing and reading data. The servo wedges <b>17</b> may be detected by a simple discrete time pulse detector <b>70</b> or by the discrete time sequence detector <b>34</b>. If the sequence detector <b>34</b> detects the servo data, then the format of the servo wedges <b>17</b> includes a preamble and a sync mark, similar to the user data sectors <b>15</b>.

0037Figure 2B shows the format of a user data sector <b>15</b> comprising an acquisition preamble <b>68</b>, a sync mark <b>70</b>, and user data <b>72</b>. Timing recovery uses the acquisition preamble <b>68</b> to acquire the correct sampling frequency and phase before reading the user data <b>72</b>, and the sync mark <b>70</b> demarks the beginning of the user data <b>72</b> (see co-pending U.S. patent application 08/313,491 entitled "Improved Timing Recovery For Synchronous Partial Response Recording").

0038To increase the overall storage density, the disk is partitioned into an outer zone <b>11</b> comprising fourteen data sectors per track, and an inner zone <b>27</b> comprising seven data sectors per track. In practice, the disk is actually partitioned into several zones and the data recorded and detected at varying data rates.

Channel Frequency Spectrum

0039Figure 1B shows a frequency spectrum of the sampled channel data according to the prior art method of adjusting the sampling rate relative to the data rate of the zone where the read head is positioned. With timing recovery <b>28</b> synchronizing the sampling <b>24</b> of the read signal <b>62</b> to the channel data rate using the prior art method, then according to the Nyquist sampling theorem, the bandwidth of the analog read signal <b>19</b> must be constrained to half the sampling rate in order to attenuate aliasing noise. This means that the analog receive filter <b>20</b> must cutoff the frequency components of the analog read signal <b>19</b> above 1/2 the sampling frequency (i.e., the data rate). Since the sampling frequency is adjusted to the data rate corresponding to the various zones, the analog receive filter must also be programmed to adjust its cutoff frequency accordingly. This is illustrated in Figure 1B which shows the frequency spectrum of the channel when sampling at an outer diameter (OD) zone f_s(OD) and at an inner diameter (ID) zone f_s(ID). When sampling at f_s(OD), the analog receive filter <b>20</b> must be programmed to pass frequencies <b>80A</b> below 1/2·f_s(OD), and cutoff frequencies <b>80B</b> higher than 1/2·f_s(OD). Similarly, when sampling at f_s(ID), the analog receive filter <b>20</b> must be programmed to pass frequencies <b>82A</b> below 1/2·f_s(ID), and cutoff frequencies <b>82B</b> higher than 1/2·f_s(ID). Programmable analog filters are expensive, complex in implementation, and must be calibrated to operate in each zone. In addition, as can be seen in Figure 1B, the analog filter must have a relatively sharp rolloff so that it does not attenuate the signal spectrum below 1/2·f_s, which further increases its cost and complexity.

0040The present invention reduces the complexity and cost of the analog filter by sampling <b>24</b> the analog read signal <b>19</b> at a fixed frequency across the entire disk. In this manner, the analog receive filter's cutoff frequency can remain fixed, and it does not require as sharp a rolloff. This is illustrated in Figure 1C where the analog read signal <b>19</b> is sampled <b>24</b> at a frequency slightly higher than the data rate of the outer diameter track (i.e., sampled at f_s(OD)+ε). When reading data from any zone on the disk, the analog receive filter <b>20</b> must pass frequencies below 1/2·f_s(OD) and cutoff frequencies above <maths id="math0001" num=""><math display="inline"><mrow><msub><mrow><mtext>(1/2·f</mtext></mrow><mrow><mtext>s</mtext></mrow></msub><mtext>(OD))+2ε</mtext></mrow></math><img file="EP0777211A2_D0001.tif" /></maths>. In other words, the analog receive filter's cutoff frequency can remain fixed because the desired signal spectrum changes shape from the outer diameter (i.e., spectrum <b>84A</b>) to the inner diameter (i.e., spectrum <b>86A</b>), but the position of the aliased spectrums (i.e., spectrums <b>84B</b> and <b>86B</b>, respectively) remain fixed. Furthermore, the analog receive filter's rolloff can be flatter due to oversampling rather than synchronous sampling the read signal; that is, the analog filter's rolloff constraint lessens the more the read signal is oversampled (by increasing ε).

0041Sampling the analog read signal at a fixed, oversampled rate requires two enabling modifications to the prior art sampled amplitude read channels: first, it requires interpolated (rather than synchronous sampling) timing recovery to extract synchronous data from the asynchronous samples; and second, it requires a more complex discrete time equalizing filter.

0042The spectrum of the discrete time equalizing filter in prior art synchronous sampling read channels scales with the changing sampling rates across the zones. Only minor adjustments are necessary to compensate for any deviations in the disk's frequency response from zone to zone. In the present invention, however, the sampling rate is fixed across the zones; the spectrum of the discrete filter does not scale to the data rate―it must be adjusted accordingly. Accurate adjustment of the discrete filter's spectrum to generate the desired partial response across the various zones when using a fixed sampling rate requires a higher number of taps and coefficients. The discrete filter is normally implemented as a transversal FIR filter, and those skilled in the art can readily construct this filter with a sufficient number of taps and coefficients necessary to implement the fixed sampling technique of the present invention. The details of the discrete filter are, therefore, not included in this disclosure.

0043While the discrete time equalizing filter of the present invention requires more taps and coefficients in order to accurately shape the read signal's frequency response across the zones, the cost of discrete time circuitry, such as digital circuitry implemented in CMOS, is rapidly decreasing as the size and cost per gate decrease. In addition, digital circuitry is more robust and provides higher yields (i.e., less defective parts). The present invention provides yet another advantage in fixing the analog receive filter across the zones and loosening the rolloff constraint: it significantly reduces the cost and complexity of the analog filter. In fact, a simple, passive RC network will suffice.

0044The other design modification necessary to implement the present invention, interpolated timing recovery, will now be discussed in greater detail.

Improved Sampled Amplitude Read Channel

0045Figure B3 shows the improved sampled amplitude read channel of the present invention wherein the conventional sampled timing recovery <b>28</b> of Figure 1 has been replaced by interpolated timing recovery <b>B100</b>. In addition to a write frequency synthesizer <b>52</b> for generating a baud rate write clock <b>54</b> applied to the write circuitry <b>9</b> at a frequency relative to the current zone (CDR <b>30</b>), a read frequency synthesizer <b>53</b> generates a fixed sampling clock <b>55</b> applied to the sampling device <b>24</b>, the discrete time equalizer filter <b>26</b>, and the interpolated timing recovery <b>B100</b>.

0046When reading data from any particular zone, the read frequency synthesizer <b>53</b> outputs a fixed sampling clock <b>55</b> at a frequency slightly higher than the highest data rate (which normally occurs at the outer diameter zone). The analog receive filter <b>20</b> used for anti-aliasing has a fixed spectrum since the sampling frequency does not change across the zones. This reduces the complexity and cost of the analog filter <b>20</b> and simplifies the operation of the read channel by not having to calibrate the analog filter <b>20</b> to operate optimumly in each zone. The interpolated timing recovery <b>B100</b> interpolates the equalized sample values <b>32</b> to generate interpolated sample values <b>B102</b> substantially synchronized to the data rate of the current zone or to the data rate of the servo wedge <b>17</b>.

0047A discrete time sequence detector <b>34</b> detects an estimated binary sequence <b>33</b> representing the user/servo data from the interpolated sample values <b>B102</b>. Alternatively, a discrete time pulse detector <b>70</b> detects the servo data from the interpolated sample values <b>B102</b>. Interpolated timing recovery <b>B100</b> generates a synchronous data clock <b>B104</b> for clocking operation of the discrete time sequence detector <b>34</b>, discrete time pulse detector <b>70</b>, sync mark detector <b>66</b> and RLL decoder <b>36</b>.

Conventional Timing Recovery

0048An overview of the conventional sampling timing recovery <b>28</b> of Figure 1 is shown in Figure B4A. The output <b>23</b> of a variable frequency oscillator (VFO) <b>B164</b> controls the sampling clock of a sampling device <b>24</b> which is typically an analog-to-digital converter (A/D) in digital read channels. A multiplexor <b>B159</b> selects the unequalized sample values <b>25</b> during acquisition and the equalized sample values <b>32</b> during tracking, thereby removing the discrete equalizer filter <b>26</b> from the timing loop during acquisition in order to avoid its associated latency. A phase error detector <b>B155</b> generates a phase error in response to the sample values received over line <b>B149</b> and estimated sample values ∼X(n) from a sample value estimator <b>B141</b>, such as a slicer in a d=0 PR4 read channel, over line <b>B143</b>. A loop filter <b>B160</b> filters the phase error to generate a frequency offset Δƒ <b>B167</b> that settles to a value proportional to a frequency difference between the sampling clock <b>23</b> and the baud rate. The frequency offset Δƒ <b>B167</b>, together with the center frequency control signal <b>64</b> from the frequency synthesizer <b>52</b>, adjust the sampling clock <b>23</b> at the output of the VFO <b>B164</b> in order to synchronize the sampling to the baud rate. A zero phase start <b>B162</b> circuit suspends operation of the VFO <b>164</b> at the beginning of acquisition in order to minimize the initial phase error between the sampling clock <b>23</b> and the read signal <b>62</b>. This is achieved by disabling the VFO <b>B164</b>, detecting a zero crossing in the analog read signal <b>62</b>, and re-enabling the VFO <b>164</b> after a predetermined delay between the detected zero crossing and the first baud rate sample.

Interpolated Timing Recovery

0049The interpolated timing recovery <b>B100</b> of the present invention is shown in Figure B4B. The VFO <b>B164</b> of Figure B4A is replaced with a modulo-Ts accumulator <b>B120</b> and an interpolator <b>B122</b>. In addition, an expected sample value generator <b>B151</b>, responsive to interpolated sample values <b>B102</b>, generates expected samples X(n) used by the phase error detector <b>155</b> to compute the phase error during acquisition. A multiplexor <b>B153</b> selects the estimated sample values ∼X(n) from the slicer for use by the phase error detector <b>155</b> during tracking. The data clock <b>B104</b> is generated at the output of an AND gate <b>B126</b> in response to the sampling clock <b>54</b> and a mask signal <b>B124</b> from the modulo-Ts accumulator <b>B120</b> as discussed in further detail below. The phase error detector <b>B155</b> and the slicer <b>B141</b> process interpolated sample values <b>B102</b> at the output of the interpolator <b>B122</b> rather than the channel sample values <b>32</b> at the output of the discrete equalizer filter <b>26</b> as in Figure B4A. A PID loop filter <b>B161</b> controls the closed loop frequency response similar to the loop filter <b>B160</b> of Figure B4A.

0050In the interpolated timing recovery of the present invention, locking a VFO to a reference frequency before acquiring the preamble is no longer necessary; multiplexing <b>60</b> the write clock <b>54</b> into the analog receive filter <b>20</b> is not necessary. Further, the sampling device <b>24</b> and the discrete equalizer filter <b>26</b> together with their associated delays have been removed from the timing loop; it is not necessary to multiplex <b>B159</b> around the equalizer filter <b>26</b> between acquisition and tracking. However, it is still necessary to acquire a preamble <b>68</b> before tracking the user data <b>72</b>. A zero phase start circuit <b>B163</b> minimizes the initial phase error between the interpolated sample values and the baud rate at the beginning of acquisition similar to the zero phase start circuit <b>B162</b> of Figure B4A. However, rather than suspend operation of a sampling VFO <b>B164</b>, the zero phase start circuit <b>B163</b> for interpolated timing recovery computes an initial phase error τ from the equalized sample values <b>32</b> and loads the initial phase error into the modulo-Ts accumulator <b>B120</b>.

0051For a more detailed description of the PID loop filter <b>B160</b>, phase error detector <b>155</b>, frequency error detector <b>157</b>, expected sample generator <b>B151</b>, and slicer <b>B141</b>, refer to the above referenced co-pending U.S. patent applications "Sampled Amplitude Read Channel Comprising Sample Estimation Equalization, Defect Scanning, Channel Quality, Digital Servo Demodulation, PID Filter for Timing Recovery, and DC Offset Control" and "Improved Timing Recovery For Synchronous Partial Response Recording." A detailed description of the modulo-Ts accumulator <b>B102</b>, data clock <b>B126</b>, and interpolator <b>B122</b> is provided in the following discussion.

Interpolator

0052The interpolator <b>B122</b> of Figure B4B is understood with reference to Figure B5 which shows a sampled 2T acquisition preamble signal <b>B200</b>. The target synchronous sample values are shown as black circles and the asynchronous channel sample values as arrows. Bellow the sampled preamble signal is a timing diagram depicting the corresponding timing signals for the sampling clock <b>54</b>, the data clock <b>B104</b> and the mask signal <b>B124</b>. As can be seen in Figure B5, the preamble signal <b>B200</b> is sampled slightly faster than the baud rate (the rate of the target values).

0053The function of the interpolator is to estimate the target sample value by interpolating the channel sample values. For illustrative purposes, consider a simple estimation algorithm, linear interpolation:<maths id="math0002" num="(1)"><math display="block"><mrow><mtext>Y(N) = x(N) + τ·(x(N-1) - x(N)); where:</mtext></mrow></math><img file="EP0777211A2_D0002.tif" /></maths> x(N) and x(N-1) are the channel samples surrounding the target sample; and τ is an interpolation interval proportional to a time difference between the channel sample value x(N-1) and the target sample value. The interpolation interval τ is generated at the output of modulo-Ts accumulator <b>B120</b> which accumulates the frequency offset signal Δƒ <b>B167</b> at the output of the PID loop filter <b>B160</b>:<maths id="math0003" num="(2)"><math display="block"><mrow><mtext>τ = (Σ Δƒ) MOD TS; where:</mtext></mrow></math><img file="EP0777211A2_D0003.tif" /></maths> Ts is the sampling period of the sampling clock <b>54</b>. Since the sampling clock <b>54</b> samples the analog read signal <b>62</b> slightly faster than the baud rate, it is necessary to mask the data clock every time the accumulated frequency offset Δƒ, integer divided by Ts, increments by 1. Operation of the data clock <b>B104</b> and the mask signal <b>B124</b> generated by the modulo-Ts accumulator <b>B120</b> is understood with reference to the timing diagram of Figure B5.

0054Assuming the interpolator implements the simple linear equation (1) above, then channel sample values <b>B202</b> and <b>B204</b> are used to generate the interpolated sample value corresponding to target sample value <b>B206</b>. The interpolation interval τ <b>B208</b> is generated according to equation (2) above. The next interpolated sample value corresponding to the next target value <b>B210</b> is computed from channel sample values <b>B204</b> and <b>B212</b>. This process continues until the interpolation interval τ <b>B214</b> would be greater than Ts except that it "wraps" around and is actually τ <b>B216</b> (i.e., the accumulated frequency offset Δƒ, integer divided by Ts, increments by 1 causing the mask signal <b>B124</b> to activate). At this point, the data clock <b>B104</b> is masked by mask signal <b>B124</b> so that the interpolated sample value corresponding to the target sample value <b>B220</b> is computed from channel sample values <b>B222</b> and <b>B224</b> rather than channel sample values <b>B218</b> and <b>B222</b>.

0055The simple linear interpolation of equation (1) will only work if the analog read signal is sampled at a much higher frequency than the baud rate. This is not desirable since operating the channel at higher frequencies increases its complexity and cost. Therefore, in the preferred embodiment the interpolator <b>B122</b> is implemented as a filter responsive to more than two channel samples to compute the interpolated sample value.

0056The ideal discrete time phase interpolation filter has a flat magnitude response and a constant group delay of τ:<maths id="math0004" num="(3)"><math display="block"><mrow><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>) = </mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jωτ</mtext></mrow></msup></mrow></math><img file="EP0777211A2_D0004.tif" /></maths> which has an ideal impulse response:<maths id="math0005" num="(4)"><math display="block"><mrow><msub><mrow><mtext>sinc(π·(n-τ/T</mtext></mrow><mrow><mtext>s</mtext></mrow></msub><mtext>)).</mtext></mrow></math><img file="EP0777211A2_D0005.tif" /></maths> Unfortunately, the above non-causal infinite impulse response (4) cannot be realized. Therefore, the impulse response of the interpolation filter is designed to be a best fit approximation of the ideal impulse response (4). This can be accomplished by minimizing a mean squared error between the frequency response of the actual interpolation filter and the frequency response of the ideal interpolation filter (3). This approximation can be improved by taking into account the spectrum of the input signal, that is, by minimizing the mean squared error between the input spectrum multiplied by the actual interpolation spectrum and the input spectrum multiplied by the ideal interpolation spectrum:<maths id="math0006" num="(5)"><math display="block"><mrow><msub><mrow><mover accent="true"><mrow><mtext>C</mtext></mrow><mo>¯</mo></mover></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>)X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msub><mrow><mtext>) - C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>)X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>); where:</mtext></mrow></math><img file="EP0777211A2_D0006.tif" /></maths><maths id="math0007" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>C</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0777211A2_D0007.tif" /></maths>_τ(<i>e</i>^jω) is the spectrum of the actual interpolation filter; and X(<i>e</i>^jω) is the spectrum of the input signal. From equation (5), the mean squared error is represented by:<maths id="math0008" num="(6)"><math display="block"><mrow><msubsup><mrow><mtext>E</mtext></mrow><mrow><mtext>τ</mtext></mrow><mrow><mtext>2</mtext></mrow></msubsup><mtext>=</mtext><mfrac><mrow><mtext>1</mtext></mrow><mrow><mtext>2π</mtext></mrow></mfrac><apply><int /><lowlimit><mtext>-π</mtext></lowlimit><uplimit><mtext>π</mtext></uplimit><mrow><mtext>|</mtext><msub><mrow><mover accent="true"><mrow><mtext>C</mtext></mrow><mo>¯</mo></mover></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>) - </mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jωτ</mtext></mrow></msup><msup><mrow><mtext>|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msup><mrow><mtext>)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext mathvariant="italic">d</mtext><mtext>ω</mtext></mrow></apply><mtext>; where:</mtext></mrow></math><img file="EP0777211A2_D0008.tif" /></maths> X(<i>e</i>^jω) is the spectrum of the read channel (e.g., PR4, EPR4, EEPR4 of Table 1 or some other partial response spectrum).

0057In practice, the above mean squared error equation (6) is modified by specifying that the spectrum of the input signal is bandlimitted to some predetermined constant 0 ≤ ω ≤ απ where 0 &lt; α &lt; 1; that is:<maths id="math0009" num=""><math display="block"><mrow><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>)| = 0, for |ω| ≥ απ.</mtext></mrow></math><img file="EP0777211A2_D0009.tif" /></maths> Then equation (6) can be expressed as:<maths id="math0010" num="(7)"><math display="block"><mrow><msubsup><mrow><mtext>E</mtext></mrow><mrow><mtext>τ,α</mtext></mrow><mrow><mtext>2</mtext></mrow></msubsup><mtext> = </mtext><mfrac><mrow><mtext>1</mtext></mrow><mrow><mtext>2π</mtext></mrow></mfrac><apply><int /><lowlimit><mtext>-απ</mtext></lowlimit><uplimit><mtext>απ</mtext></uplimit><mrow><mtext>|</mtext><msub><mrow><mover accent="true"><mrow><mtext>C</mtext></mrow><mo>¯</mo></mover></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>) - </mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jωτ</mtext></mrow></msup><msup><mrow><mtext>|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msup><mrow><mtext>)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext mathvariant="italic">d</mtext><mtext>ω</mtext></mrow></apply><mtext>.</mtext></mrow></math><img file="EP0777211A2_D0010.tif" /></maths> The solution to the minimization problem of equation (7) involves expressing the actual interpolation filter in terms of its coefficients and then solving for the coefficients that minimize the error in a classical mean-square sense.

0058The actual interpolation filter can be expressed as the FIR polynomial:<maths id="math0011" num="(8)"><math display="block"><mrow><msub><mrow><mover accent="true"><mrow><mtext>C</mtext></mrow><mo>¯</mo></mover></mrow><mrow><mtext>τ</mtext></mrow></msub><msup><mrow><mtext>(e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><mtext>) = </mtext><apply><sum /><lowlimit><mtext>n=-R</mtext></lowlimit><uplimit><mtext>n=R-1</mtext></uplimit><mrow><msub><mrow><mtext> C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msup><mrow><mtext>(n)e</mtext></mrow><mrow><mtext>-jωn</mtext></mrow></msup></mrow></apply><mtext>; where:</mtext></mrow></math><img file="EP0777211A2_D0011.tif" /></maths> 2R is the number of taps in each interpolation filter and the sample period Ts has been normalized to 1. A mathematical derivation for an interpolation filter having an even number of coefficients is provided bellow. It is within the ability of those skilled in the art to modify the mathematics to derive an interpolation filter having an odd number of coefficients.

0059Substituting equation (8) into equation (7) leads to the desired expression in terms of the coefficients C_τ(n):<maths id="math0012" num="(9)"><math display="block"><mrow><msubsup><mrow><mtext>E</mtext></mrow><mrow><mtext>τ,α</mtext></mrow><mrow><mtext>2</mtext></mrow></msubsup><mtext> = </mtext><mfrac><mrow><mtext>1</mtext></mrow><mrow><mtext>2π</mtext></mrow></mfrac><apply><int /><lowlimit><mtext>-απ</mtext></lowlimit><uplimit><mtext>απ</mtext></uplimit><mrow><mtext>|</mtext><apply><sum /><lowlimit><mtext>n=-R</mtext></lowlimit><uplimit><mtext>n=R-1</mtext></uplimit><mrow><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(n)</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>-jωn</mtext></mrow></msup><mtext> - </mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jωτ</mtext></mrow></msup><msup><mrow><mtext>|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msup><mrow><mtext>)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext mathvariant="italic">d</mtext><mtext>ω</mtext></mrow></apply><mtext>.</mtext></mrow></apply></mrow></math><img file="EP0777211A2_D0012.tif" /></maths> The next step is to take the derivatives of equation (9) with respect to the coefficients C_τ(n) and set them to zero:<maths id="math0013" num="(10)"><math display="block"><mrow><mfrac numalign="left" denomalign="left"><mrow><msubsup><mrow><mtext>∂E</mtext></mrow><mrow><mtext>τ,α</mtext></mrow><mrow><mtext>2</mtext></mrow></msubsup></mrow><mrow><msub><mrow><mtext>∂C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext>(n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext>)</mtext></mrow></mfrac><msub><mrow><mtext> = 0 for n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext> = -R, ..., 0, 1, ..., R-1.</mtext></mrow></math><img file="EP0777211A2_D0013.tif" /></maths> After careful manipulation, equation (10) leads to:<maths id="math0014" num="(11)"><math display="block"><mrow><apply><int /><lowlimit><mtext>-απ</mtext></lowlimit><uplimit><mtext>απ</mtext></uplimit><mrow><mfenced open="[" close="]"><mrow><mfenced open="(" close=")"><mrow><apply><sum /><lowlimit><mtext>n=-R</mtext></lowlimit><uplimit><mtext>n=R-1</mtext></uplimit><mrow><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext>(n)cos(ω(n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext> - n))</mtext></mrow></apply></mrow></mfenced><msub><mrow><mtext> - cos(ω(n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext> + τ)) </mtext></mrow></mfenced><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msup><mrow><mtext>)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext mathvariant="italic">d</mtext><mtext>ω</mtext></mrow></apply><mtext> = 0</mtext></mrow></math><img file="EP0777211A2_D0014.tif" /></maths>    for n_o = -R, ..., 0, 1, ..., R-1. Defining φ(r) as:<maths id="math0015" num="(12)"><math display="block"><mrow><mtext>φ(r) = </mtext><apply><int /><lowlimit><mtext>-απ</mtext></lowlimit><uplimit><mtext>απ</mtext></uplimit><mrow><mtext>|X(</mtext><msup><mrow><mtext mathvariant="italic">e</mtext></mrow><mrow><mtext>jω</mtext></mrow></msup><msup><mrow><mtext>)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext> cos(ωr) </mtext><mtext mathvariant="italic">d</mtext><mtext>ω</mtext></mrow></apply></mrow></math><img file="EP0777211A2_D0015.tif" /></maths> and substituting equation (12) into equation (11) gives:<maths id="math0016" num="(13)"><math display="block"><mrow><apply><sum /><lowlimit><mtext>n=-R</mtext></lowlimit><uplimit><mtext>n=R-1</mtext></uplimit><mrow><msub><mrow><mtext> C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext>(n)φ(n - n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext>)</mtext></mrow></apply><msub><mrow><mtext> = φ(n</mtext></mrow><mrow><mtext>o</mtext></mrow></msub><mtext> + τ)</mtext></mrow></math><img file="EP0777211A2_D0016.tif" /></maths>    for n_o = -R, ..., 0, 1, ..., R-1 . Equation (13) defines a set of 2R linear equations in terms of the coefficients C_τ(n). Equation (13) can be expressed more compactly in matrix form:<maths id="math0017" num=""><math display="block"><mrow><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>T</mtext></mrow></msub><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext> = Φ</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>; where:</mtext></mrow></math><img file="EP0777211A2_D0017.tif" /></maths> C_τ is a column vector of the form:<maths id="math0018" num=""><math display="block"><mrow><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext> = [c</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext>(-R), ..., c</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext>(0), ..., c</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msup><mrow><mtext>(R-1)]</mtext></mrow><mrow><mtext>t</mtext></mrow></msup></mrow></math><img file="EP0777211A2_D0018.tif" /></maths> Φ_T is a Toeplitz matrix of the form:<maths id="math0019" num=""><img file="EP0777211A2_D0019.tif" /></maths> and Φ_τ is a column vector of the form:<maths id="math0020" num="(14)"><math display="block"><mrow><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msup><mrow><mtext> = [φ(-R+τ), ..., φ(τ), φ(1+τ), ..., φ(R-1+τ]</mtext></mrow><mrow><mtext>t</mtext></mrow></msup><mtext>.</mtext></mrow></math><img file="EP0777211A2_D0020.tif" /></maths> The solution to equation (14) is:<maths id="math0021" num="(15)"><math display="block"><mrow><msub><mrow><mtext>C</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><msub><mrow><mtext> = Φ</mtext></mrow><mrow><mtext>T</mtext></mrow></msub><msup><mrow><mtext> </mtext></mrow><mrow><mtext>-1</mtext></mrow></msup><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>; where:</mtext></mrow></math><img file="EP0777211A2_D0021.tif" /></maths> Φ_T^-1 is an inverse matrix that can be solved using well known methods.

0060Table B2 shows example coefficients C_τ(n) calculated from equation (15) with 2R=6, α=0.8 and X(<i>e</i>^jω)=PR4. The implementation of the six tap FIR filter is shown in Figure B6. A shift register <b>B250</b> receives the channel samples <b>32</b> at the sampling clock rate <b>54</b>. The filter coefficients C_τ(n) are stored in a coefficient register file <b>B252</b> and applied to corresponding multipliers according to the current value of τ <b>B128</b>. The coefficients are multiplied by the channel samples <b>32</b> stored in the shift register <b>B250</b>. The resulting products are summed <b>B254</b> and the sum stored in a delay register <b>B256</b>. The coefficient register file <b>B252</b> and the delay register <b>B256</b> are clocked by the data clock <b>B104</b> to implement the masking function described above.

0061In an alternative embodiment not shown, a plurality of static FIR filters, having coefficients that correspond to the different values of τ, filter the sample values in the shift register <b>B250</b>. Each filter outputs an interpolation value, and the current value of the interpolation interval τ <b>B128</b> selects the output of the corresponding filter as the output <b>B102</b> of the interpolator <b>B122</b>. Since the coefficients of one filter are not constantly updated as in Figure B6, this multiple filter embodiment increases the speed of the interpolator <b>B122</b> and the overall throughput of the read channel.

Cost Reduced Interpolator

0062Rather than store all of the coefficients of the interpolation filters in memory, in a more efficient, cost reduced implementation the coefficient register file <b>B252</b> of Figure B6 computes the filter coefficients C_τ(n) in real time as a function of τ. For example, the filter coefficients C_τ(n) can be computed in real time according to a predetermined polynomial in τ (see, for example, U.S. Pat. No. 4,866,647 issued to Farrow entitled, "A Continuously Variable Digital Delay Circuit," the disclosure of which is hereby incorporated by reference). An alternative, preferred embodiment for computing the filter coefficients in real time estimates the filter coefficients according to a reduced rank matrix representation of the coefficients.

0063The bank of filter coefficients stored in the coefficient register file <b>B252</b> can be represented as an MxN matrix A_MxN, where N is the depth of the interpolation filter (i.e., the number of coefficients C_τ(n) in the impulse response computed according to equation (15)) and M is the number of interpolation intervals (i.e., the number of τ intervals). Rather than store the entire A_MxN matrix in memory, a more efficient, cost reduced implementation is attained through factorization and singular value decomposition (SVD) of the A_MxN matrix.

0064Consider that the A_MxN matrix can be factored into an F_MxN and G_NxN matrix,<maths id="math0022" num=""><math display="block"><mrow><msub><mrow><mtext>A</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub><msub><mrow><mtext> = F</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub><msub><mrow><mtext> · G</mtext></mrow><mrow><mtext>NxN</mtext></mrow></msub><mtext> .</mtext></mrow></math><img file="EP0777211A2_D0022.tif" /></maths> Then a reduced rank approximation of the A_MxN matrix can be formed by reducing the size of the F_MxN and G_NxN matrices by replacing N with L where L&lt;N and, preferably, L&lt;&lt;N. Stated differently, find the F_MxL and G_LxN matrices whose product best approximates the A_MxN matrix,<maths id="math0023" num=""><math display="block"><mrow><msub><mrow><mtext>A</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub><msub><mrow><mtext> ≈ F</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext> · G</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub><mtext> .</mtext></mrow></math><img file="EP0777211A2_D0023.tif" /></maths> The convolution process of the interpolation filter can then be carried out, as shown in Figure B7, by implementing the G_LxN matrix as a bank of FIR filters <b>B260</b> connected to receive the channel sample values <b>32</b>, and the F_MxL matrix implemented as a lookup table <b>B262</b> indexed by τ <b>B128</b> (as will become more apparent in the following discussion). Those skilled in the art will recognize that, in an alternative embodiment, the A_MxN matrix can be factored into more than two matrices (i.e., A ≈ FGH...).

0065The preferred method for finding the F_MxL and G_LxN matrices is to minimize the following sum of squared errors:<maths id="math0024" num="(16)"><math display="block"><mrow><apply><sum /><lowlimit><mtext>j=1</mtext></lowlimit><uplimit><mtext>M</mtext></uplimit><mrow><apply><sum /><lowlimit><mtext>n=1</mtext></lowlimit><uplimit><mtext>N</mtext></uplimit><mrow><msup><mfenced open="(" close=")"><mrow><msub><mrow><mtext>A</mtext></mrow><mrow><mtext>jn</mtext></mrow></msub><msub><mrow><mtext> - (F</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext> · G</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub><msub><mrow><mtext>)</mtext></mrow><mrow><mtext>jn</mtext></mrow></msub></mrow></mfenced><mn>2</mn></msup></mrow></apply></mrow></apply></mrow></math><img file="EP0777211A2_D0024.tif" /></maths> The solution to equation (16) can be derived through a singular value decomposition of the A_MxN matrix, comprising the steps of: <ul id="ul0002" list-style="none"><li>1. performing an SVD on the A_MxN matrix which gives the following unique factorization (assuming M≥N):<maths id="math0025" num=""><math display="block"><mrow><msub><mrow><mtext>A</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub><msub><mrow><mtext> = U</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub><msub><mrow><mtext>·D</mtext></mrow><mrow><mtext>NxN</mtext></mrow></msub><msub><mrow><mtext>·V</mtext></mrow><mrow><mtext>NxN</mtext></mrow></msub><mtext> where:</mtext></mrow></math><img file="EP0777211A2_D0025.tif" /></maths><ul id="ul0003" list-style="none" compact="compact"><li>U_MxN is a MxN unitary matrix;</li><li>D_NxN is a NxN diagonal matrix {σ₁, σ₂, ..., σ_N} where σ_i are the singular values of A_MxN, and σ₁≥ σ₂... ≥ σ_N ≥0; and</li><li>V_NxN is a NxN unitary matrix;</li></ul></li><li>2. selecting a predetermined L number of the largest singular values σ to generate a reduced size diagonal matrix D_LxL:<maths id="math0026" num=""><img file="EP0777211A2_D0026.tif" /></maths></li><li>3. extracting the first L columns from the U_MxN matrix to form a reduced U_MxL matrix:<maths id="math0027" num=""><img file="EP0777211A2_D0027.tif" /></maths></li><li>4. extracting the first L rows from the V_NxN matrix to form a reduced V_LxN matrix:<maths id="math0028" num=""><img file="EP0777211A2_D0028.tif" /></maths></li><li>5. defining the F_MxL and G_LxN matrices such that:<maths id="math0029" num=""><math display="block"><mrow><msub><mrow><mtext>F</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext>·G</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub><msub><mrow><mtext> = U</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext>·D</mtext></mrow><mrow><mtext>LxL</mtext></mrow></msub><msub><mrow><mtext>·V</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub><msub><mrow><mtext> ≈ A</mtext></mrow><mrow><mtext>MxN</mtext></mrow></msub></mrow></math><img file="EP0777211A2_D0029.tif" /></maths>    (for example, let <maths id="math0030" num=""><math display="inline"><mrow><msub><mrow><mtext>F</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext> = U</mtext></mrow><mrow><mtext>MxL</mtext></mrow></msub><msub><mrow><mtext>·D</mtext></mrow><mrow><mtext>LxL</mtext></mrow></msub></mrow></math><img file="EP0777211A2_D0030.tif" /></maths> and <maths id="math0031" num=""><math display="inline"><mrow><msub><mrow><mtext>G</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>LxN</mtext></mrow></msub></mrow></math><img file="EP0777211A2_D0031.tif" /></maths>).</li></ul>

0066In the above cost reduced polynomial and reduced rank matrix embodiments, the interpolation filter coefficients C_τ(n) are computed in real time as a function of τ; that is, the filter's impulse response h(n) is approximated according to:<maths id="math0032" num="(17)"><math display="block"><mrow><msub><mrow><mtext>h(n,τ) = c</mtext></mrow><mrow><mtext>τ</mtext></mrow></msub><mtext>(n) = </mtext><apply><sum /><lowlimit><mtext>i=1</mtext></lowlimit><uplimit><mtext>L</mtext></uplimit><mrow><msub><mrow><mtext> G</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>(n)·f(i,τ)</mtext></mrow></apply><mtext>; where:</mtext></mrow></math><img file="EP0777211A2_D0032.tif" /></maths> f(i,τ) is a predetermined function in τ (e.g., polynomial in τ or τ indexes the above F_MxL matrix); L is a degree which determines the accuracy of the approximation (e.g., the order of the polynomial or the column size of the above F_MxL matrix); and G_i(n) is a predetermined matrix (e.g., the coefficients of the polynomial or the above G_LxN matrix). As L increases, the approximated filter coefficients C_τ(n) of equation (17) tend toward the ideal coefficients derived from equation (15). It follows from equation (17) that the output of the interpolation filter Y(x) can be represented as:<maths id="math0033" num="(18)"><math display="block"><mrow><mtext>Y(x) = </mtext><apply><sum /><lowlimit><mtext>n=1</mtext></lowlimit><uplimit><mtext>N</mtext></uplimit><mrow><mtext> U(x-n)</mtext></mrow></apply><apply><sum /><lowlimit><mtext>i=1</mtext></lowlimit><uplimit><mtext>L</mtext></uplimit><mrow><msub><mrow><mtext>G</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>(n)·f(i,τ)</mtext></mrow></apply></mrow></math><img file="EP0777211A2_D0033.tif" /></maths> where U(x) are the channel sample values <b>32</b> and N is the number of interpolation filter coefficients C_τ(n).

0067Referring again to Figure B6, the coefficient register file can compute the interpolation filter coefficients C_τ(n) according to equation (17) and then convolve the coefficients C_τ(n) with the channel samples U(x) <b>32</b> to generate the interpolated sample values <b>B102</b> synchronized to the baud rate. However, a more efficient implementation of the interpolation filter can be achieved by rearranging equation (18):<maths id="math0034" num="(19)"><math display="block"><mrow><mtext>Y(x) = </mtext><apply><sum /><lowlimit><mtext>i=1</mtext></lowlimit><uplimit><mtext>L</mtext></uplimit><mrow><mtext>f(i,τ)</mtext></mrow></apply><apply><sum /><lowlimit><mtext>n=1</mtext></lowlimit><uplimit><mtext>N</mtext></uplimit><mrow><msub><mrow><mtext>G</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>(n)·U(x-n)</mtext></mrow></apply></mrow></math><img file="EP0777211A2_D0034.tif" /></maths>

0068Figure B7 shows the preferred embodiment of the interpolation filter according to equation (19). In the polynomial embodiment, the function of τ is a polynomial in τ, and the matrix G_i(n) are the coefficients of the polynomial. And in the reduced rank matrix embodiment, the function of τ is to index the above F_MxL matrix <b>B262</b>, and the second summation in equation (19),<maths id="math0035" num=""><math display="block"><mrow><apply><sum /><lowlimit><mtext>n=1</mtext></lowlimit><uplimit><mtext>N</mtext></uplimit><mrow><msub><mrow><mtext>G</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>(n)·U(x-n)</mtext></mrow></apply></mrow></math><img file="EP0777211A2_D0035.tif" /></maths> is implented as a bank of FIR filters <b>B260</b> as shown in Figure B7. Again, in equation (19) L is the depth of the approximation function f(i,τ) (e.g., the order of the polynomial or the column size of the above F_MxL matrix) and N is the depth of the interpolation filter's impulse response (i.e., the number of coefficients in the impulse response). It has been determined that N=8 and L=3 provides the best performance/cost balance; however, these values may be increased as IC technology progresses and the cost per gate decreases.

Servo Data Demodulation

0069The servo data in the servo wedges <b>17</b> of Figure 2A is normally recorded at a constant data rate across the zones of the disk. Prior art methods are known for demodulating the servo data and include: asynchronous servo detection by asynchronously sampling the analog pulses and detecting the servo data with a discrete time peak detector; and synchronous servo detection by synchronously sampling the analog pulses and detecting the servo data with the discrete time sequence detector incorporated into the read channel for synchronous detection of user data.

0070United States patent #5,321,559 entitled "Asynchronous Peak Detection of Information Embedded Within PRML Class IV Sampling Data Detection Channel" discloses an example asynchronous servo detection system, the disclosure of which is hereby incorporated by reference. The general details of the '559 patent are shown in Figure 1A of this patent, wherein the A/D <b>24</b> samples the analog read signal <b>62</b> asynchronously at a fixed frequency, the samples are equalized by the discrete equalizer filter <b>32</b>, and a discrete time peak detector <b>70</b> processes the equalized, asynchronous sample values <b>32</b> to detect peaks representing the servo data. Similar to the prior art analog peak detection read channels, the data stream is segmented into bit cell periods―the presence of a peak during a bit cell represents a "1" bit and the absence of a peak represents a "0" bit. However, there are problems associated with this asynchronous servo detection scheme. Namely, because the pulses are sampled asynchronously, the servo data must be recorded and detected at a very low data rate for accurate pulse detection and bit cell timing. And for the reasons discussed above, the analog receive filter must be programmed relative to the servo sampling rate in order to attenuate aliasing noise.

0071A synchronous servo detection system, such as the one disclosed in United States patent #5,384,671 entitled "PRML Sampled Data Channel Synchronous Servo Detector" hereby incorporated by reference, allows for increased servo data rates due to synchronously detecting the pulses which compensates for intersymbol interference and increases immunity to channel noise. The general details of the '671 patent are shown in Figure 1A of this patent, wherein the timing recovery <b>28</b> causes the A/D <b>24</b> to sample the analog read signal synchronous to the data rate. The discrete time equalizer filter <b>26</b> equalizes the synchronized samples, and a discrete time sequence detector <b>34</b>, such as a Viterbi detector, detects the servo data. The problem with this synchronous implementation, however, is that timing recovery must synchronize, as close as possible, the sampling rate to the data rate. Errors in timing recovery will quickly degrade the servo detection accuracy. This requires additional overhead in the servo wedges in the form of an acquisition preamble used to synchronize timing recovery before sampling the servo data. Further, synchronous PRML servo detection requires a separate frequency synthesizer to generate a center sampling frequency for timing recovery, as discussed in greater detail in the above referenced U.S. patent application entitled "Sampled Amplitude Read Channel For Reading User Data and Embedded Servo Data From a Magnetic Medium". And for the reasons discussed above, the analog receive filter must be programmed relative to the servo sampling rate in order to attenuate aliasing noise.

0072The servo demodulation technique of the present invention is shown in Figure B3. It provides, in a first embodiment, a hybrid of the above mentioned asynchronous peak detection and synchronous PRML detection techniques and, as such, allows for a servo data rate in-between the two. In an alternative embodiment, the present invention provides a synchronous PRML detection scheme similar to the above mentioned prior art except that sampled timing recovery <b>28</b> is replaced with interpolated timing recovery <b>B100</b>. Both embodiments replace the programmable analog receive filter <b>20</b> with a less complex fixed analog receive filter <b>20</b> having a fixed cutoff frequency for attenuating aliasing noise before sampling <b>24</b>. The read frequency synthesizer <b>53</b> clocks the sampling device <b>24</b> at the same frequency used for reading the user data sectors <b>15</b> (i.e., the sampling rate is not adjusted when reading a servo wedge <b>17</b>). The equalizer filter <b>26</b> equalizes the asynchronous samples <b>25</b>, and interpolated timing recovery <b>B100</b> generates synchronized interpolated data <b>B102</b>.

0073In the hybrid peak detection implementation, the interpolated sample values <b>B102</b> are only partially synchronized to the frequency of the pulse data, thereby increasing the accuracy of the peak detector <b>70</b> and allowing for a higher servo data rate over the prior art asynchronous peak detection technique. Interpolated timing recovery <b>B100</b> does not synchronize the sample values exactly to the pulse frequency because the peak detector does not compensate for intersymbol interference; that is, the servo data is recorded with sufficient spacing between pulses to avoid intersymbol interference (which can be accomplished by decreasing the data density or through (d,k) RLL encoding/decoding). Since partial synchronization does not significantly degrade how the peak detector performs, it is not necessary for timing recovery to acquire a preamble before reading the servo data.

0074Alternatively, if the discrete time sequence detector <b>34</b> detects the servo data, then interpolated timing recovery <b>B100</b> synchronizes first to a preamble and then to the servo data. Again, the present invention provides an advantage over the prior art synchronous PRML servo detection systems: it uses an analog receive filter <b>20</b> with a fixed, rather than programmable, frequency response, thereby reducing the filter's complexity and cost and improving the yield of the read channel.

0075In both embodiments of the present invention for servo detection, interpolated timing recovery <b>B100</b> generates a synchronous data clock <b>B104</b>, discussed in greater detail above, for clocking operation of the discrete time peak detector <b>B70</b> and the discrete time sequence detector <b>34</b>.

0076Although the interpolated timing recovery of the present invention has been disclosed in relation to a d=0 PR4 read channel, the principles disclosed herein are equally applicable to other types of sampled amplitude read channels such as d=1 EPR4 or EEPR4 read channels. In a d=1 read channel, the slicer <b>B141</b> of Figure B4A is replaced by a pulse detector as described in the above reference U.S. Patent No. 5,359,631.

0077The objects of the invention have been fully realized through the embodiments disclosed herein. Those skilled in the art will appreciate that the aspects of the invention can be achieved through various other embodiments without departing from the spirit and scope of the invention. The particular embodiments disclosed are illustrative and not meant to limit the scope of the invention as appropriately construed by the following claims. <tables id="tabl0001" num="0001"><table frame="all"><title>Table 1</title><tgroup cols="3" colsep="1" rowsep="1"><colspec colnum="1" colname="col1" colwidth="52.50mm" /><colspec colnum="2" colname="col2" colwidth="52.50mm" /><colspec colnum="3" colname="col3" colwidth="52.50mm" /><thead valign="top"><row><entry namest="col1" nameend="col1" align="center">Channel</entry><entry namest="col2" nameend="col2" align="center">Transfer Function</entry><entry namest="col3" nameend="col3" align="left">Dipulse Response</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">PR4</entry><entry namest="col2" nameend="col2" align="left">(1-D)(1+D)</entry><entry namest="col3" nameend="col3" align="left">0, 1, 0, -1, 0, 0, 0, ...</entry></row><row><entry namest="col1" nameend="col1" align="left">EPR4</entry><entry namest="col2" nameend="col2" align="left">(1-D)(1+D)²</entry><entry namest="col3" nameend="col3" align="left">0, 1, 1, -1, -1, 0, 0, ...</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">EEPR4</entry><entry namest="col2" nameend="col2" align="left">(1-D)(1+D)³</entry><entry namest="col3" nameend="col3" align="left">0, 1, 2, 0, -2, -1, 0, ...</entry></row></tbody></tgroup></table></tables><tables id="tabl0002" num="0002"><table frame="all"><title>Table B2</title><tgroup cols="7" colsep="1" rowsep="0"><colspec colnum="1" colname="col1" colwidth="22.50mm" /><colspec colnum="2" colname="col2" colwidth="22.50mm" /><colspec colnum="3" colname="col3" colwidth="22.50mm" /><colspec colnum="4" colname="col4" colwidth="22.50mm" /><colspec colnum="5" colname="col5" colwidth="22.50mm" /><colspec colnum="6" colname="col6" colwidth="22.50mm" /><colspec colnum="7" colname="col7" colwidth="22.50mm" /><thead valign="top"><row rowsep="1"><entry namest="col1" nameend="col1" align="center">τ·32/Ts</entry><entry namest="col2" nameend="col2" align="center">C(-2)</entry><entry namest="col3" nameend="col3" align="right">C(-2)</entry><entry namest="col4" nameend="col4" align="right">C(0)</entry><entry namest="col5" nameend="col5" align="right">C(1)</entry><entry namest="col6" nameend="col6" align="center">C(2)</entry><entry namest="col7" nameend="col7" align="right">C(3)</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="right">0</entry><entry namest="col2" nameend="col2" align="char" char=".">0.0000</entry><entry namest="col3" nameend="col3" align="char" char=".">-0.0000</entry><entry namest="col4" nameend="col4" align="char" char=".">1.0000</entry><entry namest="col5" nameend="col5" align="char" char=".">0.0000</entry><entry namest="col6" nameend="col6" align="char" char=".">-0.0000</entry><entry namest="col7" nameend="col7" align="char" char=".">0.0000</entry></row><row><entry namest="col1" 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char=".">0.0268</entry></row><row><entry namest="col1" nameend="col1" align="right">5</entry><entry namest="col2" nameend="col2" align="char" char=".">0.0407</entry><entry namest="col3" nameend="col3" align="char" char=".">-0.0979</entry><entry namest="col4" nameend="col4" align="char" char=".">0.9536</entry><entry namest="col5" nameend="col5" align="char" char=".">0.1829</entry><entry namest="col6" nameend="col6" align="char" char=".">-0.0608</entry><entry namest="col7" nameend="col7" align="char" char=".">0.0331</entry></row><row><entry namest="col1" nameend="col1" align="right">6</entry><entry namest="col2" nameend="col2" align="char" char=".">0.0473</entry><entry namest="col3" nameend="col3" align="char" char=".">-0.1120</entry><entry namest="col4" nameend="col4" align="char" char=".">0.9359</entry><entry namest="col5" nameend="col5" align="char" char=".">0.2230</entry><entry namest="col6" nameend="col6" align="char" char=".">-0.0728</entry><entry namest="col7" nameend="col7" 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