Semiconductor integrated circuit device including protection means
Abstract
When an element of an internal circuit is arranged in the vicinity of an input/output terminal of an LSI chip, electrostatic break down is caused in an internal circuit element by discharge current generated between an input/output terminal and a grounding terminal or a power source terminal. Therefore, the elements are arranged with a distance to cause dead space therebetween to make down-sizing of the LSI chip difficult. Therefore, a resistor is disposed between an input/output terminal and a protection element connected thereto. The resistor causes increasing of resistance of a current path from the input/output terminal to the grounding terminal, at the common wiring. Thus influence of the electrostatic break down for the element of the internal circuit can be restricted to permit location of the resistor to permit the internal circuit element to be arranged in the vicinity of the protection element of the input/output terminal. Thus, a problem of the dead space can be solved and down-sizing of the LSI is enabled.

Term
Term ended
Projected expiry passed 14 November 2016, 9.9 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
1 sheet
Sheet 1
Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| EP0109070A1 | Cites | European Patent Office (EPO) | A | Search report | 1,7,8 |
| EP0632560A2 | Cites | European Patent Office (EPO) | XY | Search report | 1 |
| US4131908A | Cites | United States of America | A | Search report | 1-10 |
| US5449939A | Cites | United States of America | YA | Search report | 2-10 |
8 members in 5 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 29655095 | Japan | – | |
| 29655095 | Japan | A |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| EP0774784A2 | European Patent Office (EPO) | A2 | |
| JPH09139468A | Japan | A | |
| KR970030780A | Republic of Korea | A | |
| TW314656B | Taiwan Province of China | B | |
| US5828107A | United States of America | A | |
| KR100206675B1 | Republic of Korea | B1 | |
| JP3019760B2 | Japan | B2 | |
| EP0774784A3This record | European Patent Office (EPO) | A3 |
8 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Application withdrawnWithdrawn18W | 18W | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE APPLICATION HAS BEEN WITHDRAWNSTAA | STAA | |
| First examination report despatched17Q | 17Q | |
| Request for examination filed17P | 17P | |
| Designated contracting statesAK | AK | |
| Search report despatchedORIGINAL CODE: 0009013PUAL | PUAL | |
| Designated contracting statesAK | AK | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 0774784
- Application
- 961182771
Titles3
- German
- Integrierte Halbleiterschaltungsanordnung mit einem Schutzmittel
- English
- Semiconductor integrated circuit device including protection means
- French
- Dispositif de circuit intégré semi-conducteur comprenant des moyens de protection
Classification
- CPC, 3
- H10D89/601
- H10D84/00
- H10D89/711
- IPC, 3
- H10D84 03
- H10D84 00
- H10D84 40
Designated states1
- Contracting states, 1
- United Kingdom