Memory devices with selectable access type and systems and methods using the same

A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.