An apparatus and method for a data path implemented using non-differential current mode techniques

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

0001This invention relates generally to dynamic random access memory (DRAM) units and, more particularly, to the signal paths which couple the local input/output (I/O) devices and the storage cells in dynamic semiconductor memories.

DESCRIPTION OF THE RELATED ART

0002In order to increase the speed of DRAM units, the use of current-mode techniques, as opposed to voltage mode techniques have been proposed to minimize the effect of parasitic capacitance over long data lines. However, typical current-mode circuits are implemented using differential circuit techniques. While the differential techniques have the advantage that the two interconnect lines simplify the detection of the signal, the two interconnect lines provide an undesirable increase in the area required to implement the signal path on the semiconductor chip.

0003A need has therefore been felt for apparatus and an associated technique which can take advantage of the increased speed of the current-mode techniques without incurring the penalty of increased implementing area.

SUMMARY OF THE INVENTION

0004The aforementioned and other features are accomplished, according to the present invention, by apparatus for converting the differential output signals from the sense amplifiers of a dynamic random access memory unit to a non-differential current mode signal. The current mode signal is applied to a data line. The non-differential current mode signal transmitted by the data line is applied to apparatus which converts the current mode signal first to a small swing voltage signal and then to a large swing voltage signal suitable for use with circuits coupled to the dynamic random access memory unit. To convert the small swing voltage signal to a large swing voltage signal, sample and hold apparatus stores a reference signal against which the small swing voltage signal is compared. The comparison of the reference signal and the small voltage signal determined by the logic state detected by the sense amplifiers generates a full voltage swing output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

0005The present invention will now be further described, by way of example with reference to the accompanying drawings in which; <ul id="ul0001" list-style="none"><li>Figure 1 is a block diagram of the data path non-differential current mode apparatus of the present invention;</li><li>Figure 2 is a schematic circuit diagram of the data path non-differential current mode apparatus of the present invention;</li><li>Figure 3 illustrates a simulated READ '0' transition for the present invention; and</li><li>Figure 4 illustrates a simulated READ '1' transition for the present invention.</li></ul>

DESCRIPTION OF THE PREFERRED EMBODIMENTS

DETAILED DESCRIPTION OF THE DRAWINGS

0006Referring now to Fig. 1, a block diagram of the non-differential, current mode data path, according to the present invention, along with associated memory components of a memory unit, for retrieving data from a storage cell array is shown. The local input/output signal (LOCAL I/O SIGNAL) and the logical complement (LOCAL I/O SIGNAL_), both from the storage cell array 6 is applied to the differential voltage-to-current conversion unit 5. The output signal (I_o ± DELTA I) from the differential signal-to-current conversion unit is applied through the data line 2 to the current-to-small swing voltage conversion sub-unit 11 of the current-to-full swing voltage conversion unit 10. The output signal (V_o ± DELTA V) from the current-to-small swing voltage conversion sub-unit is applied to the small swing voltage-to-full swing voltage conversion subunit 12, sub-unit 12 providing the output signal V_OUT (0->V_DD) for the non-differential, current mode data path. This signal V_OUT is applied to buffer unit 9. For storing data in the storage cell array 6, buffer unit 9 applies signals through data line transmitter 8 to the data line 2. The signals transmitted by the data line 2 are applied through data line receiver unit 7 to the LOCAL I/O signal terminal and the LOCAL I/O_ signal terminals to the storage cell array 6.

0007Referring to Fig. 2, a schematic diagram of the non-differential, current mode data path, according to the present invention, is shown. The LOCAL I/O SIGNAL is applied to a gate terminal of N-channel field effect transistor MN1, while the LOCAL I/O SIGNAL_ is applied to a gate terminal of N-channel field effect transistor MN2. The BIAS SIGNAL is applied to a gate terminal of n-channel field effect transistor MN3 and to a gate terminal of n-channel field effect transistor MN9, while a source terminal of transistor MN3 is coupled to supply terminal V_SS. A drain terminal of transistor MN3 is coupled to a source terminal of transistor MN1 and to a source terminal of transistor MN2. A drain terminal of transistor MN1 is coupled to a drain and a gate terminal of p-channel field effect transistor MP1 and to a gate terminal of p-channel field effect transistor MP2. The source terminal of transistor MP1 and the source terminal of transistor MP2 are coupled to supply terminal V_DD. The drain terminal of transistor MP2 is coupled to a drain terminal of transistor MN2, to a gate and drain terminal of p-channel field effect transistor MP4, to a gate and a drain terminal of n-channel field effect transistor MN4, and to a gate terminal of P-channel field effect transistor MP3. The source terminal of transistor MN4 is coupled to voltage supply terminal V_SS. The source terminal of transistor MP4 and the source terminal of transistor MP3 are coupled to the voltage supply terminal V_DD. The drain terminal of transistor MP3 is coupled through data line RES10 to a drain and a gate terminal of n-channel field effect transistor MN5 and to a gate terminal of n-channel field effect transistor MN6. The data line RES10 has both distributed resistance and distributed capacitance associated therewith. The source terminal transistor MN5 and the drain terminal of transistor MN6 are coupled to the voltage supply terminal V_SS. A drain terminal of transistor MN6 is coupled to a drain and a gate terminal of p-channel transistor MP5, to a gate terminal of transistor of n-channel field effect transistor MN7, and to a drain terminal of n-channel field effect transistor MN10. The source terminal of transistor MP5 is coupled to the voltage supply terminal V_DD. A drain terminal of transistor MN7 is coupled to a drain terminal and a gate terminal of p-channel field effect transistor MP6 and to a gate terminal of p-channel transistor field effect transistor MP7. A source terminal of transistor MP6 and a source terminal of transistor MP7 are coupled to the voltage supply terminal V_DD. A source terminal of transistor MN7 is coupled to a drain terminal of transistor MN9 and a source terminal of n-channel field effect transistor MN8. A source terminal of transistor MN9 is coupled to the voltage supply terminal V_SS. A gate terminal of transistor MN10 is coupled to an EQ SIGNAL. A source terminal of transistor MN10 is coupled to a gate terminal of transistor MN8 and through capacitor C1 to the voltage supply terminal V_SS. A drain terminal of transistor MN8 and a drain terminal of transistor MP7 are coupled to the output terminal.

0008Referring to Figs. 3 and 4, simulated waveforms for the READ '0' transition (i.e., LOCAL I/O SIGNAL -> low, LOCAL I/O SIGNAL_ -> high) and the READ '1' (LOCAL I/O SIGNAL -> high, LOCAL I/O SIGNAL -> low), respectively are shown. During the first 20 nanoseconds, the voltage V₁ (i.e., the voltage applied to the gate terminal of transistor MN7) and the voltage V_REF (i.e., the voltage applied to the gate of transistor MN8) are equalized. After the equalization period, then the data read, '0' in Fig. 3 and '1' in Fig. 4, is initiated.

OPERATION OF THE PREFERRED EMBODIMENTS

0009The general concept of the present non-differential, current mode data path is shown in Fig. 1. The LOCAL I/O SIGNALS (and their complements) are conventional full swing differential signals originating from sense amplifiers. These differential input signals are converted to non-differential, current mode signals with an approximately constant voltage and a current swing of I_o ± DELTA I. Because the voltage swing is limited (ideally zero), the capacitance of the data line has little effect on the propagation delay. At the receiver end of the data line, the current mode signal is converted to a full swing CMOS output signal level suitable for use by the coupled circuitry. The current-to-full swing conversion is accomplished in practice in two increments. The first increment converts the current swing to a small swing voltage signal V_o ± DELTA V. This small swing voltage signal is then converted to a full swing CMOS level by the second stage.

0010The implementation of the non-differential, current mode data line, according to the present invention is shown in Fig. 2. The differential voltage of the LOCAL I/O SIGNALs is converted to a signal voltage output using a differential amplifier (i.e., transistors MP1-MP2 and MN1-MN3). The output of the differential amplifier drives the gate of transistor MP3, the transistor MP3 modulating the current through the data line. The voltage applied to the gate of transistor MP3 is limited by transistors MP4 and MN4 to ensure that the transistor MP3 remains in saturation. At the receiver end of the data line, a current mirror is formed by transistors MN5 and MN6. The mirrored current through MN6 is passed through a diode-connected transistor MP5, thereby creating a voltage swing at the gate of transistor MN7.

0011In the typical differential data line implementation, the conversion to a full voltage swing signal is easily accomplished because the differential voltage between the two lines is increasing either positively or negatively. For the non-differential situation, this conversion is more difficult because the voltage signal is swinging around the positive voltage. To perform the conversion in the preferred embodiment voltage applied to the gate of transistor MN7 should be compared to a reference voltage. In the preferred embodiment, the reference voltage is supplied by a sample and hold technique, i.e., sampling the initial voltage a the gate of MN7 during precharge and holding this sampled voltage during the data sense operation. This sampling process eliminates the potential problem of having a reference voltage that shifts independently of the operation point of the data path circuitry, a process which could result in a reduced operation margin.

0012The comparator consists of a differential amplifier formed by transistors MP6-MP7 and MN7-MN9. The small swing voltage at the gate of transistor MN7 is coupled to one end of the differential amplifier. The voltage at the gate of transistor MN8 is generated before the sensing begins by bringing the EQ SIGNAL high. The LOCAL I/O SIGNALS are equalized at this time and the voltage at the gate of transistor MN7 is therefore at the equilibrium center value. With the EQ SIGNAL high, transistor MN10 is on, a condition which equalizes the voltage applied to the gate of transistor MN7 and the voltage applied to the gate of transistor MN8 and charges the capacitor C1. When the EQ SIGNAL turned off, capacitor C1 maintains the gate voltage of transistor MN8 at the precharged level. Once the LOCAL I/O SIGNALs separate, the gate voltage at transistor MN7 either swings up or swings down from the initial value, the polarity of the swing depending on the sensed state. The voltage V_OUT therefore swing positively or negatively, accordingly. In practice, an inverter or latch unit would be the next stage to ensure that the full swing voltage level is maintained.

0013While the invention has been described with particular reference to the preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements of the preferred embodiment without departing from the invention. In addition, many modifications may be made to adapt a particular situation and material to a teaching of the present invention without departing from the essential teachings of the present invention.

0014As is evident from the foregoing discussion, certain aspects of the invention are not limited to the particular details of the examples illustrated, and it is therefore contemplated that other modifications and applications will occur to those skilled in the art. For example, certain control signals needed to activate and coordinate the memory unit are not shown. Similarly, in the implementation of the present invention, provision would have to be made to eliminate the current drain when the device is in a standby mode of operation. It is accordingly intended that the claims shall cover all modifications and applications as do not depart from the spirit and scope of the invention.