Image processing method and apparatus

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an image processing method and apparatus and, more particularly, to motion detection processing of an input image signal.

Related Background Art

Along with recent trends toward smaller, multimedia-oriented computers, display devices in computers have remarkably advanced. As display devices, liquid crystal display devices have been popularly used. As one of such display devices, a display device using a ferroelectric liquid crystal display device (to be abbreviated as an FLCD hereinafter) is known.

As the feature of the FLCD, a high-definition display device with a large screen can be obtained. However, since a liquid crystal element itself is a binary device which cannot change the transmittance of light in an analog manner, pseudo gradation levels are expressed by combinations of ON and OFF dots upon displaying a full-color image or the like. That is, digital halftone processing must be performed to reproduce a halftone image.

Since it is difficult to display data on a large screen at a rate of 30 frames per second or more, only a portion in which a motion is detected in a frame must be rewritten by utilizing the memory characteristics as the feature of the FLCD. For this purpose, a portion including a motion in an image must be detected. Conventionally, the following method of detecting a motion is used.

Fig. 1 is a block diagram of an image processing apparatus for an FLCD, which is adapted to display an analog image signal supplied from a computer on an FLCD and includes a motion detection circuit.

Referring to Fig. 1, an analog image signal output from a computer (not shown) is converted by an A/D converter 1 into a digital signal having a predetermined number of gradation levels, e.g., a 24-bit digital signal (8 bits for each of R, G, and B colors).

A gradation conversion circuit 2 converts the R, G, and B digital signals output from the A/D converter 1 into a digital signal having a number of resolution levels that can be displayed by a display device 7, e.g., a 3-bit digital signal (1 bit for each of R, G, and B colors) by known digital halftone processing such as the dither method, the error diffusion method, or the like. The digital signal output from the gradation conversion circuit 2 is stored in a binary frame memory 5.

On the other hand, the digital signal output from the A/D converter 1 is input to a motion detector 9. The motion detection 9 will be described in detail below.

Fig. 2 is a block diagram showing the motion detector 9.

Referring to Fig. 2, the image signal input from the A/D converter 1 is stored in a line buffer 901 having a predetermined capacity for K pixels. As shown in Fig. 2, the line buffer is designed to store K pixels, and pixel data stored in the line buffer are subjected to weighted mean processing given by equation (1) below via a multiplier 902, an adder 903, and an accumulator 904 so as to be converted into a feature value S_t corresponding to a set of K pixels:<maths id="math0001" num=""><img file="EP0757331B1_D0001.tif" /></maths> where w_i is a weighting coefficient determined in advance by a predetermined method, and an image which is being processed is assumed to belong to the t-th frame. Subsequently, the calculated feature amount S_t is compared with a feature amount S_t-1, which was calculated based on image data of the previous frame and was stored in a feature amount memory 10 in Fig. 1, by a comparison controller 905. In this case, a difference ΔS as the comparison result is compared with a predetermined threshold value T, and if the following inequality holds, it is determined that a motion is detected from the corresponding line portion, and the line address of the pixels at that time is output to a frame memory control circuit 4:<maths id="math0002" num="(2)"><math display="block"><mrow><mtext mathvariant="italic">ΔS</mtext><mtext> = </mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext mathvariant="italic">t</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext mathvariant="italic">t</mtext></mrow></msub><msub><mrow><mtext>​</mtext></mrow><mrow><mtext>-1</mtext></mrow></msub><mtext></mtext><mtext mathvariant="italic">&gt; T</mtext></mrow></math><img file="EP0757331B1_D0002.tif" /></maths> Note that the line address is the start address of K successive pixels.

The above-mentioned motion detection processing is performed in units of R, G, and B colors, and the calculated feature amount is newly stored in the feature amount memory 10. The frame memory control circuit 4 outputs data of the motion-detected line from the digital signal (1 bit for each of R, G, and B colors) stored in the binary frame memory 5 on the basis of the address information output from the motion detector 9. With the above-mentioned processing, continuous analog image signals are converted into signals having a predetermined number of gradation levels, and a motion between adjacent frames is detected to partially rewrite an image to be displayed, thus realizing an image display operation in real time.

However, in the above-mentioned prior art, in order to attain motion detection, the feature amount obtained from image data of the previous frame must be stored in the feature amount memory 10.

In particular, since the screen size has been increasing in recent years, the capacity required for the feature amount memory is also increasing, resulting in an increase in cost of the apparatus.

Upon execution of motion detection, binary pixel data may be directly compared with each other without calculating any feature amount. However, in this case, if an image signal includes noise from the transmission route, a binary image bit is easily inverted, resulting in a detection error.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above situation, and has as its object to provide an image processing method and apparatus, which can reduce the capacity of a feature amount memory required for motion detection as much as possible so as to attain a cost reduction of the system, and hardly causes a detection error due to noise.

The image processing apparatus of the present invention is apparatus of the type, such as known from European Patent Application EP-A-0608053, comprising: <ul id="ul0001" list-style="none" compact="compact"><li>a) conversion means for converting an input image signal having a number of gradation levels into an image signal having a smaller number of gradation levels;</li><li>b) storage means for storing the image signal converted by the conversion means. In the apparatus known from EP-A-0608053, the motion of the image is detected on the basis of the signal input during a current period and the image detected in a previous period. The apparatus in accordance with the present invention, which is intended to achieve the above object, is characterised by: </li><li>c) restoration means for restoring the image signal stored in the storage means; and</li><li>d) detection means for detecting a motion of an image on the basis of the image signal input during a current period and the image signal in a previous period, which is restored by the restoration means.</li></ul>

Furthermore, the image processing method, in accordance with the present invention, comprises: <ul id="ul0002" list-style="none" compact="compact"><li>a) a conversion step of converting an input image signal having a number of gradation levels into an image signal having a smaller number of gradation levels;</li><li>b) a storing step of storing the image signal converted by the conversion means in a storage means;    characterised by:</li><li>c) a restoration step of restoring the image signal stored in the storage means; and</li><li>d) a detection step of detecting a motion of an image on the basis of the image signal input during a current period and the image signal in a previous period, which is restored in the restoration step.</li></ul>

Other objects, features and advantages of the invention will become apparent form the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<ul id="ul0003" list-style="none" compact="compact"><li>Fig. 1 is a block diagram showing a conventional image processing apparatus;</li><li>Fig. 2 is a block diagram showing a motion detector 9 shown in Fig. 1;</li><li>Fig. 3 is a block diagram showing an image processing apparatus according to the first embodiment of the present invention;</li><li>Fig. 4 is a detailed block diagram for explaining the processing of a motion detector 13 shown in Fig. 3;</li><li>Fig. 5 is a block diagram showing an image processing apparatus according to the second embodiment of the present invention;</li><li>Fig. 6 is a graph showing an example of a nonlinear function in a gradation conversion circuit shown in Fig. 5; and</li><li>Fig. 7 is a block diagram showing the arrangement of a comparison circuit shown in Fig. 5.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will be described hereinafter.

Fig. 3 is a block diagram showing an image processing apparatus according to the first embodiment of the present invention.

Referring to Fig. 3, the apparatus comprises an A/D converter 11, a gradation conversion circuit 12, a motion detector 13, a frame memory control circuit 14, a binary frame memory 15, a display device 17, and a filter (to be referred to as an LPF hereinafter) 16 having low-pass characteristics with coefficients shown in Fig. 4 and equation (5) shown later.

The operation of the image processing apparatus with the arrangement shown in Fig. 3 will be explained below.

An analog image signal output from a computer (not shown) is converted by the A/D converter 11 into a digital signal having a predetermined number of gradation levels, e.g., a 24-bit digital signal (8 bits for each of R, G, and B colors). The gradation conversion circuit 12 converts the digital signal output from the A/D converter 11 into a digital signal having a number of gradation levels that can be displayed by the display device 17, e.g., a 3-bit digital signal (1 bit for each of R, G, and B colors) by the dither method. The digital signal output from the gradation conversion circuit 12 is stored in the binary frame memory 15.

On the other hand, the digital signal output from the A/D converter 11 is input to the motion detector 13. The motion detector 13 will be described in detail below with reference to Fig. 4.

Referring to Fig. 4, the image signal output from the A/D converter 11 is stored in a line buffer 301 having a predetermined capacity for K pixels. As shown in Fig. 4, the line buffer 301 is designed to store K pixels, and in this case, K pixels starting from the pixel at a coordinate position (i, j) in the scanning direction in the t-th frame are input to the line buffer 301. The pixel data stored in the line buffer 301 are subjected to weighted mean processing given by equation (3) below via a multiplier 302, an adder 303, and an accumulator 304 so as to be converted into a feature value S_t corresponding to a set of K pixels:<maths id="math0003" num=""><img file="EP0757331B1_D0003.tif" /></maths> where w_k is a coefficient determined in advance by a predetermined method, and P_t(i, j) indicates the pixel at a coordinate position (i, j) in an image of the t-th frame. On the other hand, from binary image data of the (t-1)-th frame stored in the binary frame memory 5, pixel data for a total of nine neighboring pixels including the pixel at the position (i, j) as the center are fetched by the LPF 16, and are subjected to a calculation given by equation (4) below so as to be converted into a mean value by weighted mean processing among surrounding pixels:<maths id="math0004" num=""><img file="EP0757331B1_D0004.tif" /></maths> where A_mn is a coefficient to be multiplied with each pixel, and consists of values given by equation (5) below:<maths id="math0005" num=""><img file="EP0757331B1_D0005.tif" /></maths>

The mean value P̂_t-1(i, j) is a restored value P_t-1(i, j) obtained by the weighted mean processing of surrounding pixels from the gradation-converted value.

The obtained restored value P̂_t-1(i, j) is set in another line buffer 306 arranged in the motion detector 13. Subsequently, the same processing as described above is performed for K binary pixel data and a mean value of the K pixels is set in the line buffer 306. The pixel data stored in the line buffer 306 are subjected to weighted mean processing given by equation (6) below via a multiplier 307, an adder 308, and an accumulator 309, and are converted into a feature value S_t-1 corresponding to a set of K pixels:<maths id="math0006" num=""><img file="EP0757331B1_D0006.tif" /></maths> where w_k is the same weighting coefficient as that used upon calculating S_t above. The obtained two feature amounts S_t and S_t-1 are input to a comparison controller 305. The comparison controller 305 compares the two values, and then compares a difference ΔS as the comparison result with a predetermined threshold value T. If the following inequality holds, the controller 305 determines that a motion is detected in the corresponding line portion, and outputs the line address of the pixels at that time to the frame memory control circuit 14 shown in Fig. 3:<maths id="math0007" num="(7)"><math display="block"><mrow><mtext>Δ</mtext><mtext mathvariant="italic">S</mtext><mtext> = </mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext mathvariant="italic">t</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext mathvariant="italic">t</mtext></mrow></msub><msub><mrow><mtext>​</mtext></mrow><mrow><mtext>-1</mtext></mrow></msub><mtext> &gt; </mtext><mtext mathvariant="italic">T</mtext></mrow></math><img file="EP0757331B1_D0007.tif" /></maths> Note that the line address is the start address of K successive pixels. The above-mentioned motion detection processing is performed in units of R, G, and B colors.

The frame memory control circuit 14 controls the binary frame memory 15 to output data of the motion-detected line to the display device 17 on the basis of the address information output from the motion detector 13. With the above-mentioned processing, continuous analog image signals are converted into signals having a predetermined number of gradation levels, and a motion between adjacent frames is detected to partially rewrite an image to be displayed, thus realizing an image display operation in real time.

Fig. 5 is a block diagram showing an image processing apparatus according to the second embodiment of the present invention. Note that the same reference numerals in Fig. 5 denote the same parts as in Fig. 3, and a detailed description thereof will be omitted.

The apparatus shown in Fig. 5 comprises a comparison circuit 18.

The operation of the image processing apparatus with the arrangement shown in Fig. 5 will be described below.

An analog image signal output from a computer (not shown) is converted by the A/D converter 11 into a digital signal u having a predetermined number of gradation levels, e.g., 256 gradation levels per color. The signal u is converted into a signal having the number of gradation levels that can be displayed by the display device 17, e.g., two gradation levels per color, by the gradation conversion circuit 12, and the converted signal is output to the binary frame memory 15.

Note that the display device 17 comprises an FLCD, and only a portion including a motion in an image for one frame as compared to the previous frame is output from the binary frame memory 15 under the control of the frame memory control circuit 14. With this arrangement, a motion between adjacent frames is detected by the comparison circuit 18.

The gradation conversion circuit 12 comprises a cellular neural network in which neurons are locally coupled.

Upon converting an image having a size of M x N into that having two gradation levels, the operation of the cellular neural network is defined as:<maths id="math0008" num=""><img file="EP0757331B1_D0008.tif" /></maths> where A_ijmn and B_ijmn are weights to be multiplied with a connection from the neuron at a position (m, n) to the neuron at a position (i, j). Also, u_mn and y_mn are respectively input and output image data at the position (m, n). The cellular neural network generates an output image that minimizes a distortion function set as follows by the operation given by equations (8) above.

A distortion function dist(y_i, u_i) is defined as equation (9) below from a square error of the filtering result of the i-th gradation-converted output image y_i using a predetermined filter H and the input image u_i before conversion:<maths id="math0009" num="(9)"><math display="block"><mrow><mtext mathvariant="italic">dist</mtext><mtext>(</mtext><msub><mrow><mtext mathvariant="italic">y</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><msub><mrow><mtext mathvariant="italic">, u</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext>) = </mtext><mfrac><mrow><mtext>1</mtext></mrow><mrow><mtext mathvariant="italic">MN</mtext></mrow></mfrac><mtext>(</mtext><msub><mrow><mtext mathvariant="italic">Hy</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">u</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><msup><mrow><mtext>)</mtext></mrow><mrow><mtext mathvariant="italic">T</mtext></mrow></msup><mtext>(</mtext><msub><mrow><mtext mathvariant="italic">Hy</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">u</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0757331B1_D0009.tif" /></maths>

By comparing this distortion function and the energy function of the neural network, weights as the parameters of the network are set as follows:<maths id="math0010" num="(10)"><math display="block"><mrow><mtext mathvariant="italic">A</mtext><mtext> = -</mtext><msup><mrow><mtext mathvariant="italic">H</mtext></mrow><mrow><mtext mathvariant="italic">T</mtext></mrow></msup><mtext mathvariant="italic">H</mtext><mtext> + </mtext><mtext mathvariant="italic">diag</mtext><mtext>{</mtext><msup><mrow><mtext mathvariant="italic">H</mtext></mrow><mrow><mtext mathvariant="italic">T</mtext></mrow></msup><mtext mathvariant="italic">H</mtext><mtext>}</mtext><mspace linebreak="newline" /><mtext mathvariant="italic">B</mtext><mtext> = </mtext><mtext mathvariant="italic">H</mtext><mspace linebreak="newline" /><mtext mathvariant="italic">S</mtext><mtext> = 0</mtext></mrow></math><img file="EP0757331B1_D0010.tif" /></maths> When the network operates based on these parameters and an output image is obtained, the value of the distortion function is minimized.

The operation of this embodiment will be described below with reference to Fig. 5.

A digital image signal uⁿ of the n-th frame input from the A/D converter 11 is converted into an image yⁿ by the operation of the neural network given by equations (11) below, and the converted image is output:<maths id="math0011" num=""><img file="EP0757331B1_D0011.tif" /></maths> where uⁿ_ij(t) and yⁿ_ij(t) are the values of the input image signal uⁿ and the output image signal yⁿ corresponding to the position (i, j) on the screen in the t-th operation of the neural network. Also, f is a nonlinear function determined by the number of gradation levels that can be displayed by the display device 17, and A_ijmn and B_ijmn are filter coefficients for a spatial filter operation applied to the yⁿ_ij and uⁿ_ij, which coefficients are determined in advance by equations (10) above. Note that the filter H is defined by a two-dimension Gaussian distribution which resembles the visual characteristics of man.

Fig. 6 shows an example of the nonlinear function f. The number of levels of an output with respect to an input is the same as the number of gradation levels that can be displayed by the display device 17, and the output corresponds to image data having the number of gradation levels that can be displayed by the display device. In Fig. 6, the number of output gradation levels is 2, and the display device 17 is a binary device which takes either an ON or OFF state.

The gradation conversion circuit 12 calculates output data yⁿ(t) using equations (11), and calculates a sum total of differences between repetitive portions of the calculated image signals in one frame. When the sum total becomes equal to or smaller than a predetermined value T_s, as indicated by inequality (12) below, the circuit 12 outputs the output image signal yⁿ(t) at that time as a gradation-converted image yⁿ to the binary frame memory 15.<maths id="math0012" num=""><img file="EP0757331B1_D0012.tif" /></maths> Between the image signal yⁿ output at that time and the input image signal uⁿ, the distortion function given by equation (9) above is minimized by the operation of the cellular neural network.

Subsequently, an image signal of the next (n+1)-th frame is input, and is converted into a digital image signal uⁿ⁺¹ by the A/D converter 11 in the same manner as in the previous frame. Thereafter, the converted signal is input to the comparison circuit 18. On the other hand, the image yⁿ of the previous frame stored in the frame memory is input to the LPF 16, and is converted as follows in accordance with equation (13) below:<maths id="math0013" num="(13)"><math display="block"><mrow><msup><mrow><mover accent="true"><mrow><mtext mathvariant="italic">û</mtext></mrow><mo>ˆ</mo></mover></mrow><mrow><mtext mathvariant="italic">n</mtext></mrow></msup><mtext> = </mtext><msup><mrow><mtext mathvariant="italic">Hu</mtext></mrow><mrow><mtext mathvariant="italic">n</mtext></mrow></msup></mrow></math><img file="EP0757331B1_D0013.tif" /></maths> uⁿ⁺¹ and ûⁿ are input to the comparison circuit 18 in units of lines, and a motion between two frames in the corresponding line is detected on the basis of these data.

Fig. 7 is a block diagram showing the arrangement of the comparison circuit 18.

uⁿ⁺¹ and ûⁿ input to the comparison circuit 18 in units of lines are input to an adder 801 in units of<maths id="math0014" num="(14)"><math display="block"><mrow><mtext>d = </mtext><mtext mathvariant="italic">û</mtext><msubsup><mrow><mtext></mtext></mrow><mrow><mtext mathvariant="italic">ij</mtext></mrow><mrow><mtext mathvariant="italic">n</mtext></mrow></msubsup><msubsup><mrow><mtext> - u</mtext></mrow><mrow><mtext mathvariant="italic">ij</mtext></mrow><mrow><mtext mathvariant="italic">n</mtext><mtext>+1</mtext></mrow></msubsup></mrow></math><img file="EP0757331B1_D0014.tif" /></maths> where û<maths id="math0015" num=""><math display="inline"><mrow><mfrac linethickness="0" numalign="left" denomalign="left"><mrow><mtext>n</mtext></mrow><mrow><mtext>ij</mtext></mrow></mfrac></mrow></math><img file="EP0757331B1_D0015.tif" /></maths> and u<maths id="math0016" num=""><math display="inline"><mrow><mfrac linethickness="0" numalign="left" denomalign="left"><mrow><mtext>n+1</mtext></mrow><mrow><mtext>ij </mtext></mrow></mfrac></mrow></math><img file="EP0757331B1_D0016.tif" /></maths> are the i-th image data in the j-th line.

The difference d is input to a comparator 803, and is compared with a predetermined threshold value Th1. When d is larger than Th1, the comparator 803 outputs "1"; otherwise, the comparator 803 outputs "0". The comparator 803 supplies the output value to a counter 804.

A pixel counter 802 counts the number of input pixels, and outputs a reset signal to the counter 804 when the count value has exceeded a pre-set value L. Upon reception of the reset signal, the counter 804 outputs the number K of "1" data input so far, and clears its internal counter to zero. A comparator 805 receives the number K of input data, and compares the input value with a predetermined threshold value Th2. When K has exceeded Th2, the comparator 805 outputs "1"; otherwise, the comparator 805 outputs "0".

On the other hand, the difference d output from the adder 801 is also input to an accumulator 806. The accumulator 806 accumulates the input values d in units of pixels, and outputs an accumulated value V to a comparator 807 upon reception of a reset signal from the pixel counter 802. The comparator 807 compares the input value V with a predetermined threshold value Th3. When V has exceeded Th3, the comparator 807 outputs "1"; otherwise, the comparator 807 outputs "0". Finally, in the comparison circuit 18, an OR gate 809 ORs the results outputs from the comparators 805 and 807, and outputs the OR as a rewriting flag for the currently effective line. A line counter 808 counts a line number on the basis of the output from the pixel counter 802, and outputs the count value as the currently effective line No. data.

Referring to Fig. 5, the frame memory control circuit 14 controls the binary frame memory 15 to output data of a line to be output to the display device 17 on the basis of the rewriting flag and the line No. data received from the comparison circuit 18. In this manner, since the LPF processing is performed upon comparison, and data are compared using a combination of a plurality of threshold values, stable detection is guaranteed even when noise is superimposed on an input image.