Apparatus and method for data packing through addition

A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.