Semiconductor device layout

p0001The invention relates to a semiconductor device having a semiconductor substrate and at least one formed on the semiconductor substrate transistor having first, second and third formed on a main surface of the semiconductor substrate and from each other electrically insulated electrode terminal areas, one of which the gate or base terminal, one of the associated source or emitter terminal, and a drain or the collector of at least one transistor, each electrode terminal portion is formed from at least one finger portion and an electrically conductive connected to the belonging finger portion contact flat portion. In particular, the at least one finger portion a compared to the extension in the width considerably greater longitudinal extension, the surface of the contact face portion with respect to the surface of each finger portion of the electrode terminal region is considerably increased, and the finger portions of the electrode terminal portions are arranged at least approximately parallel to each other aligned on the semiconductor substrate.

p0002In previously known GaAs field-effect transistors with multi-finger assembly, in particular those for high frequency applications, is usually on one side of the actual active FET region, a series of drain bonding pads, and on the other side alternately a number of gate bonding pads and a number of source Vias (metallized hole through the semi-insulating substrate for through to the rear) provided. Such an arrangement is for example in the data sheets NE 9004 (NEC), JS8855-AS (Toshiba), CFX 91 (Philips), FLR056 XV (Fujitsu) described and illustrated by the shown in FIG. 1 schematic plan view in another. The purpose of such arrangement is a low-inductance as possible connection to the outer circuit, in particular with regard to the gegenkoppelnde source inductance, which would otherwise affect the high frequency performance negatively. For effective heat dissipation the previous chips were thinly formed mainly. In the schematic plan view shown in Fig. 1 is a conventional semiconductor device having a semiconductor substrate 1 made of GaAs and a number of formed on the semiconductor substrate, transistors having a the gate or base terminal of the associated electrode terminal region 2, one of the source or emitter terminal of the associated electrode terminal region 3 , and the drain bzw.Kollektoranschluß associated electrode terminal section 4 provided. Each connection region 2, 3 and 4 is made parallel to each other and in the direction of a finger portions 5 adjacent extending finger portions 6, 7 and 8, and the contact surface sections 9, 11 and Via-contact surfaces 10 with respect to the finger portions 7, 6 and 8 enlarged Flat , In the known arrangement, the contact flat portions 9 and 10 are arranged for the gate terminals and the source terminals alternately in a row on one side opposite to the finger portions 5, while the contact surface portions 4 of the drain terminals on the opposite side of the finger portions 5 are aligned. The source contact surfaces can be other than as a source vias formed as a normal contact surfaces on the surface of the semiconductor substrate.

p0003The invention has for its object to provide a semiconductor device of the generic type is available, which in a most slightly elevated flat demand an enlarged electrical conductivity and current-carrying capacity in particular the finger portions and at the same time a reduction in the effective thermal resistance, as well as a significant reduction in the parasitic source - enables or emitter inductance.

p0004This object is achieved by a semiconductor device according to claim first

p0005The inventive semiconductor device is characterized in that at least one electrode terminal region whose contact area section is on one side with respect to the finger sections arranged a further electrically connected to the belonging finger portion contact surface portion which is disposed on the opposite side with respect to the finger sections. The further contact surface portions advantageously have an opposite each finger portion enlarged area.

p0006The inventive arrangement provides the advantage, especially when a sufficiently small distance between the contact surface portions to the active region of the transistor and sufficiently thick metallization of the electrode terminal portions, in particular to facilitate the vias, a significant reduction in the effective heat resistance, so that due to the electrical power dissipation, especially resulting in the active region of the transistor can be dissipated better. It should be noted that metals in general, a far more than an order of magnitude better thermal conductivity than the usual have semiconductor materials of Si or GaAs, so that even thin metal layers may allow a substantial reduction of the thermal resistance.

p0007Following the principle of the invention is provided in a further embodiment that at least one electrode terminal region whose contact area section is arranged on one side with respect to the finger sections, comprising an electrically connected to this contact area section and / or the belonging further contact area section further finger section. The other finger portion can in a lead electrically connected thereto widening portion on the opposite side with respect to the finger sections arranged and has a relation to the other finger portion at least somewhat larger width. It may be provided in an advantageous manner that the other finger portion of the finger portions of the associated electrode terminal portion is electrically connected with respect to a ridge with the finger portion and / or the further contact area section on the opposite side. Can also be provided in detail, that the finger portion of the opposite side and to the jetty next horizontally arranged contact surface portion of an adjacent electrode terminal portion is formed to bridge electrically insulating cross over to form an intersection.

p0008In a preferred arrangement according to the invention may further be provided that the the gate or base terminal of the transistor associated electrode terminal region has a plurality of finger sections connected electrically conductively associated with the associated contact area section of the gate or base terminal of the transistor electrode terminal region, and parallel between the finger portions of the source or emitter terminal and the drain or collector terminal of Transisters associated electrode lands.

p0009In a further embodiment of the semiconductor device according to the invention it can be provided that the plurality of finger portions of the gate or base terminal of the transistor associated electrode terminal region are connected via a lead to the associated contact area section of the gate or base terminal. It is advantageous when the finger portion of the on the one side with respect to the finger sections arranged contact surface portion of a range, the electrode terminal to the gate or base terminal of the transistor associated feed line is electrically insulating is formed to cross over to form a crossing location.

p0010The crossover points can in this case be designed as a metal-insulator-layer metal junction (MIM junction) or as airlift.

p0011In continuation of the invention may be provided, that the one contact surface portions of the source or emitter terminal of the transistors associated electrode terminal portions and the contact surface portion of the gate or base terminal of the transistors associated electrode terminal portions aligned alternately and in a row on one side with respect to the finger sections are, and the further contact flat portions of the source or emitter terminal of the transistors associated electrode terminal portions and the contact surface portions of the drain or collector terminal of the transistors associated electrode terminal portions on the opposite side of the finger portions with respect to alternately and aligned in a row.

p0012In a particularly preferred embodiment of the semiconductor device according to the invention it can be provided that the connection to that finger sections which are assigned to the source or emitter terminal region of the transistor, with the formation of an insulating crossover point on the gate or base terminal of the transistor belonging lead is performed, and (which is assigned to the drain or collector terminal of the transistor) simultaneously on the opposite side with respect to the finger sections with the formation of likewise insulating crossover points as webs underneath the third electrode terminal region belonging injections is performed.

p0013The connection or junction assembly of the semiconductor device according to the invention allows a much more effective heat dissipation, which would otherwise require the use of maximum metallization thicknesses for the allocations. be with the principle of the invention for connecting the internal FET cells (the actual active FET region form) to the external environment, in this case the contact surface portions, advantageously used two types of line crossings: On the gate or base terminal side (ie on the one side with respect to the finger sections) crosses a connection metal level as the source and emitter terminal of the gate or base delivery on the drain or collector terminal side (ie on the opposite side with respect to the finger sections) crosses, for example, the same connection metal layer, this time as the drain - or collector terminal, the source or emitter feed, which here in the intersection area, for example, merely could consist ohm metal. In addition, the lower intersection metals with an additional connection metal layer may be reinforced, if considered appropriate, for resistance or electromigration reasons.

p0014In a further, particularly preferred embodiment of the invention it can be provided that the contact area sections and / or the further contact area sections of the source or emitter terminal of the at least one transistor associated electrode terminal region have a Substratdurchkontaktierung. In this way can be particularly minimized by high-impedance substrates advantageously the inductance to the back at the via. The ground inductance can be further minimized in a formation of two Substratdurchkontaktierungs rows (Via-hole rows) on both sides with respect to the finger sections in particular, the area required is only slightly high than in the conventional arrangement with only one Via-Hole- number on only one side with respect to the finger sections. If these plated-through holes disposed sufficiently close to the active region (distance in the order of magnitude of the substrate thickness or less), so the thermal resistance to the heat sink (back side of the semiconductor substrate) is significantly reduced, in particular at a relative to the finger portions and the center line of two-sided arrangement of the source - or emitter terminal of the transistor associated contact surface sections according to the invention.

p0015Both effects in this embodiment of the semiconductor device according to the invention, therefore, the minimization of the inductance to the rear in the plated-through hole and the reduction of the heat resistance together can be obtained, but are also independently used, for example, the better heat dissipation particularly in the foreground in power applications, and the minimized source inductance for example in low-noise components plays a larger role.

p0016The terminal design of the invention to the outer contact surface portions or pads thus allows, in particular in the internal FET cells both the source and emitter than to impose on the drain or collector full of and the connection metal layers, so that the electrical conductivity and the current-carrying capacity are increased at all fingers, and ultimately electromigration problems are at least reduced.

p0017The inventive semiconductor device is applied to FETs, bipolar transistors, and similar components, in particular for high frequency applications, as well as monolithic integrated circuits containing such devices. Conceptually the the source or emitter portion associated components can be interchanged with the drain or collector portion or the gate or base terminal assigned components, so that, for example, the outer contact surface portions or pads in the corresponding pad rows also from gate sections or drain sections in place may consist of source portions. Instead of source vias also source pads can be used, in this case of course eliminates the aspect of the thermal resistance at Via. Nevertheless arise even here thermal advantages due to the larger surface metallized and thus better heat distribution on the surface of the semiconductor substrate.

p0018The advantages of the invention apply to both a basic chip (only one drain and gate pad or terminal), for frequent finger structures ( "arbitrarily" many gate and drain pads) as well as MMICs with respective FET cells and other comparable other semiconductor devices.

p0019Further features, advantages and expediencies of the invention will be apparent from the description of an embodiment with reference to the drawing. It shows:<ul><li>Figure 1 is a schematic plan view of a conventional GaAs field effect transistor with multi-finger assembly, and</li><li>Figure 2 is a schematic plan view of a semiconductor device according to the invention with two-sided plated-through contacts and special topology.</li></ul>

p0020In the embodiment, a semiconductor device according to the invention 13 shown in Figure 2, a GaAs field effect transistor is formed with multi-finger assembly 14 on a GaAs semiconductor substrate 15th The transistor has a first electrode terminal region 16, which is assigned to the gate G of the transistor, a second electrode terminal area 17, which is assigned to the source terminal S of the transistor, and a third electrode terminal region 18 that is associated with the drain terminal D of the transistor, which electrode terminal portions 16, having 17, 18, the connection topology shown in Fig. 2. The topology shown in FIG. 2 is concerning. The outer terminals 16, 17, 18 shown to scale approximately with 1 cm in the figure correspond to about 50 microns in reality, which represented topology with all geometric details and other illustrations features full content of the disclosure the present application are expected. Each electrode terminal area 16, 17, 18 is comprised of finger portions 19, 20, 21 having a relation to the extension in the width considerably greater longitudinal extension and is electrically conductively connected with the belonging finger portion 19, 20, 21, contact surface portion 22, 23, 24, the area of ​​each opposite the face of each of the finger portions 19, 20, 21 is considerably increased. The finger portions 19, 20, 21 of all the electrode terminal portions 16, 17, 18 are aligned parallel to one another and 25 (which serves with respect to the finger sections to denote the arrangement on the thereof left and right sides and, moreover, is not necessarily a line of symmetry) in the direction of a center line adjacently disposed on the semiconductor substrate 15th These are not shown to scale. In particular, significantly more individual fingers 19, 20, 21 each of the external terminal portions 16, 17, be associated with the 18th The source terminals associated electrode terminal portion 17 has in addition to the respect on one side of the center line 25 arranged contact surface portion 23 a further contact surface portion 26 which is arranged on the opposite side relative to the center line 25, in the representation of FIG. 2 on the right side and the also has shown how an individual against the finger portion 20 enlarged area. Furthermore it has the source terminals associated electrode terminal region 17 a further finger section 27 which, starting a contact face portion 23 extends from the through a bend 28 in parallel to the other finger portions 19, 20, 21 and opens into an associated portion 29 opposite to the side with respect to the center line 25 is arranged. The section 29 is connected via a web 30 with the finger portion 20th The the gate of the transistor associated electrode terminal section 16 has a parallel to the center line 25 running and in the representation of FIG. 2 arranged on the left side feed line 32, which causes the electrical connection between the finger portions 19 with the contact surface portion 22. As shown, the further finger portions 27 of the source terminal of the associated electrode terminal region 17 are passed over a bridge 33 via the feed line 32 which bridge 33 is a finger portion 27 opposite to the lead 32 electrically insulating intersection forms, as metal-insulator-layer metal crossover or as an air bridge may be formed. Analogously, the finger portions 21, the starting 18 extending from after the representation of FIG. 2 is arranged on the right side contact surface portions 24 of the electrode terminal area to the left, out by means of a bridge 34 on the web 30 of the electrode terminal portion 17 which bridge 34 a crossover location for the electrical insulation of the finger portion 21 of the web 30 forms and can in turn be formed as a metal-insulator-metal junction layer, or as an air bridge. The two contact surface sections 27 of the electrode terminal region 17 are, as is evident from Fig. 2, a connecting portion 35 electrically connected together and disposed on the FIG. 2 right hand side and 18 arranged between the contact face portions 24 of the electrode terminal region further contact surface portion 26a of the electrode terminal region 17 connected , The intermediate contact surface portion 24a of the electrode terminal region 18 may be connected over a bridge 36, which leads through the connecting portion 35 with the finger portion 21 in turn. In the manufacture of the semiconductor device of the gate terminal G associated electrode terminal region 16 may be contiguous manufactured in a process step of forming a first metallization level, and the source S and drain D of the associated electrode terminal portions 17 and 18 can in one step in a process step of forming a second metallization are produced. In specific methods, the layers can be achieved by the same metallisation.

p0021In the illustrated embodiment of FIG. 2, the contact surface portions 22 and 24 of the electrode terminal portions formed 16 and 18 as a so-called bonding pads, while the source terminal S associated contact surface sections 23 and / or the further contact area sections 26 as so-called Via-hole contacts, ie a metallized hole formed by the semi-insulating substrate for through-contacting to the backside of the substrate, as shown by the shaded areas 37 in FIG. 2. The advantage of two-sided Via series is, in particular, to achieve a substantial reduction in the inductance to the back of the substrate with only minimal increased space requirements down, and at a sufficiently small distance between the vias 37 to the active region and sufficiently thick metallization in Via 37 an effective reduction to achieve the thermal resistance, so that the resulting mainly in the active region due to the electrical dissipation of heat can be better dissipated.