EP0741299A2

Circuit for determining differences in capacity

Abstract

The two capacitors (1, 2) are alternately connected to an integrator with differential amplifier (3), the input current of which is positive (+ I) if the first capacitor (1) is integrated, or negative (-I) if the second capacitor ( 2) is integrated, the switches (5, 6, 7) being switched synchronously. The differential amplifier keeps the voltage on both capacitors the same. A clocked control device (4) takes care of the synchronous switching and measures and adds the respective charging and discharging times separately and measures and, if necessary, adds the output voltage of the integrator and controls the last charging cycle so that the voltage across the capacitors is then equal to the initial voltage. The relative or absolute capacity difference is calculated from the determined sums and can be output digitally.

EP0741299A2, drawing sheet 1 — Sheet 1 of 38

Term

Term ended

Projected expiry passed 14 March 2016, 10.5 years ago.

10 claims: 1 independent, 9 dependent

1
Schaltungsanordnung zum Ermitteln der Differenz zwischen der Kapazität eines ersten Kondensators (1) und der Kapazität eines zweiten Kondensators (2), bei der ein Differenzverstärker (3) mit einem invertierenden und einem nicht-invertierenden Eingang und mit einem Ausgang, eine positive Stromquelle (+I), die einen Strom mit konstanter Stromstärke und einer ersten Flußrichtung liefert, eine negative Stromquelle (-I), die einen Strom mit konstanter Stromstärke und der entgegengesetzten Flußrichtung liefert, ein Masseanschluß, eine Steuereinrichtung (4), eine erste Schaltvorrichtung (5) und eine zweite Schaltvorrichtung (6, 7) vorhanden sind, bei der diese erste Schaltvorrichtung (5) zwei Schaltpositionen (P 1 , P 2 ) aufweist, in denen jeweils diese positive Stromquelle (+I) oder diese negative Stromquelle (-I) mit dem invertierenden Eingang dieses Differenzverstärkers (3) verbunden ist, bei der der nicht-invertierende Eingang dieses Differenzverstärkers (3) mit diesem Masseanschluß verbunden ist, bei der diese zweite Schaltvorrichtung (6, 7) so eingerichtet ist, daß damit zwei verschiedene Schaltpositionen, in denen jeweils ein Anschluß eines dieser Kondensatoren (1, 2) mit einem der Eingänge des Differenzverstärkers (3) und ein Anschluß des anderen dieser Kondensatoren (1, 2) mit dem jeweils anderen Eingang dieses Differenzverstärkers verbunden ist, eingestellt werden können, bei der die anderen Anschlüsse dieser Kondensatoren mit dem Ausgang dieses Differenzverstärkers und einem Eingang dieser Steuereinrichtung (4) verbunden sind und bei der für diese Steuereinrichtung Mittel vorgesehen sind, mit denen diese erste und diese zweite Schaltvorrichtung (5;6, 7) synchron umgeschaltet werden können, mit denen die Zeit zwischen zwei solchen Umschaltvorgängen und die an den Kondensatoren anliegende Spannung gemessen werden können, mit denen Zeiten addiert werden können und mit denen die für die Bestimmung der Kapazitätsdifferenz erforderlichen Werte ermittelt werden können.
2
Schaltungsanordnung nach Anspruch 1, bei der die erste Schaltvorrichtung (5) ein erster Schalter (5) ist und die zweite Schaltvorrichtung (6, 7) ein zweiter Schalter (6) und ein dritter Schalter (7) ist, bei der diese Schalter (5, 6, 7) jeweils alternativ in eine erste Schaltposition (P 1 ) und in eine zweite Schaltposition (P 2 ) gebracht werden können, in denen ein fester Anschluß des betreffenden Schalters jeweils mit einem von zwei alternierenden Anschlüssen verbunden ist, bei der der feste Anschluß des ersten Schalters (5) mit dem invertierenden Eingang des Differenzverstärkers (3) und einer der alternierenden Anschlüsse des ersten Schalters (5) mit der positiven Stromquelle (+I) und der andere der alternierenden Anschlüsse des ersten Schalters (5) mit der negativen Stromquelle (-I) verbunden ist, bei der entweder a) der feste Anschluß des zweiten Schalters (6) mit einem Anschluß eines der Kondensatoren (1, 2) und der feste Anschluß des dritten Schalters (7) mit einem Anschluß des anderen Kondensators verbunden ist und jeweils einer der alternierenden Anschlüsse des zweiten und des dritten Schalters (6, 7) mit dem einen Eingang des Differenzverstärkers und der jeweils andere der alternierenden Anschlüsse mit dem jeweils anderen Eingang des Differenzverstärkers verbunden ist oder b) der feste Anschluß des zweiten Schalters (6) mit einem Eingang des Differenzverstärkers und der feste Anschluß des dritten Schalters (7) mit dem anderen Eingang des Differenzverstärkers verbunden ist und jeweils einer der alternierenden Anschlüsse des zweiten und des dritten Schalters mit einem Anschluß eines der Kondensatoren (1, 2) und der jeweils andere der alternierenden Anschlüsse mit einem Anschluß des anderen Kondensators verbunden ist und bei der für die Steuereinrichtung (4) Mittel vorgesehen sind, mit denen diese Schalter (5, 6, 7) wie für diese zweite Schaltvorrichtung vorgesehen synchron umgeschaltet werden können.
3
Schaltungsanordnung nach Anspruch 2, bei der die Schalter (5, 6, 7) einzeln umgeschaltet werden können.
4
Schaltungsanordnung nach einem der Ansprüche 1 bis 3, bei der die positive und die negative Stromquelle (+I, -I) Ströme mit einer dem Betrag nach gleichen Stromstärke liefern.
5
Schaltungsanordnung nach einem der Ansprüche 1 bis 4, bei der die erste Schaltvorrichtung (5) unabhängig von der zweiten Schaltvorrichtung (6, 7) umgeschaltet werden kann.
6
Schaltungsanordnung nach einem der Ansprüche 1 bis 5, bei der die zweite Schaltvorrichtung (6, 7) eine Schaltposition ermöglicht, in der die mit einem Eingang des Differenzverstärkers verbundenen Anschlüsse der Kondensatoren beide mit dem Masseanschluß verbunden sind, bei der die zweite Schaltvorrichtung zwischen dieser Schaltposition und jeder der beiden Schaltpositionen, in denen die mit einem Eingang des Differenzverstärkers verbundenen Anschlüsse der Kondensatoren mit verschiedenen Eingängen des Differenzverstärkers verbunden sind, synchron mit der ersten Schaltvorrichtung (5) umgeschaltet werden kann und bei der die Steuereinrichtung (4) Mittel aufweist, mit denen zumindest für eine dieser Schaltpositionen jeweils erfolgende Änderungen der an den Kondensatoren anliegenden Spannung addiert werden können und diese Summe gespeichert werden kann.
7
Schaltungsanordnung nach Anspruch 6, bei der die Steuereinrichtung (4) Mittel aufweist, mit denen zwischen Schaltpositionen umgeschaltet werden kann, sobald der Betrag der Summe der jeweils in einer bestimmten Konstellation der Schaltpositionen der Schaltvorrichtungen (5;6, 7) erfolgenden Änderungen der an den Kondensatoren anliegenden Spannung den Betrag eines von der Steuereinrichtung gespeicherten Wertes erreicht.
8
Verfahren zum Ermitteln des Quotienten aus den Kapazitäten zweier Kondensatoren (1, 2) oder des Quotienten aus der Differenz und der Summe der Kapazitäten zweier Kondensatoren (1, 2) unter Verwendung einer Schaltungsanordnung nach einem der Ansprüche 1 bis 7, bei dem a) der Quotient aus den Stromstärken des von der positiven Stromquelle (+I) gelieferten Stromes und des von der negativen Stromquelle (-I) gelieferten Stromes fest eingestellt wird, die erste Schaltvorrichtung (5) in eine erste Schaltposition (P 1 ) gebracht wird und die zweite Schaltvorrichtung (6, 7) so eingestellt wird, daß der eine Kondensator mit dem einen Eingang des Differenzverstärkers und der andere Kondensator mit dem anderen Eingang des Differenzverstärkers verbunden ist, b) der mit der ersten Schaltvorrichtung verbundene Kondensator während einer vorgegebenen oder von der Steuereinrichtung (4) aus bisherigen Verfahrensschritten ermittelten Zeit geladen oder entladen wird, während der Differenzverstärker den anderen Kondensator auf dieselbe Spannung lädt, c) die erste und die zweite Schaltvorrichtung synchron umgeschaltet werden, so daß die mit einem Eingang des Differenzverstärkers verbundenen Anschlüsse der Kondensatoren mit dem jeweils anderen Eingang des Differenzverstärkers verbunden werden, d) der Schritt b) ausgeführt wird, e) die Schritte c) und d) mehrmals hintereinander ausgeführt werden, wobei für jede der beiden Schaltpositionen, zwischen denen in Schritt c) umgeschaltet wird, gesondert die Zeiten, während derer Schritt b) oder d) ausgeführt worden ist, addiert werden und der Schritt d) so oft und jeweils so lange ausgeführt wird, daß die an den Kondensatoren anliegende Spannung anschließend mit der zu Anfang an den Kondensatoren anliegenden Spannung zumindest soweit übereinstimmt, wie für die vorgegebene Meßgenauigkeit erforderlich ist, und f) der Quotient der Kapazitäten oder der Quotient aus der Differenz und der Summe der Kapazitäten der Kondensatoren aus dem bekannten oder separat ermittelten Quotienten der Stromstärken und den Summen der für die Schaltpositionen gesondert addierten Zeiten ermittelt wird.
9
Verfahren zum Ermitteln der Differenz der Kapazitäten zweier Kondensatoren (1, 2) oder des Quotienten aus der Differenz und der Summe der Kapazitäten zweier Kondensatoren (1, 2) unter Verwendung einer Schaltungsanordnung nach Anspruch 6 oder 7, bei dem a) der Quotient aus den Stromstärken des von der positiven Stromquelle (+I) gelieferten Stromes und des von der negativen Stromquelle (-I) gelieferten Stromes fest eingestellt wird, die erste Schaltvorrichtung (5) in eine erste Schaltposition (P 1 ) gebracht wird und die zweite Schaltvorrichtung (6, 7) in eine von zwei speziellen Schaltpositionen A oder B eingestellt wird, in denen entweder A) der eine Kondensator mit dem einen Eingang des Differenzverstärkers und der andere Kondensator mit dem anderen Eingang des Differenzverstärkers verbunden ist oder B) die mit einem Eingang des Differenzverstärkers verbundenen Anschlüsse der Kondensatoren beide mit dem Masseanschluß verbunden sind, b) ein zwischen dem invertierenden Eingang des Differenzverstärkers und dem Ausgang des Differenzverstärkers parallel zu dem Differenzverstärker vorhandener weiterer Kondensator (8) (Schaltungskomponente bestimmter Kapazität oder unbekannte parasitäre Kapazität) während einer vorgegebenen oder von der Steuereinrichtung aus bisherigen Verfahrensschritten ermittelten Zeit geladen oder entladen wird, während der Differenzverstärker den oder die anderen Kondensator(en) auf dieselbe Spannung lädt, c) die erste und die zweite Schaltvorrichtung synchron umgeschaltet werden, so daß die Kondensatoren aus der eingestellten speziellen Schaltposition in die andere spezielle Schaltposition gelangen, d) der Schritt b) ausgeführt wird, e) die Schritte c) und d) mehrmals hintereinander ausgeführt werden, wobei für jede der beiden speziellen Schaltpositionen gesondert die Zeiten, während derer Schritt b) oder d) ausgeführt worden ist, addiert werden und zumindest für eine dieser speziellen Schaltpositionen gesondert die während dieser Zeiten jeweils erfolgenden Änderungen der an den Kondensatoren anliegenden Spannung addiert werden und der Schritt d) so oft und jeweils so lange ausgeführt wird, daß die an den Kondensatoren anliegende Spannung anschließend mit der zu Anfang an den Kondensatoren anliegenden Spannung zumindest soweit übereinstimmt, wie für die vorgegebene Meßgenauigkeit erforderlich ist, und die Summe der in dieser speziellen Schaltposition erfolgten Änderungen der an den Kondensatoren anliegenden Spannung von der Steuereinrichtung gespeichert wird, f) die zweite Schaltvorrichtung (6, 7) in eine der zwei speziellen Schaltpositionen B oder C eingestellt wird, wobei in Schaltposition C der eine Kondensator mit dem einen Eingang des Differenzverstärkers und der andere Kondensator mit dem anderen Eingang des Differenzverstärkers verbunden ist und dabei die Anschlüsse gegenüber der speziellen Schaltposition A vertauscht sind, g) der Schritt b) ausgeführt wird, h) der Schritt c) ausgeführt wird, wobei zwischen den speziellen Schaltpositionen B und C umgeschaltet wird, i) der Schritt b) ausgeführt wird, j) die Schritte h) und i) mehrmals hintereinander ausgeführt werden und für diese beiden speziellen Schaltpositionen gesondert die Zeiten, während derer Schritt g) oder i) ausgeführt worden ist, addiert werden und zumindest für eine dieser speziellen Schaltpositionen gesondert die während dieser Zeiten jeweils erfolgenden Änderungen der an den Kondensatoren anliegenden Spannung addiert werden und entweder die Summe der in dieser speziellen Schaltposition erfolgten Änderungen der an den Kondensatoren anliegenden Spannung ebenfalls von der Steuereinrichtung gespeichert wird oder der Schritt i) in dieser speziellen Schaltposition so oft und jeweils so lange ausgeführt wird, daß der Betrag dieser Summe den Betrag des von der Steuereinrichtung in Schritt e) gespeicherten Wertes erreicht, und der Schritt i) insgesamt so oft und jeweils so lange ausgeführt wird, daß die an den Kondensatoren anliegende Spannung anschließend mit der zu Anfang an den Kondensatoren anliegenden Spannung zumindest soweit übereinstimmt, wie für die vorgegebene Meßgenauigkeit erforderlich ist, und k) aus dem bekannten oder separat ermittelten Quotienten der Stromstärken, den Summen der für die Schaltpositionen gesondert addierten Zeiten und dem Quotienten der in den Schritten e) und j) jeweils erfaßten Summen der Änderungen der Spannung der Quotient aus der Differenz und der Summe der Kapazitäten der Kondensatoren ermittelt wird oder aus diesen Werten und dem bekannten oder separat bestimmten Wert der Kapazität des weiteren Kondensators (8) die Differenz der Kapazitäten der Kondensatoren ermittelt wird.
10
Verfahren nach Anspruch 8 oder 9, unter Verwendung einer Schaltungsanordnung nach Anspruch 5 oder nach einem der Ansprüche 6 oder 7, rückbezogen auf Anspruch 5, bei dem der Quotient aus den Stromstärken des von der positiven Stromquelle gelieferten Stromes und des von der negativen Stromquelle gelieferten Stromes ermittelt wird, indem a) die erste Schaltvorrichtung in eine erste Schaltposition gebracht wird und die zweite Schaltvorrichtung so eingestellt wird, daß mindestens ein Kondensator mit der ersten Schaltvorrichtung verbunden ist, b) dieser Kondensator während einer vorgegebenen oder von der Steuereinrichtung aus bisherigen Verfahrensschritten ermittelten Zeit geladen oder entladen wird, c) nur die erste Schaltvorrichtung umgeschaltet wird, d) der Schritt b) ausgeführt wird, e) die Schritte c) und d) mehrmals hintereinander ausgeführt werden, wobei für jede der beiden Schaltpositionen der ersten Schaltvorrichtung gesondert die Zeiten, während derer Schritt b) oder d) ausgeführt worden ist, addiert werden und der Schritt d) so oft und jeweils so lange ausgeführt wird, daß die an dem Kondensator anliegende Spannung anschließend mit der zu Anfang an dem Kondensator anliegenden Spannung zumindest soweit übereinstimmt, wie für die vorgegebene Meßgenauigkeit erforderlich ist, und f) der Quotient aus den Stromstärken des von der positiven Stromquelle gelieferten Stromes und des von der negativen Stromquelle gelieferten Stromes als Quotient aus der Summe der für die Schaltposition, in der der Kondensator mit der negativen Stromquelle verbunden ist, gesondert addierten Zeiten und der Summe der für die Schaltposition, in der der Kondensator mit der positiven Stromquelle verbunden ist, gesondert addierten Zeiten ermittelt wird.

Independent claims10

34 paragraphs, as filed

0001The invention relates to a device and a method for digitally measuring the capacitance difference between two capacitors.

0002Such a device or circuit arrangement can be used, for example, for the digital evaluation of differential capacitors. Differential capacitors are often used in sensor technology to measure pressure, acceleration, humidity, inclination, etc. Various devices for measuring capacitance differences have already been proposed (see, for example, DE 36 23 136, US 43 92 378, DE 41 03 433, EP 0 503 272). In the known methods, the measured variable (capacity difference) is represented either by the value of a voltage (or a current) or by the pulse duty factor of a PWM signal. In any case, an additional A / D conversion must take place for digital processing.

0003The invention is based on the object of specifying a device which makes it possible to measure the capacitance difference between two capacitors and to output them digitally, without, however, additionally requiring an A / D converter for the measuring circuit. The device should be designed in such a way that it can be implemented with commercially available components in the simplest possible manner and, if necessary, integration can also take place without problems. In a further embodiment, the device should make it possible to eliminate existing parasitic capacitances from the determination of the measurement result.

0004This object is achieved with the circuit arrangement having the features of claim 1 and with the method for measuring capacitance differences using this circuit arrangement according to claim 8 or 9. Further configurations result from the dependent claims.

0005In the circuit arrangement according to the invention, a positive current is integrated with one capacitor and a negative current is integrated with the other capacitor, the voltage of the capacitor not used for the integration being tracked to the voltage of the capacitor used for the integration and a sequence control controlling the time periods of the individual integrations measures, calculates a value from it and outputs it digitally and controls the integration cycles in such a way that the voltage on the capacitors remains within a predetermined range.

0006There follows a more detailed description of this circuit arrangement and of the measuring method with reference to FIGS. 1 and 2, which each show basic circuit diagrams of this circuit arrangement.

0007In the circuit arrangement shown in Figure 1, the two capacitors 1, 2 are shown, for the z. B. the quotient of the capacities or the difference in capacities related to the sum of the capacities (relative capacity difference) is to be determined. An integrator can be alternately connected to these capacitors 1, 2, which is fed from a current source with a positive output current (positive current source + I) alternately with a current source with a negative output current (negative current source -I). A first circuit device 5, which in this exemplary embodiment is formed by a first switch 5, makes it possible, as an alternative, to switch on one or the other current source. The current sources each deliver a current with constant current intensity, which is led to the inverting input of a differential amplifier 3. The non-inverting input of this differential amplifier 3 is connected to a ground connection. One connection each of the two capacitors 1, 2 to be measured is connected to the output of this differential amplifier 3. There is a second circuit device which is formed in the exemplary embodiment shown in FIG. 1 by a second switch 6 and a third switch 7. This second circuit device 6, 7 is set up in such a way that it enables a connection of the capacitors 1, 2 either to the ground connection (reference potential at the non-inverting input of the differential amplifier 3) or to the inverting input of the differential amplifier 3 (virtual ground) connect. This circuit arrangement ensures that the voltages on the two capacitors match at all times.

0008The synchronous switching of the three switches 5, 6, 7 is effected by a sequence control which comprises a control device 4 arranged behind the output of the differential amplifier 3. This control device 4 also has a voltmeter that measures the voltage across the capacitors. The control device 4 also has a timer and means for adding determined time periods. The control device 4 is preferably connected to a clock generator. The times can then be added digitally and processed in this form for the further calculation and the output of the result. In a preferred embodiment of the circuit arrangement according to the invention, this control device 4 immediately delivers the arithmetically determined result for the value of the capacitance difference. For further developments of this circuit arrangement, it is advantageous if the first switch 5 can be actuated independently of the other switches or if the first switch 5 can only be switched synchronously with one of the other two switches. Instead of a synchronous control of separate switches, a z. B. multiple switches realized by an electronic circuit are provided, which are constructed in such a way that, when switching over, they simultaneously change all the connections to be switched over accordingly. Even with such a realization of the two circuit devices, the first circuit device integrated in the common switch can be distinguished from the second circuit device. The separate designation of these circuit devices and the description of the specific embodiment according to FIG. 1 therefore do not constitute any restriction to the possible further embodiments of this circuit arrangement. The arrangement shown in FIG. 1 is advantageous because of the particularly simple design.

0009To explain the functioning of this arrangement, the measuring method is first described below. At the start of a measurement, the capacitors are preferably completely or at least largely discharged. The first switching device (first switch 5) is in a first switching position P1 switched, in the example given in Figure 1, the positive current source + I is connected to the inverting input of the differential amplifier 3. In the starting position shown in FIG. 1, the first capacitor 1 is connected to the inverting input of the differential amplifier by means of the second switching device, while the second capacitor 2 is connected to the ground connection. The current supplied by the positive current source + I is therefore first integrated by charging the first capacitor to a specific voltage. The circuit arrangement causes the second capacitor 2 to be charged to the same voltage because of the differential amplifier. The charging of the first capacitor 1 takes place, for. B. for a predetermined period of time. This period is monitored by the control device in which, for. B. this time is fixed or determined by a connected clock. Instead, it can be checked via the voltmeter that the voltage across the capacitors only rises to a certain value, and then the integration of the current is interrupted. After this specific integration time has elapsed, the first and second switching devices 5, 6, 7 are switched synchronously by the control device 4, so that now the current from the other current source (in this example, the negative current source -I) is integrated with the opposite direction of flow and the capacitor previously connected to the ground connection is connected to the inverting input of the differential amplifier and the other capacitor is connected to the ground connection. This second integration, in which the current flows in the opposite direction, is carried out for as long as the time period or the clock rate specified in the control device 4 corresponds or until the voltage applied to the capacitors falls below a certain value. This value can e.g. B. the reference potential given by the ground connection. Then all switches are brought into the starting position at the same time, so that a further integration cycle can take place, in which the first capacitor is again charged with the positive current and then the second capacitor is discharged with the negative current, the differential amplifier in each case applying the voltage to the aligns another capacitor. The control device 4 can, for. B. set the integration times so that the output voltage is again applied to the capacitors after each integration cycle. The voltage across the capacitors can also change after each integration cycle, however, for the evaluation of the measurement results, at least the last integration period is preferably selected so that the voltage originally applied to the capacitors is finally reached again. The sums of the voltage changes during charging or discharging of the capacitors then drop out of the equations used for determining the result value.

0010The evaluation of the measurement uses the equation valid for capacitors <maths id="math0001" num=""><math display="inline"><mrow><mtext>CU = Q</mtext></mrow></math><img file="EP0741299A2_D0001.tif" /></maths>, where the charge Q is equal to the product of current strength and time because of the constant current. This equation is applied n times for n integration cycles. The resulting calculation leads to the following equations. Where:<ul id="ul0001" list-style="none" compact="compact"><li>I.+, I- the amount of the current strength of the current from the positive or negative current source,</li><li>C.+, C- the capacitance of the capacitor connected to the positive or negative current source,</li><li>C.1, C2 the capacitance of the first or second capacitor,</li><li>C.0 the capacitance of another capacitor,</li><li>t+"t"+, t ''+ Times during which the positive current source + I is charging,</li><li>t-"t"-, t ''- Times during which the negative current source -I is discharged</li><li>U+'U'+, U ''+, U-'U'-, U ''- Voltage differences that are caused at the capacitors when charging or discharging.</li></ul>

0011In the following equations, the small letter as the lower index of the sum sign means the running index with which the quantities belonging to an integration cycle are numbered. The plus sign as an index identifies a time interval and a voltage change therein during connection to the positive current source + I, ie in the exemplary embodiment in FIG. 1, the first switch 5 is in the P position1. The minus sign accordingly means the time intervals or voltage changes during the connection to the negative current source -I, ie specifically the first switch 5 in the second switching position P.2. The calculation is based on the following equations:<maths id="math0002" num=""><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub></mrow></mtd></mtr><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0741299A2_D0002.tif" /></maths> If the charging times and voltage changes are summed up separately during the measurement, the difference or the quotient of the capacitances can already be determined from these equations when the current strengths are known. If you set up the measurement so that<maths id="math0003" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0003.tif" /></maths>, then follows from the equations<maths id="math0004" num=""><math display="block"><mrow><msub><mrow><mtext>C.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><mtext>.</mtext></mrow></math><img file="EP0741299A2_D0004.tif" /></maths> In order to set the sum of the voltage changes during upward and downward integration equally, it is only necessary to use a voltmeter to determine when the voltage applied to the capacitors again reaches the initial value. At this moment, the charging or discharging of the capacitors is interrupted and the two sums of positive and negative voltage changes are the same. Instead of determining the quotient of the capacities from the last given equation, one can determine the relative capacity difference, ie the difference of the capacities divided by the sum of the capacities: (C.+-C-) / (C++ C-) from the equation derived from the previous equation<maths id="math0005" num=""><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext>-C</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> + I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext>) = (C</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><mtext>).</mtext></mrow></math><img file="EP0741299A2_D0005.tif" /></maths> It is particularly advantageous if the two current sources + I, -I supply currents whose current intensities have the same amount I+, I- to have. This value then falls out of the last equation. If the capacitances of the capacitors are known, the difference between the capacitances can be determined relatively precisely using this method, even if the measuring accuracy of the individual capacitances is not sufficient to determine this difference. This circuit arrangement and this measuring method can of course also be used to determine the capacitance of a capacitor very precisely from the difference between this unknown capacitance and the very precisely determined capacitance of a second capacitor used as a reference variable.

0012A development of the invention allows influences of parasitic capacitances on the measurement result to be eliminated or, when using a third capacitor, the capacitance of which is very precisely determined, the capacitance difference between the two capacitors to be measured can also be specified with absolute precision. This development of the invention is explained with reference to FIG. 2, in which a further capacitor 8 is present in parallel with the differential amplifier 3 between its inverting input and its output. This further capacitor 8 can either be a further component or a parasitic capacitance already present in the circuit arrangement, with FIG. 2 then only representing the equivalent circuit diagram of a real circuit according to FIG. 1. The measuring method then turns out z. B. as follows.

0013In the first phase of integration there are the first switch 5 and the second switch 6 z. B. as shown in the first switching position P1. The third switch 7 is in the other switching position P.2, so that the first capacitor 1 is connected to the positive current source + I and the second capacitor 2 is connected to the ground connection. The first capacitor 1 and the further capacitor 8 are then charged together with the positive current, the differential amplifier 3 charging the second capacitor 2 to the same voltage. Then only the first switch 5 is in the switching position P2 and the third switch 7 synchronously to the first switching position P.1 switched. Then only the further capacitor 8 is discharged with the negative current from the current source -I, while the voltage across the two capacitors connected to the ground connection is tracked by the differential amplifier.

0014Switching the first switch 5 and the third switch 7 again initiates the next integration cycle. Instead of starting in the constellation of the switching positions shown in FIG. 2, the second switch 6 and the third switch 7 can both both initially in the switching position P.1 be so that the first capacitor 1 and the second capacitor 2 are both connected to the ground terminal. The positive current from the current source + I is then initially used to charge only the further capacitor 8 or the parasitic capacitance. Then the further capacitor 8 and z. B. the first capacitor 1 discharged together after connection to the negative current source -I. You can also start with the negative current from the negative current source -I. The process of alternating charging and discharging is preferably ended at a moment when the voltage applied to the capacitors has reached the initial value again.

0015A second section of the method then takes place, in which, for. B. starts charging only the further capacitor 8. For this purpose, the second switch 6 and the third switch 7 are both in the switching position P.1 brought, so both capacitors connected to the ground connection. The further capacitor 8 is then charged again, but now the first switch 5 and the second switch 6 into the other switching position P after the charging time2 switched. Thereafter, the second capacitor 2 and the further capacitor 8 are discharged together. The first switch 5 and the second switch 6 are switched over again and the further capacitor 8 or the parasitic capacitance is charged again, and the switch is switched over again, the first switch 5 and the second switch 6 now being actuated synchronously. These integration cycles are ended when the voltage on the capacitors has reached the initial value again. For the evaluation of the measurement result, it is particularly advantageous if, for the first section of the measuring method, in which the first switch 5 is always switched synchronously with the one of the other two switches, the sum of all integration times of only the further capacitor - that is, if, for. B. all switches in switch position P1 are - is the same as the sum of the integration times of only the further capacitor in the second section of the method if the first switch 5 is always switched synchronously with the other of the two switches. As will be explained in more detail below using the equations used for the calculation, the evaluation is considerably simplified as a result.

0016In this embodiment of the invention there must also be a voltmeter which transmits the voltage applied to the capacitors to the control device. If the capacitance of the further capacitor 8 is not known, the control device must have means which allow the voltage changes to be added separately for a specific constellation of the switching positions of all switches for each section of the method. It is essential for the elimination of the influence of a parasitic capacitance, that is to say if the capacitance of the further capacitor 8 is not known, that the method is carried out in such a way that the four sums of the amounts of the voltage changes in each case for each section of the method and for each constellation the switching positions of the three switches added separately are the same. This addition of the amounts of the voltage changes can take place indirectly, because the current strengths of the charging current and the discharging current each remain constant. Every change in voltage is therefore proportional to the duration of the charge or discharge. It is therefore sufficient if, in the first section of the method, all the time intervals during which both the first capacitor and the second capacitor are connected to the ground connection are added, and at the end of this section it is checked via the voltmeter that the voltage applied to the capacitors Voltage has reached the initial value again, and if in the second section the integration cycles take place so often that the sum of the time intervals, during which again both the first capacitor and the second capacitor are connected to the ground connection, is equal to this sum from the first section. It then only needs to be checked by the voltmeter that at the end of the second section of the method the voltage applied to the capacitors also reaches the initial value so that the four sums of the amounts of voltage changes added separately for the sections and switching positions are all the same. The summation of the respective time intervals can be done digitally by simply counting the clock signals using a clock generator connected to the control device.

0017For the first section of this method, in which the further capacitor 8 is charged or discharged individually or together with the first capacitor 1, the following two basic equations are obtained, in which C0 the capacitance of the further capacitor 8 and C.1 the capacitance of the first capacitor 1 and t+, t- the times during which the first switch 5 in the switching position P1 or P2 was and U+ and U- the amounts of the associated changes in the voltage applied to the capacitors mean:<maths id="math0006" num=""><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub></mrow></mtd></mtr><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> = (C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0741299A2_D0006.tif" /></maths> The following basic equations result accordingly for the second section of the method, in which the variables are each provided with a line to differentiate the times and voltage changes compared to the first section of the method:<maths id="math0007" num=""><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></mtd></mtr><mtr><mtd><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> = (C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0741299A2_D0007.tif" /></maths> If, as described, the voltage across the capacitors reaches the initial value again after each section of the method, the following applies accordingly <maths id="math0008" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0008.tif" /></maths> and <maths id="math0009" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0009.tif" /></maths>. Each pair of basic equations thus supplies one of the following equations:<maths id="math0010" num=""><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>C.</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> = (C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub></mrow></mtd></mtr><mtr><mtd><mrow><msub><mrow><mtext>C.</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> = (C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0741299A2_D0010.tif" /></maths> Solving these equations according to C1 or C2 and subtraction returns<maths id="math0011" num=""><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> = = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> (Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext>, Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><mtext>).</mtext></mrow></math><img file="EP0741299A2_D0011.tif" /></maths> If, as already described above, the sum of the charging times of the further capacitor 8 is advantageously chosen to be the same in both sections of the method, that is <maths id="math0012" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0012.tif" /></maths> then the above equation can be simplified<maths id="math0013" num="(Glg.1)"><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> (Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0741299A2_D0013.tif" /></maths> With knowledge of the capacity C0 of the further capacitor 8, the difference in the capacitances C can be derived from this equation1 of the first capacitor 1 and C2 of the second capacitor 2 determine.

0018If the further capacitor 8 is an unknown parasitic capacitance, the first equation of the two pairs of basic equations according to C is used in the calculation0 resolved and the resulting term inserted in the second equation. Doing so again<maths id="math0014" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0014.tif" /></maths> and <maths id="math0015" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0015.tif" /></maths> considered. After insertion, the equation follows from the two second equations of the pairs of basic equations<maths id="math0016" num=""><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>/ Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> + + I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>/ Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>) = = (C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>/ Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> + + I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>/ Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><mtext>).</mtext></mrow></math><img file="EP0741299A2_D0016.tif" /></maths> If, as explained above, in each section of the method the sums of the magnitudes of the voltage changes are in each case the same size in one direction, ie if <maths id="math0017" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>U</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>U '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0017.tif" /></maths> then applies because of the first and third basic equations <maths id="math0018" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0018.tif" /></maths>. The above equation is then simplified<maths id="math0019" num="(Glg.2)."><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> + I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> - 2 I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext>) = = (C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0741299A2_D0019.tif" /></maths> The quotient can again be derived from this equation <maths id="math0020" num=""><math display="inline"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) / (C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0741299A2_D0020.tif" /></maths> the relative capacity difference.

0019For the evaluation, the quotient of the amounts of the current intensities I+/ I- be known. Current sources are advantageously used which deliver currents of the same magnitude but with the opposite direction of flow. If this is not possible or is not desired due to other circuit components, the amounts of the currents supplied by the positive current source + I and the negative current source -I can also be set differently. If the current strengths are not known, they can also be determined from the circuit arrangement according to the invention. This requires a reference measurement in which only a fixed capacitance of one or more of the existing capacitors is used. If only the capacity C0 the further capacitor 8 is used, the second switch 6 and the third switch 7 are both in the switching position P.1 brought or in another embodiment of the second switching device corresponding to the first capacitor 1 and the second capacitor 2 connected to the ground terminal. If the reference measurement is carried out, one of the other capacitors or all capacitors can be used together. It is only essential that the set position of the second switching device 6, 7 is not changed during this measurement. The connected capacities are also not changed for the duration of the measurement. The first switching device 5 switches back and forth between the positive and the negative current source. So there is an alternating time t ''+ loaded and a time t ''- unload. The times in which the first switching device 5 each in the switching position P1 and the times in which the first switching device 5 is in the switching position P2 are added separately. The result is the Σjt ''+ j and Σkt ''-k. The associated amounts of change in voltage across the charged or discharged capacitor are also added separately to the sums ΣjU ''+ j and ΣkU ''-k. Then the equations apply<maths id="math0021" num=""><math display="block"><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub><msub><mrow><mtext> = C Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>U ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub><mtext> and</mtext></mrow></math><img file="EP0741299A2_D0021.tif" /></maths><maths id="math0022" num=""><math display="inline"><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub><msub><mrow><mtext> = C Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>U ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0022.tif" /></maths>, where C is the capacitance of the capacitor in question. If the last charging or discharging process takes so long that<maths id="math0023" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>U ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>U ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0023.tif" /></maths> applies what z. B. can be easily determined by the fact that then the voltage across the capacitor is equal to the initial voltage, follows immediately from the equations<maths id="math0024" num=""><math display="block"><mrow><msub><mrow><mtext>I.</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub><msub><mrow><mtext> = I</mtext></mrow><mrow><mtext>-</mtext></mrow></msub><msub><mrow><mtext> Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub><mtext>.</mtext></mrow></math><img file="EP0741299A2_D0024.tif" /></maths> The quotient I can be immediately derived from this equation+/ I- to calculate. If the sum of the charging and discharging times are selected so that<maths id="math0025" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0025.tif" /></maths>, then equations 1 and 2 are simplified<maths id="math0026" num="(Glg.1')"><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub><msub><mrow><mtext> = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> (Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0741299A2_D0026.tif" /></maths> or.<maths id="math0027" num="(Glg.2')."><math display="block"><mrow><msub><mrow><mtext>(C.</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> - C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> + Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> - 2 Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub><msub><mrow><mtext>) = = (C</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> + C</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>) (Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0741299A2_D0027.tif" /></maths>

0020The integration is reasonably designed in such a way that either charging and discharging is carried out the same number of times, or that charging or discharging is carried out at most once, that is, there is no switching back and forth without a charging or discharging process taking place in between. The numbers of the summands belonging to a summation index in the associated pairs of basic equations are therefore either the same or differ by at most one. For the calculation, as can be seen from the equations given, it is necessary that the control device 4, which may include a computing or evaluation device, has means with which the respectively measured time intervals can be added, and that the Control device 4 also has means which automatically switches the switching devices synchronously or interrupts the integration when a certain voltage at the capacitors is reached. Possibly. Means must also be available to add detected voltage changes and to store the value of the sum, which must then be able to be compared with another value. The summation, storage and comparison of voltage differences is always to be understood, particularly when interpreting the claims, that these voltage differences can be recorded in the form of time intervals proportional to the actual voltage differences and that the specified operations are carried out with these time intervals (integration times).

0021When eliminating parasitic capacitance, it suffices e.g. B. if the voltage changes when loading the parasitic capacitance are added by the one current source in each case. This value is stored by the control device 4. It is also compared by comparing the voltage across the capacitor with the stored initial value (e.g. Voltage 0 at full discharge) ensure that the capacitors are back to the initial value of the voltage after the first section of the process. In the second section of the method, all voltage changes that occur when charging only the parasitic capacitance alone are added accordingly. The loading process is stopped at the moment when this sum corresponds to the previously saved sum. The unloading occurs again until the initial voltage is reached. In this way it is achieved that the four sums of the amounts of the voltage changes appearing in the equations are of equal size. It is therefore only necessary for the control device 4 to add a voltage difference to an already stored value after every second switchover operation and to store the maximum value reached in between and to compare the subtotals of the voltage changes achieved in each case. As described above, this can be done directly by counting the same long time intervals determined by a clock. A comparison of the numbers determined in this way is sufficient for the sequence control of the method, because the respective total amounts of the voltage changes with analog evaluation of actually measured and added voltage changes would only have to be compared with one another for equality and the amount in volts is not used in the further calculation would need to be.

0022If the two currents are equal in amount or if a reference measurement is used to determine I+/ I- the sums of the charging times are chosen the same as described above, the equations used for the calculation are simplified (see equations 1 'and 2') so that the relative capacitance difference or the capacitance difference based on the capacitance of the further capacitor from the various sums of Loading and unloading times can be easily calculated. It is therefore only necessary to add these times separately and to save the respective sums for the calculation. From the equations on which the calculation is based, in the largely simplified form, which are applicable to the preferred embodiments of the measuring method described, it can be seen that the result can be calculated by adding, subtracting, multiplying and dividing only time intervals, these times being divided by a certain number of clock signals, the spacing of which determines the smallest time intervals, are defined and therefore only numbers have to be expected.

0023The times of the loading and unloading processes can all be selected the same or different instead of the last. To simplify the calculation, the last integration time must be chosen so that the initial voltage on the capacitors is reached again. If you basically allow different integration times, the control device can e.g. B. be provided with means which switch the switching devices synchronously when a predetermined maximum or minimum voltage is reached across the capacitors. The times t+"t"+, t-"t"-, t ''+ and t ''- can then be different from each other, but in each integration cycle z. B. be the same. If the sections of the procedure begin in the same constellation of switch positions,<maths id="math0028" num=""><math display="inline"><mrow><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+</mtext></mrow></msub><msub><mrow><mtext> = t '</mtext></mrow><mrow><mtext>+</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0028.tif" /></maths> be. The required equality of the sums of the amounts of the respective voltage changes in one direction then automatically results from the equality of the numbers of charging and discharging processes. A digital summation of the integration times is also possible here if the control device is clocked.

0024A digital evaluation of the measurement can e.g. B. with the circuit arrangements shown in Figures 1 and 2 on the right side in the scheme. In this example, the integration cycles take place between a voltage U.L and a voltage UH. The control device 4 is connected to the output of the first differential amplifier 3 via two differential amplifiers 10, 11. One of the inputs of these differential amplifiers is at the potential of one of these voltages U.L, UH. There are counters 12, 13, a divider 14 and a clock 9 (trigger). These counters 12, 13 are switched on and off by the control device 4 and count the time units given by the clock generator. The counter 12 can be switched between addition and subtraction (up / down counter), for which the control line 23 is provided.

0025The measurement is designed in such a way that these counters 12, 13 first receive a reset command from the control device 4 via the corresponding control line 24 (RESET) to an initial value ("ZERO"). The measurement of the capacities begins after the control device 4 has switched the switching devices 5, 6, 7 so that the capacitors z. B. on the voltage UL are charged. The switching devices for the first integration cycle are then switched. In the example of Figure 1 z. B. the first switch 5 in the switching position P.1, the second switch 6 in the switching position P1 and the third switch 7 in the switching position P2 brought. Counters 12, 13 are started simultaneously via control lines 22, 25 (ENABLE). As long as the voltage UH has not yet been reached at the capacitors, the counters add up the time intervals given by the clock generator. If the voltage UH is reached, the control device switches the switching devices, so that in this example the three switches 5, 6, 7 are switched to the other switching position. At the same time, the first counter 12 is set to subtraction via the control line 23 (UP / DOWN), so that this counter now counts the time intervals negatively. The capacitors are discharged until the voltage UL is achieved. This integration cycle is e.g. B. run n times. The control lines 21, 26 (ENABLE, LOAD) between the control device 4 and the divider 14 are then used to load the values determined by the counters into the divider 14 and to carry out the division. The result of this division immediately gives the quotient of the sum and difference of the capacities.

0026The arrangement according to FIG. 2 comprises two further counters 15, 16, which are intended to determine whether the sums of all loading times are the same in the different sections of the method. With this arrangement, all counters 12, 13, 14, 15 can be switched between addition and subtraction (up / down counter), for which purpose the control lines 23, 27, 29, 31 (UP / DOWN) are provided. Here too, the control line 24 (RESET) transmits the reset command for the initial state "ZERO" to the counters so that a new measurement can be started. In the first section of the process, in which e.g. B. in each integration cycle, the first switch 5 and the third switch 7 are each switched synchronously, the third counter 15 is set via the corresponding control line 28 (ENABLE) to add the time intervals given by the clock 9. In the second section of the method, the first switch 5 and the second switch 6 are switched synchronously. So that the sum of all loading times in this second section of the method, the sizes of which are each provided with a line in the above-mentioned calculations, is equal to the sum of the loading times in the first section of the method, z. B. of the third counter 15 via the control line 29 (UP / DOWN) to subtraction this counter value is reduced at every time interval until the initial value ("ZERO") is reached again. Then the number of all loading times in the second section of the method is equal to the number of all loading times in the first section of the method.

0027With this way of carrying out the method, e.g. B. the quotient of the difference and the sum of the capacitances to be measured can be determined according to equation 2 given above. With the first counter 12 z. B. in the case of equal amounts of the currents of the positive current source + I and the negative current source -I the value of the expression<maths id="math0029" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0029.tif" /></maths> certainly. With the second counter 13, the value of the expression<maths id="math0030" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> + Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> - 2 Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0030.tif" /></maths> certainly. For this purpose, all counters are first reset to the initial value ("ZERO") via the control line 24 (RESET). The capacitors are connected to the voltage UL charged. The measurement begins with all three switches 5, 6, 7 in switch position P.1. At the same time, the second counter 13 is started via the control line 25 (ENABLE) and set to subtraction via the control line 27 (UP / DOWN). The third counter 15 is started via the control line 28 for addition. Then the charging process takes place until the voltage on the capacitors of UL on UH has risen. Then the control device 4 switches the first switch 5 and the third switch 7 into the other switching position P.2 switched. At the same time, the first counter 12 is started via the control line 22 (ENABLE), the second counter 13 is switched to addition via the control line 27 (UP / DOWN) and the third counter 15 is stopped. If the voltage on the capacitors of UH to the value UL has changed, the control device 4 again switches the first switch 5 and the third switch 7 to the first switching position P.1. The first counter 12 is stopped via the control line 22, the second counter 13 is switched to subtraction via the control line 27 (UP / DOWN), and the third counter 15 is started via the control line 28 (ENABLE) for addition. This integration cycle is repeated as often as intended.

0028Then the second stage of the process begins. The control device 4 sets the switches 5, 6, 7 to the switching position P1, stops the first counter 12 via the control line 22, starts the second counter 13 via the control line 25 and switches it to subtraction via the control line 27 and starts the third counter 15 via the control line 28 and simultaneously switches it via the control line 29 (UP / DOWN) on subtraction. Based on the voltage UL The charging process takes place on the capacitors until the voltage UH is reached. Then the control device 4 switches the first switch 5 and the second switch 6 to the other switching position P.2. At the same time, the first counter 12 is started and set to subtraction via the control line 22 and the control line 23, the second counter 13 is set to addition via the control line 27 and the third counter 15 is stopped via the control line 28. If the voltage on the capacitors of UH to the value UL has changed, the control device 4 again switches the first switch 5 and the second switch 6 to the first switching position P.1. This integration cycle is repeated in the second section of the method until the third counter 15 has reached the initial value ("ZERO"). The control lines 21, 26 (ENABLE, LOAD) between the control device 4 and the divider 14 are then used to load the values determined by the first counter 12 and by the second counter 13 into the divider 14 and to carry out the division.

0029If the amounts of the current strengths of the positive and negative current sources are not the same and their quotient has to be determined, the otherwise unnecessary fourth counter 16 can be used to ensure the same sum of the total charging times for a third section of the method. For this purpose, the fourth counter 16 is started together with the third counter 15 for addition. The control line 30 (ENABLE) is provided for this. In the second section of the method, in which the third counter 15 subtracts, the fourth counter 16 remains switched off. In a third section of the method, this counter 16 is then set to subtraction via the relevant control line 31 (UP / DOWN) and this third section of the method is continued until the fourth counter 16 displays the initial value (“NULL”). With a reference measurement with<maths id="math0031" num=""><math display="inline"><mrow><msub><mrow><mtext>C = C</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0031.tif" /></maths> the second switch 6 and the third switch 7 are both in the switching position P.1, while the first switch 5 is switched between the switching positions. The first counter 12 and the second counter 13 are started via the control lines 22, 25 and switched over the control lines 23, 27 between addition and subtraction so that, for. B. the first counter 12 the value<maths id="math0032" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> - Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0032.tif" /></maths> and the second counter 13 the value<maths id="math0033" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>G</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>-G</mtext></mrow></msub><msub><mrow><mtext> + Σ</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>-i</mtext></mrow></msub><msub><mrow><mtext> - 2 Σ</mtext></mrow><mrow><mtext>k</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>-k</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0033.tif" /></maths> determined. The control device 4 can then use the control lines 21 and 26 to instruct the divider again to divide these values determined by the first counter 12 and the second counter 13. The third counter 15 and the fourth counter 16 are started or stopped by the control device via the control lines 28, 30 and switched from addition to subtraction via the control lines 29, 31 in such a way that in a section of the method the relevant number either only during the charging processes the time intervals of both counters are added or each is subtracted from a counter from the previously obtained value down to the initial value. By using a third counter 15, which emits a signal to the control device 4 if the initial value is reached again, it is therefore also possible for two sections of the method <maths id="math0034" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext>t '</mtext></mrow><mrow><mtext>+ h</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0034.tif" /></maths> can be achieved. With the fourth counter 16, the equality of the sum of the time intervals can also be achieved for a third section, that is<maths id="math0035" num=""><math display="inline"><mrow><msub><mrow><mtext>Σ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>t</mtext></mrow><mrow><mtext>+ f</mtext></mrow></msub><msub><mrow><mtext> = Σ</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext>t ''</mtext></mrow><mrow><mtext>+ j</mtext></mrow></msub></mrow></math><img file="EP0741299A2_D0035.tif" /></maths>.

0030An expedient implementation of this method with reference measurements using all four counters is as follows in detail. First, all the capacitors 1, 2, 8 are switched to the voltage U at the suitable switching positions of the switches via the current sourcesL loaded. The control device 4 then switches the first switch 5, the second switch 6 and the third switch 7 to the first switching position P.1. Simultaneously with the start of the integration, the third counter 15 is started via the control line 28 and the fourth counter 16 via the control line 30 for addition. If the voltage UH is reached on the capacitors, the control device switches the first switch 5 and the third switch 7 in the other switching position P.2. At the same time, the first counter 12 is started via the control line 22 and the second counter 13 via the control line 25 for addition, and the third counter 15 and the fourth counter 16 are stopped. If the output voltage UL on the capacitors is reached again, the first integration cycle has ended. The control device stops the first counter and the second counter via the control lines 22, 25, switches the first switch 5 and the third switch 7 into the switching position P again1 and starts the third counter 15 and the fourth counter 16 again via the control lines 28, 30 for addition.

0031After the intended number of integration cycles has been completed, the control unit stops the counters, switches the first switch 5, the second switch 6 and the third switch 7 to the switching position P, respectively1 and starts the third counter 15 via the control line 28 and switches this counter via the control line 29 to subtraction. The charging process then takes place again until the voltage U on the capacitorsH is reached. The third counter 15 is then stopped via the control line 28. In this second section of the method, before the capacitors are discharged, the first switch 5 and the second switch 6 are switched to the other switching position P2 switched, the first counter 12 started via the control lines 22 and 23 for subtraction and the second counter 13 started via the control line 25 for addition. If the capacitors have the value UL voltage is reached again, the counters are stopped and a new integration cycle can begin. For this purpose, the control device switches the first switch 5 and the second switch 6 into the switching position P again1 and starts the third counter 15 over the control line 28 again for subtraction. The integration cycles in this second section of the method are carried out until the third counter 13 has reached the initial value ("ZERO") again.

0032Then the third section of the process begins, in which the switches are all initially in switch position P1 be set and the fourth counter 16 for subtraction is started via the control lines 30 and 31. After the capacitors on the voltage UH are loaded, the control device switches the first switch 5 to the switching position P.2, starts the second counter 13 for subtraction with double step size (that is, the time intervals are counted twice) via the control lines 25 and 27 and stops the fourth counter 16 via the control line 30L is reached on the capacitors, this integration cycle of the third section has ended. All switches are again in switch position P1 brought, the second counter 13 is stopped and the fourth counter 16 is started again via the control line 30 for subtraction. These integration cycles are repeated until the fourth counter 16 has reached its initial value ("ZERO") again. The values which are then stored in the first counter 12 and in the second counter 13 can then be loaded again into the divider 14 for the division, which is initiated via the control lines 21 and 26. The further evaluation takes place as previously described.

0033In addition, it should also be mentioned that synchronous switching of the switching devices is also to be understood as the process in which the current sources are first switched off, ie the first switch 5 is neither connected to one or the other connection, then the other switches are switched and then the connection to the power source is made. In this way, such embodiments of the method are included in which, for. B. due to a certain inertia of the switching devices, a sufficiently simultaneous switchover cannot take place. The current source is then first switched off, then all switches are brought into the new constellation of the switching positions and only then is the current source connected via the first switch 5. In the sense of the method according to the invention, this process is also to be understood as a synchronous switchover.

0034The present invention thus makes it possible to carry out a digital measurement of capacitance differences in a simple manner without the disruptive influence of parasitic capacitances, no high-precision elements being required for the configuration of the circuit arrangement. The method according to the invention for eliminating parasitic capacitances using the specified circuit arrangement specifically enables the application of the invention to evaluate the measurement results of micromechanical sensors.

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Document	Relation	Office	Cited during
US10877064B2	Cited by	United States of America	Applicant
CN106687777A	Cited by	China	Search report
US4459541A	Cites	United States of America	Search report
US5028876A	Cites	United States of America	Search report
US5194819A	Cites	United States of America	Search report

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19513022	Germany	A	1995-04-06
19513022	Germany	–	1995-04-06
DE1995113022	–	–	–
19513022	–	–	–

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DE19513022C1	Germany	C1	1996-08-14
JPH08285904A	Japan	A	1996-11-01
EP0741299A2This record	European Patent Office (EPO)	A2	1996-11-06
US5629629A	United States of America	A	1997-05-13
EP0741299A3	European Patent Office (EPO)	A3	1998-03-04
JP3530306B2	Japan	B2	2004-05-24
EP0741299B1	European Patent Office (EPO)	B1	2007-01-24
DE59611414D1	Germany	D1	2007-03-15

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Circuit for determining differences in capacity

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