Full flash analog-to-digital converter

A full flash analog-to-digital converter comprises a plurality of comparators for comparing an analog input voltage with respective reference voltages, a first-stage encoder for generating low-order bits based on output signals from the comparators, a second-stage encoder for generating high-order bits based on the low-order bits generated by the first-stage encoder, the first-stage encoder comprising a circuit for generating a complement bit of the highest-order bit of the low-order bits generated by the first-stage encoder, and the second-stage encoder comprising a circuit for generating the high-order bits based on the highest-order bit and the complement bit.