A circuit for driving a thin film transistor liquid crystal display
Abstract
Described in this invention is a circuit for driving a thin film transistor liquid crystal display (TFT-LCD) which reduces the number of the analog switch and power consumption by omitting the large power consumption elements such as the operational amplifier and the push-pull amplifier.

Term
Term ended
Projected expiry passed 12 February 2016, 10.6 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
4 claims: 1 independent, 3 dependent
- 1A circuit for driving a thin film transistor liquid crystal display (TFT-LCD), which comprises:an analog switch for carrying out the switching operation in responce to a switching signal;a circuit connected to the analog switch for generating a common electrode voltage in response to the analog switching signal;a circuit connected to the analog switch for generating a gate-on voltage to turn on the thin film transistor by shifting the analog switching signal to a predeteminded potential and converting the shifted signal;and a circuit connected to the analog switch for generating a gate-off voltage to turn on the thin film transistor in response to the analog switching signal.
49 paragraphs, as filed
0001The present invention relates to a circuit for driving a thin film transistor liquid crystal display (TFT-LCD), which more specifically generates a signal capable of driving a thin film transistor liquid crystal display with low-power consumption.
0002In these days, the technology of screen informations has been concentrated on the production of display devices. In particular, flat panel display devices have grown increasingly popular as substitutes for a cathod ray tubes and are now being produced on a commercial scale.
0003Liquid crystal displays, among the various types of the flat panel display devices, are particularly well matched to integrated circuits because of their thinness, low-weight, low-cost, and low-power consumption. Accordingly, liquid crystal displays have been widely applied to laptopcomputors, pocket computors, automobiles, and color televisions.
0004There have been generally known two methods of driving a liquid crystal display: one is an AC common driving method; another is a DC common driving method.
0005The typical AC common driving method is described below with reference to the appending drawings.
0006Fig. 1 is a waveform for driving a prior art TFT-LCD, Fig. 2 is a circuit block diagram for driving a prior art TFT-LCD and Fig. 3 shows a detailed circuit diagram of a prior art analog switch for a TFT-LCD.
0007As shown in Fig. 1, to drive the TFT-LCD, there are basically provided a common electrode voltage generating wave Vcom for generating a constant voltage (VgL1 - VgL2) periodically, a gate-on voltage generating wave Vgh for generating an absolute constant voltage of VgL1 - VgL2 which causes the TFT-LCD to be turned on, and a gate-off voltage generating wave Vgl for generating an absolute constant voltage of VgL1 - VgL2 which causes the TFT-LCD to be turned off.
0008To create such waveforms, it has been used a construction shown in Fig. 2, which is comprised of analog switches 1, 3 and 5 for generating a rectangular waveform in response to an analog switching signal POL; and buffers 2, 4 and 6 for amplifying power in response to the input rectangular waveform, so that the TFT-LCD starts to be operated.
0009The operation of such a constructed TFT-LCD is described below.
0010The operation of the TFT-LCD is begun with the application of power by a user.
0011The switching signal POL is then applied to the analog switches 1, 3 and 5, and the input analog swiching signal POL is converted to a rectangular wave.
0012The rectangular waveform is outputted to the buffers 2. 4 and 6 and then amplified. Next, the amplified waveform is outputted as each waveforms as a common electrode voltage generating waveform Vcom, a gate-on voltage generating waveform Vgh and a gate-off voltage generating waveform Vgl, each serving as the driving signal of the TFT-LCD.
0013The above-mentioned operation is described below in more detail with reference to Fig. 3.
0014In this figure, the switching signal POL is an inverse signal which causes the analog switches l, 3 and 5 to be turned on or off, and voltages V1 and V2 are potentials inputted from the analog switches, each having a different level.
0015As shown in this figure, provided that the switching signal POL is at a high state, the buffer AS1 is turned on and the inverter AS2 is turned off, thereby outputting the voltage V1, whereas provided that the switching signal POL is at a low state, the buffer AS1 is turned off and the inverter AS2 is turned on, thereby outputting the voltage V2.
0016As a result, the analog switch generates a rectangular waveform having the voltages V1 and V2 in response to the analog switching signal POL.
0017In such an operation, the buffers 2, 4 and 6 each composed of the operational amplifier and the push-pull amplifier enable the power to be compensated, thereby generating the common electrode voltage generating waveform Vcom, the gate-on voltage generating waveform Vgh and the gate-off voltage generating waveform Vgl.
0018However, many disadvantages can be generated from the prior art construction. Included among these are that power consumption of the entire circuits is large because the buffer and the switch are composed of large power consumption elements such as the operational amplifier and the push-pull amplifier, and that there generates a constant offset voltage of the operational amplifier to the power source and a lowered voltage between the base and the emitter of the push-pull circuit, giving a difficulty to the generation of the rectangular wave of the power source voltage. Another disadvantge is that power consumption drastically increases because a higher voltage than a desired rectangular waveform is required.
0019In view of the above, it is an object of the present invention to provide a circuit for driving a thin film transistor liquid crystal display (TFT-LCD) capable of reducing power consumption and outputting power source voltage.
0020To achieve this object, according to a preferred embodiment of the present invention, a circuit is provided which comprises: an analog switch for carrying out the switching operation in responce to a switching signal; a circuit connected to the analog switch for generating a common electrode voltage in response to the analog switching signal; a circuit connected to the analog switch for generating a gate-on voltage to turn on the thin film transistor by shifting the analog switching signal to a predeteminded potential and converting the shifted signal; and a circuit connected to the analog switch for generating a gate-off voltage to turn on the thin film transistor in response to the analog switching signal. <ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1 is a waveform for driving a prior art TFT-LCD;</li><li>Fig. 2 is a circuit block diagram for driving a prior art TFT-LCD;</li><li>Fig. 3 is a detailed circuit diagram of a prior art analog switches;</li><li>Fig. 4 is a circuit diagram for driving a TFT-LCD of a preferred embodiment of the present invention;</li><li>Fig. 5 shows each waveform for driving a TFT-LCD of a preferred embodiment of the present invention; and</li><li>Fig. 6 shows waveforms from each circuit for driving a TFT-LCD of a preferred embodiment of the present invention.</li></ul>
0021A preferred embodiment of the present invention is described with reference to the accompanying drawings.
0022As shown in Fig. 4, a circuit for driving a TFT-LCD, which is comprised of an analog switch 10 for carrying out the switching operation in response to a switching signal POL; a common electrode voltage generating cicuit 11 connected to the analog switch 10 for generating a common electrode voltage in response to the analog switching signal POL; a gate-on voltage generating circuit 12 connected to the analog switch 10 for generating a gate-on voltage which causes a TFT to be turned on by shifting the analog switching signal to a constant potential and converting the shifted signal; and a gate-off voltage generating circuit 13 connected to the analog switch 10 for generating a gate-off voltage which causes the TFT to be turned off in response to the analog switching signal.
0023More detailed construction is described below with the same figure.
0024The switching signal POL as the inverse signal is inputted to the analog switch 10.
0025The analog switch 10 is connected to gate terminals of a first MOS transistor M1 and a second MOS transistor M2 of the common electrode generating circuit 11, a first capacitor C1 of the gate-on voltage generating circuit 12, and a gate terminal of a fourth MOS transistor M4 of the gate-off voltage generating circuit 13.
0026The common electrode voltage generating circuit 11 is connected to a second capacitor C2 of the gate-on voltage generating circuit 12 and a third capacitor C3 of the gate-off voltage generating circuit 12.
0027Further, the gate-on voltage generating circuit 12 is constructed in such a manner that anode of a first diode D1 is connected to a power source VCC and cathod is connected to the first capacitor C1 and a gate terminal of a third MOS transistor M3. A source terminal of the third MOS transistor M3 is connected to a power source VGG and a drain terminal of the third MOS transistor M3 is connected to the second capacitor C2.
0028The gate-off voltage generating circuit 13 is constructed in such a manner that a source terminal of the fourth MOS transistor M4 is connected to a power source VEE and a drain terminal of the fourth MOS transistor M4 is connected to the third capacitor C3.
0029The operation of the driving circuit of this invention is described below.
0030The analog switch 10 receives the switching signal POL and creates a rectangular waveform which causes the first, second and fourth MOS transistors M1, M2 and M4 to be turned on.
0031In such a operation, the voltages are given by<maths id="math0001" num=""><math display="block"><mrow><mtext>VGG > VCC > VDD > GND > VEE,</mtext></mrow></math><img file="EP0726558A1_D0001.tif" /></maths> and<maths id="math0002" num=""><math display="block"><mrow><mtext>VGG < VCC + | VCC - VEE |</mtext></mrow></math><img file="EP0726558A1_D0002.tif" /></maths>
0032In the output waveform of the analog switch 10, provided that the switching signal POL is low, the buffer AS1 shown in Fig. 3 is turned off and the inverter AS2 is turned on, whereby the reference voltage VEE is outputted. whereas provided that the switching signal POL is high, the buffer AS1 is turned on and the inverter AS2 is turned off, whereby the voltage VCC is outputted.
0033When the analog switch 10 outputs the voltage VEE, the first MOS transistor M1 of P-type of the common electrode generating circuit 11 is turned on and the voltage VDD is outputted from the drain of the first MOS transistor M1. Whereas, when the analog switch 10 outputs the voltage VCC, the second MOS transistor M2 of N-type of the common electrode generating circuit 11 is turned on and the ground voltage GND which is connected to the source of the second MOS transistor M2 is outputted to the drain, thereby creating the common electrode voltage generating waveform Vcom as shown in Fig. 5.
0034Differently from the above, the waveform at the first node Nl is level-shifted as much as the voltage VCC - VEE as shown in Fig. 6.
0035In detail, when the first node Nl outputs the voltage VEE, the first diode Dl is turned on and the third node N3 outputs the voltage VCC-V<sub>BE</sub>, whereby the first capacitor C1 charges (VCC-VBE-VEE)*Cl.
0036Next, when the first node N1 outouts the voltage VCC, the first diode D1 is turned off, the first capacitor C1 charges (VCC-VBE-VEE)*C1 and the third node N3 outputs VCC+VCC-VBE-VEE, thereby creating the common electrode voltage generating waveform Vcom as shown in Fig. 5.
0037Thus a formed waveform of the third node N3 is turned on or off the third MOS transistor M3.
0038The third MOS transistr M3 is turned on when the third node N3 has the voltage VC, and thus the voltage VGG of the source is outputted to the drain.
0039As a result, the second capacitor C2 which is connected to the waveform Vcom charges C2*(VGG-VDD). This electric charge is maintained even though the third MOS transistor M3 is turned off, i.e., the third node N3 is at 2*VCC-VEE, so that the fourth nodd N4 is at VGG-VDD-GND and generates the voltage VGG-VDD.
0040The gate-on voltage generating waveform Vgh is created when the above-mentioned operation is repeated as shown in Fig. 5.
0041Whereas, when the first node Nl is at the lebel VCC, the fourth MOS transistor M4 of the gate-on voltage generating circuit 13 is turned on and the fifth node N5 shows the level VEE.
0042At this time, the third capacitor C3 charges C3*(VEE-GND) and the first node N1 shows the level VEE. Accordingly, the common electrode voltage generating waveform Vcom is at the lebel VDD when the fourth MOS transistor M4 is turned off, so that the fifth node N5 shows the level VEE+VDD.
0043The gate-off voltage generating waveform Vgl is created when the above-mentioned operation is repeated as shown in Fig. 5.
0044As mentioned above, it is possible to obtain the improved driving circuit of the TFT-LCD which reduces power consumption by reducing the number of the analog switch and omitting the operational amplifier and the push-pull amplifier.
0045The resultant circuit has some advantages which are summarized below.
0046Firstly, power consumption is reduced drastically.
0047Secondly, good quality image can be obtained since the common elctrode voltage generating waveform and the gate-on voltage generating waveform are the same.
0048Thirdly, the best charateristics of the display can be realized by obtaining a maximun possible driving ability of the TFT-LCD.
0049Fourthly, large productivity of this circuit is permitted because there is no additional external variable resistor for controlling lebel. In other words, the number of the elements is reduced, without the requirement of the control time.
6 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6
Every citation, both ways
| Document | Relation | Office | Category | Cited during |
|---|---|---|---|---|
| CN100399409C | Cited by | China | – | Search report |
| EP0242468A1 | Cites | European Patent Office (EPO) | A | Search report |
| EP0447919A2 | Cites | European Patent Office (EPO) | A | Search report |
| GB2188471A | Cites | United Kingdom | A | Search report |
| DE4306988A1 | Cites | Germany | A | Search report |
9 members in 6 offices; this record represents the family
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 19950002511 | Republic of Korea | A | |
| 9502511 | Republic of Korea | – | |
| KR19950002511 | – | – | – |
| 9502511 | – | – | – |
Members9
| Document | Office | Kind | |
|---|---|---|---|
| EP0726558A1This record | European Patent Office (EPO) | A1 | |
| KR960032280A | Republic of Korea | A | |
| JPH08248390A | Japan | A | |
| KR0134919B1 | Republic of Korea | B1 | |
| US5754151A | United States of America | A | |
| EP0726558B1 | European Patent Office (EPO) | B1 | |
| DE69627735D1 | Germany | D1 | |
| TW568317U | Taiwan Province of China | U | |
| JP3534519B2 | Japan | B2 |
22 legal events, as 2 offices reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | Office | |
|---|---|---|---|
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Patent expired after termination of 20 yearsExpiredPE20 | PE20 | GB | |
| Annual fee paid to national office [announced via postgrant information from national office to epo]GrantedPGFP | PGFP | EP | |
| Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)REGISTERED BETWEEN 20130307 AND 20130313732E | 732E | GB | |
| Fr: translation not filedEN | EN | EP | |
| No opposition filedOpposition26N | 26N | EP | |
| No opposition filed within time limitOppositionORIGINAL CODE: 0009261PLBE | PLBE | EP | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: NO OPPOSITION FILED WITHIN TIME LIMITSTAA | STAA | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Corresponds to:REF | REF | EP | |
| European patent grantedGrantedFG4D | FG4D | GB | |
| Designated contracting statesAK | AK | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| (expected) grantORIGINAL CODE: 0009210GRAA | GRAA | EP | |
| Despatch of communication of intention to grant a patentORIGINAL CODE: EPIDOS IGRAGRAH | GRAH | EP | |
| Despatch of communication of intention to grantORIGINAL CODE: EPIDOS AGRAGRAG | GRAG | EP | |
| Despatch of communication of intention to grant a patentORIGINAL CODE: EPIDOS IGRAGRAH | GRAH | EP | |
| Despatch of communication of intention to grantORIGINAL CODE: EPIDOS AGRAGRAG | GRAG | EP | |
| First examination report despatched17Q | 17Q | EP | |
| Request for examination filed17P | 17P | EP | |
| Designated contracting statesAK | AK | EP | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI | EP |
Numbers
- Publication
- 0726558
- Publication, DOCDB
- 0726558
- Publication, EPODOC
- EP0726558
- Application
- 96300955
- Application, DOCDB
- 96300955
- Application, EPODOC
- EP19960300955
Titles3
- German
- Treiberschaltung für eine Flüssigkristallanzeige mit Dünnfilmtransistoren
- English
- A circuit for driving a thin film transistor liquid crystal display
- French
- Circuit de commande pour un dispositif d'affichage à cristaux liquides comprenant des transistors en couche mince
Classification
- CPC, 2
- G09G3/3696
- G09G2330/021
- IPC, 2
- G02F1 133
- G09G3 36
Designated states3
- Contracting states, 3
- Germany
- France
- United Kingdom