Synchronous digital transmission system with hierarchical synchronisation network

p0001The invention relates to a synchronous digital message transmission system according to the preamble of claim and a network element according to the preamble of claim 6 for a synchronous digital communication system.

p0002A synchronous digital transmission system operates, for example, according to a standard for synchronous digital hierarchy (SDH / SONET standard). In such a digital transmission system, individual network elements are interconnected by various transmission media (eg, copper cables, optical fiber or radio links).

p0003A connection of a network element is a transmission medium through interface devices (network node interface), for example, from the ITU-T Recommendations G.703 and G.957 are known. In Recommendation G.703 specifications are electrical properties of such interface devices and the Recommendation G.957 specifications of optical properties of the interface devices are given. In an interface device, which is connected to an optical fiber, for example, incoming optical signals are converted by an opto-electric transducer into electrical signals.

p0004A network element is for example an exchange of a public switched telephone network, or a cross-connect or an ADD / Dropp Multiplexer. An installed in the central office switching principle requires that all switches in the system operate synchronously. For an overview, how to synchronize the exchanges can take place, is the article by M. Wolf et al, "Synchronization and timing", Electrical Communication (Alcatel), 4th Quarter 1993, pages 349-358.

p0005There are two methods for synchronization of network elements are called: master / slave synchronization and mutual synchronization.

p0006The master / slave principle, a single primary reference clock for synchronizing a first hierarchical level of node is used. These nodes transfer their derived clocks on the nodes of the next level and so on. In the process of mutual synchronization, all nodes are equivalent interconnected by the existing digital links. In each node, an average phase value is calculated from the incoming clock signals and its own internal clock.

p0007A hierarchical synchronization system thus is given when the master / slave principle. In a system according AESS standard for synchronous digital hierarchy (SDH), a framework is set, the in a multiplex section has a called SOH area. (SOH: Section overhead). This SOH a synchronization quality indicator is transmitted, for which the bits are set 5 to 8 of the S1 byte. (See, for example ITU-T Recommendation G. 707, G.708 or G.709)

p0008This synchronization quality indicator indicates a quality class of a transmitted standardized reference clock and provides a powerful, autonomous function to improve quality management of synchronization. The synchronization quality indicator is commonly known as "synchronization status message" and will be referred to with SSM. By bits 5 to 8 of the S1 byte are uazB standardized reference clocks G. 811, G. 812 ITU-T or a message "Do not use for synchronization" set, which is hereinafter referred to as DNU.

p0009A working document by B. Neihoff, "More on Synchronization Status Message problems", ETS / TM3 / WG6, Working Document 22, Oslo, 25-29 October 1993, it is known that when using SSM problems can arise. These include, for. Example, synchronization loops (timing loops) that arise when such there in FIG. 2, a network element (SDXC) its selected reference clock source (selected source) loses and by means of a selection procedure (synchronization source selection algorithm, SSSR) a other reference clock source selects. It is also noted that such synchronization loops can occur in any network configuration, end in the two bidirectional SSM paths in the same network element and are also produced there. The working document is proposed to solve the problem of defining "enable / disable" functions.

p0010The invention addresses the problem of providing another digital communication system in which no synchronization loops may occur. A task solved the digital communications system is the subject of claim 1. Furthermore, the invention has for its object to provide a network element for such a digital communication system. A task-solving network element is the subject of patent claim 6.

p0011Advantageous embodiments of the invention are specified in the subclaims.

p0012The invention is explained in more detail below with reference to drawings. Show it:<dl id="dl0001"><dt>Fig. 1</dt><dd>a network element, in which two priority classes are defined for interface devices, and</dd><dt>FIG. 2</dt><dd>a digital communication system with new network elements.</dd></dl>

p0013In Fig. 1, a network element is shown, for example, part of a according to the standard for synchronous digital hierarchy (SDH) communication system is operating.

p0014In such a digital communication system, the network elements, for example, by copper cables and / or optical waveguide are connected together. The network element as a cross-connect, has a number of interface means S₁, ..., S_x, ..., S_{x + i},

p0015In Fig. 1, six interface devices S₁, S₂, S_x, S_{x + 1}, S_{x + 2}, S_{x + i} drawn; to Verdeutlichtung are three interface devices S₁, S₂, S_x on one side, which is hereinafter referred to as an upper side, of the network element and three interface devices S_{x + 1}, S_{x + 2}, S_{x + i} on an opposite side, which is hereinafter referred to as the lower side.

p0016At each interface device S₁, S₂, S_x the upper side comes to an SSM, the interface devices in accordance with the S₁, S₂, S_x with SSM₁, SSM₂ and SSM_x are designated. From any interface device S₁, S₂, S_x can also be a SSM, for example, are sent out with the message DNU. In Fig. 1, the directions of the SSM by arrows with the corresponding direction to the interface devices S₁, S₂, S_x located.

p0017The network element also has a selection device 1, in which a mode filter is included, a clock generator 6 and control means 7. Any interface device S₁, S₂, S_x is connected via a connection 3, 2, 5 with the selecting means first The selector 1 are characterized clocks south of the interface devices₁, S₂, S_x incoming STM-N signals, respectively. In addition, each interface device S₁, S₂, S_x connected via a connection 8, 9, 10 to the control device. 7 About these compounds 8, 9, 10, the control device 7, respectively, the SSM, the SSM₂, SSM_x supplied. The controller 7 is in turn connected via a control line 12 to the selecting means 1, and via a connection 2 to the clock generator 6 via a connection 4, the selecting means 1 is connected to the clock generator 6th

p0018With the interface means S_{x + 1}, S_{x + 2}, S_{x + i} the lower side is the control device 7 via a connecting thirteenth At an output 14 of the clock generator 6 exits the clock which is communicated to other network elements. For the output 14 is connected to each interface device S₁... S_x... S_{x + i} connected; in FIG. 1 is indicated for simplicity by a drawn at the output 14 arrow.

p0019For the function of each component: The existing in the selector 1 mode filter is specified by the ITU-T Recommendation G.812 or G81s and has to filter out the task Takstörungen (jitter and wander). Another object of the mode filter is to keep the frequency of its output signal in case of failure of its input signal as constant as possible.

p0020The control device 7 evaluates the incoming SSM, the SSM₂, SSM_x and determines therefrom an interface device S₁, S₂, S_x as a clock reference source. The selection device 1 is then controlled by the control device 7, that the clock of the clock reference source is forwarded to the clock generator 6th The clock generator 6 is for example a phase locked loop (PLL), which passes by a synchronization to the coming of the selector 6 clock, this clock via the output 14th If a synchronization of the clock generator 6 is not possible, for example because too much noise accompanies the clock or because the clock has failed, a message is, the clock generator 6 of the controller. 7 Such message causes for example, that the network element goes into a wait state (hold-over). The controller 7 generates a SSM, which corresponds to the current state of the network element. This SSM can be one of the interface devices S₁, S₂, S_x the upper side received SSM₁, SSM₂, SSM_x be. but it may also be a new, generated by the control device 7 SSM.

p0021The interface means S_{x + 1}, S_{x + 2}, S_{x + 1} the lower side give each the selected or generated SSM on; incoming SSM will be ignored. Even at these interface devices S_{x + 1}, S_{x + 2}, S_{x + i} the directions of the SSM are indicated by arrows with the corresponding direction. In this network element are for the interface means S₁, ..., S_x... S_{x + i} two classes (top, bottom) set out below: The interface devices S₁, S₂, S_x the upper side have the class "top" and the interface means S_{x + 1}, S_{x + 2}, S_{x + i} the lower side of the class "bottom". The classes "top, bottom" (abbreviated: bot) are shown in Figure 1 to the interface means S.₁, ..., S_x, ..., S_{x + i} located.

p0022The interface means S₁, S₂, S_x Class "top" represent possible clock reference sources from which one is selected by the controller. 7 That is, with the S interface devices₁, S₂, S_x this class "top" interface means one or more other network elements are connected, the SSM will be accepted in principle for synchronization. The interface means S_{x + 1}, S_{x + 2}, S_{x + i} Class "bottom" ignore incoming SSM as already mentioned, that is arriving from the other network elements SSM is not used for synchronization.

p0023Such network elements described in the preceding a synchronization network can also be created in a non-hierarchical transmission and switching system. It can by setting the classes "top, bottom" to determine an interface device, if the network element must synchronize another network element or not.

p0024In FIG. 2 illustrates an exemplary hierarchical synchronization network with nine network elements NE11 ... NE33 is shown. These network elements NE11 ... NE33 are shown in the form of a grid (3x3 matrix), the grid points representing the idealized geographical locations of network elements NE11 ... NE33 and the grid lines, the cable or radio connections between the network elements. At the network elements NE11, NE13, NE32 a reference clock in the hierarchical synchronization network is fed. The reference clock (the "master clock") generated by a reference clock source, for example, a cesium clock, a clock stability of 10^-11 Has. In Fig. 2, the network elements NE11, NE13, NE32 shown as solid circles and the remaining network elements NE12, NE31 N21 ..., NE33 that have no reference clock source, as open circles. At the individual network elements NE11 ... NE33 classes "top" and "bottom" are indicated.

p0025The network elements NE11, NE13, NE32 have only interface devices with Class "bottom"; of other network elements, they can not be synchronized.

p0026The network element NE21 accepts only one coming from the network element NE11 clock (class "top") and ignored SSM that. Of the network elements NE22, NE31 come (class "bottom")

p0027The other synchronization devices for the individual network elements arising from Fig. 2, thus obviating their explanation at this point.