Method for correcting gray scale data in a self luminous display panel driving system

BACKGROUND OF THE INVENTION

The present invention relates to a method for controlling tones in a self-luminous display such as a plasma display panel and an electroluminescence display panel, and more particularly to a method for preventing false contouring.

There has been known an image display device having a self-luminous display panel such as a plasma display panel and an electroluminescence panel. The plasma display panel utilizes a gas discharge so that the quantity of the light emitted therefrom cannot be continually controlled. Hence the emission is actuated by pulses, that is, the brightness of the image on the display is represented by the number of the pulses, namely, by the frequency of the emission. The image becomes brighter as the number of the emission, or the frequency per unit time increases so that the tone can be controlled.

In order to drive the panel so as to show a picture thereon, each field of a composite video signal is divided into a plurality of sub-fields on time axis. The sub-fields are differently weighted in order to impart a tone to the image on the display. Namely, a digital video signal is reproduced not by a dot sequential scanning of each pixel, but by repeating a plane sequential scanning of the pixel in accordance with the weight of the pixel.

As shown in Fig. 22a, each field is divided into eight sub-fields D₈ to D₁, corresponding to the 8 bits of a pixel data so that, in order to complete a field, a bit plane scanning takes place. The time length of each sub-field is determined in accordance with its weight. The ratio of weights from the first sub-field to the eighth sub-field are, for example, 128(2⁷):64(2⁶):32(2⁵):16(2⁴):8(2³):4(2²):2(2¹):1(2⁰), as shown in Fig. 22b. For example, when the logic value of the eighth position and hence the highest order bit of the pixel data is "1", which indicates the logic for emitting, the light is emitted 128 times during the sub-field D₈. When the logic value of the eighth bit is "0", light is not emitted at all during the sub-field D₈. When the seventh bit of the pixel data is "1", the light is emitted 64 times during the sub-field D₇. When the plane sequential scanning is thus carried out eight times, the light from each pixel is visually recognized by the viewer as a brightness corresponding to the total of the pulses of eight sub-fields. Thus, the tone of 2⁸ (256) steps, from 0 to 255, can be obtained by combining the eight weights.

Fig. 22c shows, as examples, the light emitting periods corresponding to each sub-field of the eight-bit pixel data, "11111111", "10000000", and "00000001".

The above described sub-field system is an excellent system which enables to realize various tones in a single-tone display which is capable of indicating only two tones "1" and "0". However, a false contouring due to visual characteristics inherently occurs in the system. The false contouring is a phenomenon where a flat image, the levels of signals thereof cross the tone levels such as 128, 64, 32 and 16, which are the powers of 2. As a result, contour lines in stripes appear on the display as if the tones of the image are lost. The phenomenon becomes strikingly apparent when an image of a flat mass moves on the display and is hardly recognized when the image is stationary, that is when a still picture stored in a memory is shown. Namely, the false contours are recognized only when an image moves about level boundaries. In addition, when a load of a still visual signal fluctuates due to a noise included therein, the false contours also appear.

The cause of the false contouring is described with reference to Figs. 23a, 23b, 24a, 24b, 24c and 24d. As shown in Fig. 23a, when the tone is decreased so that the number of pulses decreases from 128 to 127 in the next field, the emission at the sub-field D₈ is stopped and the emission at the sub-fields D₇ to D₁ is started. The difference in the levels of the tone corresponds to 1 least significant bit (LSB). In such a case, a transition period t₁ where the emission of light does not occur is so long that the viewer senses it as though the tone is decreased, although momentarily. As a result, there are formed on the display, stripes similar to isobaric curves in a weather map. Although the tone of each pixel is decreased only one step, since the stripes move with the movement of the image, they become apparent to the viewer.

Fig. 23b shows a case where bright contour lines are formed. When the number of pulses is increased from 127 to 128, emission at the sub-fields D₇ to D₁ is stopped and emission at the sub-field D₈ is started. A transition period t₂ is so short that the luminous density is increased. Hence a bright stripe appears on the display.

There are displays where the sub-field are arranged starting from the sub-field with a smallest weight as shown in Figs. 24a to 24d. Each space before the sub-fields indicates a constant non-light emitting period for selecting the next sub-field at which the light is emitted. The spaces are omitted in Figs. 23a and 23b for the sake of simplicity.

As shown in Fig. 24a when a pixel data is "11111111", corresponding to 255 pulses, the light is flashed during all of the sub-fields. When the pixel data is "10000000", corresponding to 128 pulses, the light is emitted only during the sub-field D₈ (Fig. 24b). Fig. 24c shows an example where the data is "01111111" corresponding to 127 pulses, so that the light is emitted at sub-fields D₁ to D₇. When the data changes to "10000000", a transition period t₅ shown in Fig. 24d becomes much longer than periods t₃ and t₄ which are shown respectively in Figs. 24b and 24c. As a result, dark stripes appear on the display. To the contrary, when the data changes from "10000000" to "01111111", the non-light emitting period becomes short so that bright stripes appear.

In order to restrain the false contouring, Japanese Patent Application Laid-Open Nos. 2-291597, 3-145691 and 4-211294 propose to change the arrangement of the sub-fields. For example, the emitting period for a sub-field corresponding to the most significant bit (MSB) of the pixel data is positioned between those of the lower bits so that the difference in luminance, particularly that of the sub-field of the MSB is decreased. However, experiments have shown that the false contours are observed in the lower bit levels.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for correcting pixel data in a self-luminous display panel driving system, where the false contouring is prevented.

According to the present invention, there is provided a method for correcting pixel data in a self-luminous display panel driving system, wherein one field of a composite video signal is divided into N sub-fields, luminance of each pixel is set by a pixel data comprising N bits corresponding to the number of the sub-field and each of digit positions of the N bits represents a weight for the luminance.

The method comprising steps of comparing a present pixel data of a pixel with a prior pixel data of a same pixel, detecting whether there is a change between a data of a highest luminance and a data of a luminance of a one digit lower in the comparison, and producing an inter-frame change signal when a change is detected, correcting the present pixel data in response to the inter-frame change signal so as to change the sub-field of the present pixel data.

In a method, the correcting data is performed so as to reduce a period between sub-fields of the prior pixel data and the present pixel data.

In another method, the correcting data is performed so as to increase a period between sub-fields of the prior pixel data and the present pixel data.

The other objects and features of this invention will become understood from the following description with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

<ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1 is a block diagram showing a self-luminous display panel and a control system thereof according to the present invention;</li><li>Fig. 2 is a block diagram of a correcting circuit provided in the control system of Fig. 1;</li><li>Fig. 3 is a table showing correcting data for correcting pixel data in the correcting circuit of Fig. 2;</li><li>Figs. 4a to 4c are charts explaining the correcting operation;</li><li>Fig. 5 is a chart explaining emission at sub-fields within one frame and the corresponding visual response;</li><li>Fig. 6 is a chart explaining the emission at sub-fields within three consecutive frames and the corresponding visual response according to the present invention;</li><li>Fig. 7 is a chart showing the visual response when a false contouring occurs;</li><li>Fig. 8 is a chart showing the visual response when the false contouring is prevented;</li><li>Fig. 9 is a chart showing another arrangement of the sub-fields;</li><li>Fig. 10 is a circuitry showing a second embodiment of the correcting circuit provided in the control system of Fig. 1;</li><li>Fig. 11 is a circuitry showing a device provided in the correcting circuit of Fig. 10;</li><li>Fig. 12a is a block diagram showing another device provided in the correcting circuit of Fig. 10;</li><li>Fig. 12b shows a matrix of pixels for explaining the operation of the device of Fig. 12a;</li><li>Fig. 13 is a block diagram showing another example of the device shown in Fig. 12a;</li><li>Fig. 14a is a diagram showing another device provided in the correcting circuit of Fig. 10;</li><li>Fig. 14b shows a matrix of pixels for explaining the operation of the device of Fig. 14a;</li><li>Figs. 15a to 15d and 16 to 20 are illustrations explaining the operation of the second embodiment;</li><li>Fig. 21 is a circuitry showing another example of the correcting circuit of Fig. 10;</li><li>Fig. 22a is an illustration showing sub-field of a pixel;</li><li>Fig. 22b is a table showing each sub-fields and the corresponding light-emitting number of times;</li><li>Fig. 22c shows charts explaining the light-emitting period of the sub-fields;</li><li>Figs. 23a and 23b are charts showing the light-emitting periods in a conventional system which cause false contouring; and</li><li>Figs. 24a to 24d show the light-emitting periods in a conventional system having other arrangements of the sub-fields.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to Fig. 1, a self-luminous display device of the present invention such as a plasma display device comprises a video signal processing circuit 1 where a composite video signal is applied. The video signal processing circuit 1 extracts from the composite video signal, R video signal corresponding to a red video component, G video signal corresponding to a green video component and B video signal corresponding to a blue video component. The R, G and B video signals are applied to an A/D converter 3. The composite video signal is further applied to a sync signal separation circuit 5 which operates to extract horizontal and vertical synchronizing signals from the input composite video signal. The horizontal and vertical synchronizing signals are applied to a timing pulse generating circuit 6 which produces various timing pulses based on the synchronizing signals. The timing pulses are applied to the A/D converter 3 which is operated in synchronism with the timing pulse, so as to convert the R video signal, G video signal and B video signal into pixel data signal for each pixel provided in a display panel 12. Each pixel data in the present invention is an 8-bit pixel data, the eight digits of which corresponds to the number of sub-fields. The pixel data signal is corrected by a data correcting circuit 7, which will later be described in detail, and fed to a frame memory 8. The timing pulse from the timing pulse generating circuit 6 is also fed to the data correcting circuit 7.

The timing pulses is further applied to a data control circuit 9 and a read out timing pulse generating circuit 20. The memory control circuit 9 produces writing pulses and reading pulses corresponding to the timing pulse from the timing pulse generating circuit 6 and applies the pulse to the frame memory 8. The frame memory 8 stores the pixel data from the A/D converter 3 in order in accordance with the matrix of the panel in response to each writing pulse, and reads the pixel data for applying the data to an output processing circuit 10 in response to the reading pulse.

The output processing circuit 10 is operated to send the data voltages of 8 digits to a data electrode driver 13 of the display panel 12. The electrode driver 13 applies a high data voltage (1) or a low data voltage (0) for every digit of the pixel data dependent on the pixel data to designated data electrodes D₁, D₂, D₃ ... D_m-1, and D_m at a corresponding timing.

The read out timing pulse generating circuit 20 produces a scanning pulse for starting a discharge for emitting light, sustaining pulse for sustaining the emitting of the light and an erasing pulse for stopping the discharge and erasing the light. The scanning, sustaining and erasing pulses are applied to a row electrode driver 11 of the display panel 12.

The display panel 12 comprises data electrodes D₁, D₂, D₃ ... D_m-1 and D_m, odd row electrodes X₁, X₂, X₃ .., X_n-1 and X_n, and even row electrodes Y₁, Y₂, Y₃ ... Y_n-1, and Y_n for performing interlaced scanning. Each of the data electrodes intersects each of the odd and even row electrodes to form a pixel. The data electrode driver 13 is connected to the data electrodes for driving the electrodes. The row electrode driver 11 is connected to the row electrodes X₁, X₂ ... X_n and Y₁, Y₂ ... Y_n. Such a plasma display device is well-known so that a further description thereof is omitted.

Referring to Fig. 2, the data correcting circuit 7 has a pixel data first memory 30 wherein pixel data for each pixel from the A/D converter 3 is fed. The data is an 8-bit data which is expressed as "d₈, d₇, ... d₁". Namely, each bit is expressed as d_n (n = 1 to 8 ) where n indicates the position. The luminance of the bit increases as the number n becomes larger. The data stored in the memory 30 is further applied to a pixel data second memory 32 through a one-frame delay circuit 31. Accordingly, the pixel data second memory 32 always stores a pixel data of one frame before that of the pixel data first memory 30.

The present pixel data stored in the pixel data first memory 30 is fed to a high-order four bits detecting circuits 33₁ to 33₆ and the last pixel data stored in the pixel data second memory 32 is fed to high-order four bits detecting circuits 34₁ to 34₆. The high-order four bits detecting circuits 33₃ to 33₅ and 34₃ to 34₅ to 33₅ are omitted in the figure. Each of the four bits detecting circuits 33₁ to 33₆ and 34₁ to 34₆ is provided with a present data which are shown in the following table. <tables id="tabl0001" num="0001"><table frame="all"><title>TABLE</title><tgroup cols="4" colsep="1" rowsep="1"><colspec colnum="1" colname="col1" colwidth="39.37mm" /><colspec colnum="2" colname="col2" colwidth="39.37mm" /><colspec colnum="3" colname="col3" colwidth="39.37mm" /><colspec colnum="4" colname="col4" colwidth="39.37mm" /><thead valign="top"><row><entry namest="col1" nameend="col1" align="center">DETECTING CIRCUIT</entry><entry namest="col2" nameend="col2" align="center">PRESET DATA</entry><entry namest="col3" nameend="col3" align="center">DETECTING CIRCUIT</entry><entry namest="col4" nameend="col4" align="center">PRESET DATA</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="right">33₁</entry><entry namest="col2" nameend="col2" align="right">1000</entry><entry namest="col3" nameend="col3" align="right">43₁</entry><entry namest="col4" nameend="col4" align="right">0111</entry></row><row><entry namest="col1" nameend="col1" align="right">33₂</entry><entry namest="col2" nameend="col2" align="right">0100</entry><entry namest="col3" nameend="col3" align="right">43₂</entry><entry namest="col4" nameend="col4" align="right">0011</entry></row><row><entry namest="col1" nameend="col1" align="right">33₃</entry><entry namest="col2" nameend="col2" align="right">0010</entry><entry namest="col3" nameend="col3" align="right">43₃</entry><entry namest="col4" nameend="col4" align="right">0001</entry></row><row><entry namest="col1" nameend="col1" align="right">33₄</entry><entry namest="col2" nameend="col2" align="right">0111</entry><entry namest="col3" nameend="col3" align="right">43₄</entry><entry namest="col4" nameend="col4" align="right">1000</entry></row><row><entry namest="col1" nameend="col1" align="right">33₅</entry><entry namest="col2" nameend="col2" align="right">0011</entry><entry namest="col3" nameend="col3" align="right">43₅</entry><entry namest="col4" nameend="col4" align="right">0100</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="right">33₆</entry><entry namest="col2" nameend="col2" align="right">0001</entry><entry namest="col3" nameend="col3" align="right">43₆</entry><entry namest="col4" nameend="col4" align="right">0010</entry></row></tbody></tgroup></table></tables>

The high-order four bits detecting circuits 33₁ and 34₁ are connected to input terminals of an AND gate 35₁. Similarly, AND gates 35₂ to 35₆ to which output signals of the high-order four bits detecting circuits 33₂ to 34₆ and 34₂ to 34₆ are respectively fed are provided. Namely, when the high-order four bits of the present pixel data fed from the pixel data first memory 30 coincides with the preset data in any of the detecting circuits 33₁ to 33₆, the circuit applies a high level voltage to the corresponding AND gate. When the high-order four bits of the last pixel data fed from the pixel data second memory 32 coincides with the preset data in any of the detecting circuits 34₁ to 34₆, the circuit applies a high level voltage to the corresponding AND gate. For example, when the high-order four bits of the present pixel data is "1000" and high-order four bits of the last pixel data is "0111", the AND gate 35₁ are fed with high level input signals from the high-order four bit detecting circuits 33₁ and 34₁, thereby producing a high level output signal.

Each of the high-order four bits detecting circuits 33₁ to 33₆ and 34₁ to 34₆ actually comprises four exclusive OR gates to which exclusive OR results of respective bit values of high-order four bits of the pixel data and the preset data are fed, and four NOR gates connected to the exclusive OR gates.

The high level output signals from the AND gates 35₁ to 35₆ are applied to an addition and subtraction circuit 36 to which the present pixel data from the pixel data first memory 30 is also fed through a delay circuit 37. The addition and subtraction circuit 36 adds to or subtracts from the present pixel data to produce a correcting data predetermined in accordance with the AND gate from which the high level output signal is fed. The delay time set in the delay circuit 37 is so determined as to compensate the time it took for the detecting circuits 33₁ to 33₆ and 34₁ to 34₆ and the AND gates 35₁ to 35₆ to operate.

The correcting data for each of changing patterns of the pixel data between the frames is shown in the table of Fig. 3. Patterns A₁ to C₂ show cases where the arrangement of sub-fields begins with the most weighted sub-field D₈ and ends with the least weighted sub-field D₁ as shown in Fig. 23a, and patterns A₃ to C₄ show cases where the arrangement begins with the least weighted sub-field D₁ and ends with the most weighted sub-field D₈ as shown in Fig. 24a. As shown in Fig. 3, the manner in which false contour appears and whether to increase or decrease the luminance to correct the data in the patterns A₁ to C₂ are changed in the patterns A₃ to C₄.

In the changing pattern A₁, the pixel data, for example, changes from "10000000" in a frame (n-1) to "01111111" in a frame (n). The false contours appear as a dark stripe. In order to prevent the false contour, correcting data "00000001 + a₁" which is "00100000" is added to the pixel data "01111111". As a result, the present pixel data "01111111" is corrected to "10011111".

The high-order four bits detecting circuits 33₁ and 34₁ detect the changing patterns A₂ and A₄, and the high-order four bits detecting circuits 33₂ and 34₂ detect the patterns B₂ and B₄. Similarly, other patterns are determined by the pairs of detectors 33₃ and 34₃, 33₄ and 34₄ and so on. Namely, the addition and subtraction circuit 36 has a memory storing the correcting data shown in Fig. 3 and corrects the present pixel data, depending on how the sub-field D₈ to D₁ are arranged, in accordance with the changing pattern. Alternatively, the memory in the addition and subtraction circuit 36 may store the calculated corrected pixel data so that when any of the changing patterns A₁ to C₄ is detected, the corrected pixel data is read out to replace the present data without calculating the corrected data.

As can be seen from the table, in the instances where the sub-fields are arranged in the order from the sub-field with the largest weight as in the changing patterns A₁ to C₂, when the highest bit having the high data voltage (1) in the frame (n-1) changes to the bit of the next lower order in the frame (n) as in patterns A₁ to C₁, the pixel data is corrected by addition. On the other hand, when the highest bit with the high data voltage changes to the bit of the next higher order as in patterns A₂ to C₂, the pixel data is corrected by subtraction. Hence the highest bit having the high data voltage of the corrected data becomes the same as that of the data of the previous frame (n-1). For example, in the changing pattern A₁, the present pixel data "01111111" of the frame (n) wherein the highest bit is d₇, is corrected to "10011111" wherein the highest bit is d₈, which is the same bit as the highest bit in the data of last frame (n-1).

When the sub-field are arranged in the order from the sub-field with the least weight as in the changing patterns A₃ to C₄, when the highest bit having the high data voltage in the frame (n-1) changes to the bit of the next lower order in the frame (n) as in patterns A₃ to C₃, the pixel data is corrected by subtraction. On the other hand, when the highest bit with the high data voltage changes to the bit of the next higher order as in patterns A₄ to C₄, the pixel data is corrected by addition. The low-order bits of the resultant corrected data are changes of the low-order bits of the present data. For example, in the changing pattern A₃, the present pixel data of the frame (n) is "01111111" and the corrected data is "01100000". The low-order five bits of the corrected data are the changes of those of the present pixel data. In the pattern B₃, the data of the present frame (n) "00111111" is replaced by the corrected data "01100000". Namely, the low-order four bits "0000" of the corrected data are change of "1111" which coincides with the low-order four bits of the present data before correction.

Each of the correcting values a₁ to a₄, b₁ to b₄, and c₁ to c₄ is smaller than one half of the data of the last frame (n-1).

The entire correcting circuit 7, or at least the addition and subtraction circuit 36 may be formed as a microprocessor.

The operation of the correcting circuit is described hereinafter with reference to Figs. 4a to 4c.

Fig. 4a shows an example where the pixel data changes during a period of a frame (n-2) to a frame (n+1), from "10000000", "10000000", "01111111", to "01111111". Chart (1) shows the sub-fields during which the light is emitted when the data is not corrected and chart (2) shows the sub-fields when the data is corrected. In the chart (1), since the length of time between the sub-field D₈, which corresponds to the highest light emitting bit, in the frame (n-1) and the sub-fields D₇ to D₁ in the frame (n) is long as shown between arrows, the non-emitting period becomes longer than the non-emitting periods between the frames (n-2) and (n-1) and between (n) and (n+1). Hence false contours in the form of dark stripes appear due to the persistence.

In order to prevent the false contouring, the data "01111111" of the data for the frame (n) is replaced by a value "10000000 + a₁" wherein the value a₁ is a data such as "11111111" which corresponds to the data where the light is emitted at sub-fields D₆ to D₁. Hence light is emitted at the sub-fields D₈ and D₆ to D₁ as shown in the chart (2). The non-emitting period is thus shortened so that stripes do not appear on the display.

Referring to Fig. 4b, when the pixel data changes from "01111111", "01111111", "10000000" to "10000000" during the frames (n-2) to (n+1), the light is emitted at the sub-fields D₇ to D₁ in the frames (n-2) and (n-1) and at sub-field D₈ in the frames (n) and (n+1). Thus, the non-emitting period between the frames (n-1) and (n) becomes extremely shorter compared to those between other frames shown in the chart (1), thereby producing a bright false contour. When the correcting data "a₂ + 1" is subtracted from the data of the frame (n), the corrected data for the frame (n) becomes "01111111 - a₂", which corresponds to the emitting periods of the sub-fields (D₇ to D₁) - a₂. Hence the emitting periods in the frames (n-1) and (n) are separated from one another as shown in the chart (2), so that the bright false contour is prevented.

In Fig. 4c, the pixel data changes from "01000000", "01000000", "00111111" to "00111111" during the frames (n-2) to (n+1). Namely, the light emitting periods change from the sub-field D₇ to sub-fields D₆ to D₁ between the frames (n-1) and (n). The non-emitting period shown between the arrows in the chart (1) is so long that dark stripes are shown. However, when the correcting data (b₁ + 1) is added to the pixel data "00111111" for the frame (n), the corrected data becomes "01000000 + b₁". Hence the light is emitted for a period of the sub-field D₇ and a sub-field corresponding to the data b₁ as shown in chart (2). The non-emitting period is accordingly shortened, thereby preventing the dark stripes.

As can be seen from the examples, the value of the correcting data a₁ to b₁ varies in accordance with the position of the highest bit having the high data voltage. Namely, the value a₁, which is a correcting value when the highest bit is the highest-order bit d₈, is larger than the value b₁, which is a correcting value when the highest bit is the next highest bit d₇. In other words, it is preferable to set the correcting value to increase as the position of the highest bit of the data becomes higher.

Although the experiments carried out by the inventors of the present invention have shown that the false contouring can be effectively prevented by detecting the high-order four bits of the pixel data, the present embodiment may be modified so as to detect the high-order three bits or the high-order five bits to predict the occurrence of the false contouring.

The change in the position of the highest bit having the high data voltage can be detected through a program executed by a microprocessor.

Although the present pixel data is compared with that of one frame before in the present embodiment, it may be compared with the data of two or three frames before. Moreover, the number of sub-fields, and hence the number of the bits need not be confined to eight, but be a natural number as appropriate.

There has been observed some cases where the false contouring occurs even after the pixel data are corrected as described above. As shown in Fig. 5, when the pixel data having eight bits d₁ to d₈ of a frame is "11111111", the light is emitted during all sub-fields D₈ to D₁. Each sub-field comprises a non-emitting period Wc for writing the pixel data, and a light-emitting period shown by hatchings. As the emitting period becomes longer, the viewer senses that the luminance is increased so that visual response S is increased. To the contrary, during each non-emitting period, the sense of luminance decreases so that the visual response S declines.

Fig. 6 shows the visual response S in the case of Fig. 4a where the data changes from "10000000" to "01111111" and corrected in accordance with the changing pattern A₁ of Fig. 3 so that the corrected pixel data in the frame (n) is "10011111". Namely, since in the frame (n-1), the light is emitted for only a period of the sub-field D₈ as shown in the chart (2) of Fig. 4a, a visual response S(n-1) gradually rises during the sub-field D₈ and then declines. In the next frame (n), the light is emitted during the sub-field D₈ and during the sub-fields D₅ to D₁, thereby causing a visual response S(n) to rise during the sub-field D₈ and to repeat the risings and declinings thereafter. In the frame (n+1), the light is emitted during the period of sub-fields D₇ to D₁, a visual response S (n+1) changes as shown in the figure.

It has been known that the persistence of the emission in the last frame affects the emission in the present frame. As shown in Fig. 7, in the frame (n+1), the persistence of the visual response S(n) of the last frame is overlapped with the present visual response S(n+1). After a period t₆ from the start of the frame (n+1), the two responses intersect at a point P1, that is the same luminance is sensed, although one of the responses is headed upward, and the other downward.

The false contouring is observed in such a circumstance. However, the false contouring can be prevented by forcing the attenuating slope of the visual response S(n+1) in the frame (n+1) to coincide with that of the visual response S(n) in the last frame (n) as shown in Fig. 8.

In order to control the visual response, the non-emitting period Wc is corrected. Namely, a non-emitting period Wc₁ of the sub-field D₇ is rendered shorter than the normal non-emitting period Wc, whereas a non-emitting period Wc₂ of each of the sub-fields D₆ and D₅ is rendered longer. The non-emitting period of other sub-fields may be corrected in order to attain the same result. The same correcting method can be applied to a device where the sub-fields are arranged to start from those of the smaller weight as shown in Fig. 9.

The false contouring can be sufficiently prevented in the above described embodiment if the display is showing a still picture, or the speed at which an image on the display moves is relatively low. However, when the image quickly moves a dark portion generates in a boundary between adjacent sub-fields of "100" and "011". Thus the false contouring appears in a different manner than it would in a still picture.

More particularly, the intensity of the moving false contours varies in accordance with the moving speed of the image. In addition intensity varies within the false contours depending on the moving direction thereof. When the moving speed of the image is faster than one pixel per frame, the bright or the dark stripe becomes more intense than the still false contour. The intensity increases with the increase of the speed.

The second embodiment of the present invention is intended to prevent such a moving false contour.

Referring to Fig. 10, the correcting circuit 7 has a one-frame delay circuit 21 to which the present pixel data from the A/D converter 3 of Fig. 1, designated A in the figure, is fed. The one-frame delay circuit 21 comprises a RAM for storing the present pixel data A and a pixel data B of one frame before, and a read/write control circuit for reading the last pixel data B from an address in the RAM and writing the present pixel data A at the address as the last pixel data. The pixel data A and B are applied to an inter-frame change detecting circuit 22.

Referring to Fig. 11, the inter-frame change detecting circuit 22 comprises three exclusive OR gates 22a to which the values "1", "0", and "0" are respectively fed. The high-order three bits of the present pixel data A are also fed to the exclusive OR gates so as to be compared with the respective values. Namely, when the high-order three bits of the pixel data A is "100", each of the exclusive OR gates 22a produces a low level output. The outputs are applied to a NOR gate 22b which accordingly produces a high level output. Similarly, the high-order three bits of the last pixel data B are compared with values "0", "1" and "1" by three exclusive OR gates 22c, each of which produces a low level output when the three bits are "011". The low level outputs of the exclusive OR grates 22c are applied to a NOR gate 22d which produces a high level output.

The high level outputs of the NOR gates 22b and 22d are applied to an AND gate 22e which produces a high level output as an increasing signal LH. That is to say, the inter-frame change detecting circuit 22 detects that the values of the MSB and the following two bits are changed, so as to increase luminance.

The inter-frame change detecting circuit 22 is further provided with means for detecting the decrease of the luminance comprising three exclusive OR gates 22f and a NOR gate 22g, three exclusive OR gates 22h and a NOR gate 22i, and an AND gate 22j. When the exclusive OR gates 22f detect that the high-order three bits of the present pixel data A is "011", the NOR gate 22g produces a high level output which is applied to the AND gate 22j. When the exclusive OR gates 22h detect that the high-order three bits of the last pixel data B is "100", the NOR gate 22i applies a high level output to the AND gate 22j. Thus, the AND gate produces a high level output as a decreasing signal HL.

Namely, the inter-frame change detecting circuit 22 detects that the value of MBT and those of the two following lower bits in the last frame are each changed from the last frame in the present frame.

As shown by the dash-dot lines and dash-two-dot lines in Figs. 10 and 11, there are further provided two other inter-frame change detecting circuits which determine the changes of values of the second and third highest order bits, for example, from "010" to "001". The inter-frame change detecting circuit 22 may be adapted to detect the change of data in high-order two bits and high-order four bits. The circuit may also be modified to detect the change such as "10******" to "01******", and from "01******" to "10******" so as to expand the detecting range, thereby improving the effect of the correction. The detecting range is also expanded when the changes such as from "1*******" to "0*******", from "01******" to "00******", and from "001*****" to "000*****" are detected.

Referring back to Fig. 10, the decreasing signal HL and the increasing signal LH are fed to a changing speed detecting circuit 23.

As shown in Fig. 12a, the changing speed detecting circuit 23 comprise serially connected one-frame delay circuit 23a for eight horizontal pixels, an 8-bit shift register 23b and 8-clock delay circuits 23c for eight vertical pixels, each receiving an output of corresponding one-frame delay circuit 23a. When the decreasing signal HL or the increasing signal LH is applied, the changing speed detecting circuit 23 looks up the pixels in a matrix of nine rows by nine columns including the present pixel shown in hatchings at the center thereof as shown in Fig. 12b. Namely, the changing speed detecting circuit 23 calculates the number of pixels where the bit of the highest order having the high data voltage had changed. Each of the one-frame delay circuits 23a stores the data on pixels in one of the rows.

It is preferable to provide two sets of the delay circuits 23a and 23c for each of the decreasing signal and the increasing signal. However, such an additional device improves an increase of the circuitry and a decrease in calculating speed. Hence, in the present embodiment, a preprocessing circuit 23d connected to the first delay circuit 23a is provided as shown in Fig. 13. The preprocessing circuit 23d is applied with the decreasing signal HL or the increasing signal LH. When the bit having the high data voltage moves to a lower position, -1 is stored in the first delay circuit 23a. On the other hand, when the bit moves to a higher position, +1 is stored. When the position of the bit does not change, -1 and +1 are alternatively stored. In the next row, the storing order of the values -1 and +1 for the unchanging pixels is changed.

The delay circuits 23a are connected to respective adders 23e, each of which adds the values stored in each delay circuit. The values stored in the delay circuits 23c are added at adders 23f. The total of the values in the delay circuit 23c added at the adders 23f are subtracted from the total of the delay circuit 23b at a subtracter 23h to obtain the number of the pixels which have changed. The number of the pixels is stored in a latch 23i and further applied to an adder 23g to be added to the total of the adders 23e. Hence, the number of pixels in the front portion of the matrix of nine by nine is added and the number of the pixels in the rear portion is subtracted.

The changing speed detecting circuit 23 thus calculates a value C representing the number of the pixels the data of which have changed and the manner of the change in the nine by nine matrix. Thus, the speed of the false contour is detected. Although the value may include small errors, it approximately indicates the changing speed.

As shown in Fig. 10, the calculated value C is fed to a correcting data calculator 24 having a ROM storing a plurality of correcting data D. The data D is set to increase as the value C increases as shown in a graph in Fig. 10. However, when the number of the changing pixels exceeds a predetermined value, for example, 45 which is more than the half of all the pixels in the nine by nine matrix, the detected value C is considered as an error so that the correcting data D is decreased.

The pixel data A is further applied to an in-space change detecting circuit 25 in Fig. 10. The detecting circuit 25 compares the data A with those of eight adjacent pixels in a three by three matrix as shown in Fig. 14b.

Referring to Fig. 14a, the in-space change detecting circuit 25 has a comparator 25a for comparing the pixel data A with the data "10000000", a first delay circuit 25b, second delay circuit 25c, and third delay circuit 25d. In each of the delay circuits, the reference D represents a one-clock delay circuit, and H represents a one-frame delay circuit. Thus, the first to third delay circuits 25b, 25c and 25d produce pixel data <u>a</u> to h of the matrix of Fig. 14b.

The in-space detecting circuit 25 has a comparator 25f for comparing the present pixel 25e with the eight pixels <u>a</u> to h in the three by three matrix. When the present pixel 25e differs from any one of the eight pixels, the comparator 25f produces a change detecting signal E.

The present pixel may be compared with four pixel disposed above, below, right and left thereof. The pixels the data of which is compared with the present data may be determined in accordance with an existing noise component, thereby increasing the accuracy of the detection. Furthermore, a movement detecting circuit for detecting the direction of the movement may be provided so that the pixels in the moving direction is compared with the present pixel, thereby further increasing the detecting accuracy.

The change detecting signal E is applied to a false contouring detecting circuit 26 (Fig. 10). The determining circuit 26 is provided with an OR gate 26a to which the increasing signal LH and the decreasing signal HL are fed. The output of the OR gate 26a and the detecting signal E are applied to the input terminals of an AND gate 26b. Thus, the AND gate 26b produces a high level output as a false contouring detecting signal F when the pixel data have changed and the data differs from those of the surrounding pixels.

The false contouring detecting signal F is applied to a changeover circuit 27 having a switch 27a to close the switch. Thus, the correcting data D obtained at the correcting data calculator 24 is accordingly applied to an addition and subtraction circuit 28 to which the pixel data A is fed. The pixel data A is corrected by the correcting data D so that a corrected data G is obtained. Namely, the data is corrected only when the false contouring is anticipated.

The correcting data calculator 24 may be modified to provide a ROM wherein the corrected data G in accordance with the changing speed C are stored, thereby obviating the addition and subtraction circuit 28.

As shown by the dash-dot lines and dash-two-dot lines, each of the changing speed detecting circuit 23, correcting data calculator 24, in-space change detecting circuit 25, false contouring detecting circuit 26 and the changeover circuit 27 and the addition and subtraction circuit 28 are provided in three to correspond to the respective inter-frame change detecting circuits 22.

Although descriptions are omitted, various delay circuits are provided in the correcting circuit 7 so that data of the same pixel is processed in each device at one time.

The operation of the present embodiment will be described hereinafter with reference Figs. 15 to 19. Fig. 16 shows a still image. The abscissa represents the space (pixel) and the ordinate shows time (frame). In figures, only the sub-fields corresponding to high-order four bits are shown. The image radiates at 0111 in the left side portion and at 1000 in the right side portion. The non-radiating-portion between rows of pixels is the addressing period.

Figs. 15a to 15d show movement of an image where a circular image moves from the right to the left in the display.

Fig. 17 shows the movement of the bright portion of "100" to the left together with the movement of an image, at a speed of three pixels per frame during the frames F(n) to F(n+₃).

In such a case, a dark line generates in a boundary between sub-fields "100" and "011", where the luminance rapidly decreases in the directions of the arrows. This is the false contour caused by the movement of the image.

Fig. 18 shows an example of correcting method in order to prevent the occurrence of the false contouring.

When the pixel data A is corrected to the data G in accordance with the present embodiment, correcting data, that is correcting sub-fields are added at the pixels in the boundary shown by the arrow in each frame. Thus, vacant pockets in each frame are filled with the sub-fields, thereby preventing the false contouring.

Referring to Fig. 19, when the image moves to the right from "0111" to "1000", false contouring in the form of bright stripes occurs in the boundary as shown by the arrow. The sub-fields are subtracted from the pixels as shown by the arrows in Fig. 19.

Although the present embodiment has been described with respect to the display device wherein the sub-fields are started with the least weighted sub-fields, the sub-fields may be arranged starting with the most weighted sub-field, or arranged in other orders.

When the moving speed is high, sub-fields are further added to the adjacent pixels as shown by the arrows in Fig. 20.

Fig. 21 shows another example of the control circuit 7 of the present embodiment for preventing the false contouring at a higher moving speed of the image.

The control circuit 7, in addition to the devices shown in Fig. 10, is further provided with a second correcting data calculator 41, second false contouring detecting circuit 42 incorporating a second in-space change detecting circuit 43, second changeover circuit 44, and a second addition and subtraction circuit 45.

The second correcting data calculator 41 is applied with the value C obtained in the changing speed detecting circuit 23. The calculator 41 is provided with a ROM which stores a plurality of correcting data D' in accordance with the value C. As shown by the graph in Fig. 21, the correcting data D' is zero when the moving speed is low and increases with the increase of the moving speed. Hence the correcting data D' is obtained only when the moving speed is larger than a predetermined value.

An in-space change detecting signal E' from the OR gate 26a for determining the decrease or the increase of the pixel data of the false contouring detecting circuit 26 is applied to the second change detecting circuit 43. The second change detecting circuit 43 has a one-clock delay circuit, and comparator for comparing the present pixel with the eight pixels in the three by three matrix. Thus pixels subjected to change are determined.

The output signal of the second change detecting circuit 43 is applied to a NOR gate 42a of the second false contouring detecting circuit 42. The NOR gate 42a is further applied with the change detecting signal E from the in-space change detecting circuit 25 fed through an inverter 42b. Thus, when the present pixel is the pixel adjacent to the pixel which forms the front edge of a moving false contour, a second false contouring detecting signal F' is produced.

The second false contouring detecting signal F' is applied to the second changeover circuit 44 to close a switch provided therein. Hence the second correcting data D' is applied to the second addition and subtraction circuit 45 where the pixel data A is corrected by the correcting data D' to obtain a corrected data G'. The corrected data G' is applied to the addition and subtraction circuit 28 so as to be further corrected by the correcting data D. Fig. 20 shows the correcting data D and D'.

Although the pixels in nine by nine matrix were monitored to determine the changing speed in the present embodiment, it is necessary to monitor a larger range when the moving speed becomes high.

From the foregoing it will be understood that the present invention provides a self-luminous display device wherein the false contouring is prevented although the cause thereof may vary.

While the presently preferred embodiments of the present invention have been shown and described, it is to be understood that these disclosures are for the purpose of illustration and that various changes and modifications may be made without departing from the scope of the invention as set forth in the appended claims.