Arrangement and method for handling data structures during their flow through a network node.

p0001The invention relates to an arrangement and a method for processing an ATM cell containing binary data structure in their passage through a node of a communication network, with an input interface, a reading device for reading at least one cell portion, a writing device for writing at least one cell portion and an output interface.

p0002An ATM (Asynchronous Transfer Mode) layer is used to transport short information packets called ATM cells from a transmitting station to their destination station. Known ATM cells are packets of fixed lengths and have a header (header) and a subsequent information field on (Jean-Yves Le Boudec in the article "The Asynchronous Transfer Mode: a tutorial" in Computer Networks and ISDN Systems 24 (1992), SS 279-309). The total length of the cells is in each case 53 bytes, wherein the head part (header) of 5 bytes contain 48 bytes and an information field. The cell-route information contained in the header part is a label and no explicit address because of the fixed and small cell size. When a switching unit (hereinafter referred to as nodes) an incoming cell with the directions label m reading at an input port, it is determined from a route switching table an output port j and a label n. The cell is then written j on the output port and is replaced by the new label n. from the new label n the next switching unit extracts corresponding information etc .. the route switching tables must be set in advance or dynamically allocated. The transport of all the cells takes place over a connection.

p0003There is also already known. Translators (translator), who carry out the pure head translation in the ATM layer and in addition will be able to attach a route information for switching the individual packets of information to the ATM cell.

p0004In the known ATM systems, there are, in principle, no fixed definition of a data rate, but only the specification of a maximum data rate to a connecting line. The data rate of a particular compound on such a line is defined as the number of cells per unit time. There is no frame structure on such a line so that an allocation of cells to a compound for a fixed time raster is not possible. The header data must therefore be re-processed from cell to cell, and it is impossible to predict when the next cell arrives for an existing connection.

p0005The invention is based, to expand the application possibilities of an ATM system significantly the task. In particular, the possibility should be created, to be able to extract and insert data in the transport of information packets through an ATM layer.

p0006This object is achieved according to the invention in that the reading device is assigned a first mask means for selectively reading all information sections of the processed data structure, including initial and / or secondary and / or parallel Spann and information field of the ATM cell and that the writing device, a second mask means for selectively writing the ATM cell is assigned to the binary data structure in their information field and header field and / or in at least one of the first, last, or parallel span.

p0007The inventive method for processing a one ATM cell containing binary data structure in their passage through a node of a communications network is characterized,<ul><li>a) that a data structure with at least one additional information section as bias and / or credits and / or parallel clamping is used, the initial and / or secondary and / or parallel Spann selectively adjustable (programmable) / are; </li><li>b) that the information and / or header of the ATM cell and / or at least one of the first, last, or parallel margin is read selectively via a first mask means; and</li><li>c) is that at least selectively described as a function of the read operation according to step b) of the group consisting of information field, the cell head, header, trailer and parallel clamping portions of information via a second mask means and / or removed.</li></ul>

p0008The switching nodes are configured such that any data on the first mask device selectively in bits, bytes, or can be read in sections in the invention. With the extracted data, internal and external tables can be addressed. About the second mask means the data structure - again selectively - described at any point, be amended or deleted. Thereby, each node gets even with integration in a conventional ATM layer network self-intervention option for content, format and route guidance. In run (on the fly) can be extracted any bits and bytes and / or inserted and / or overwritten. The sources of data to be inserted not only external tables, but also an interior or exterior, external algorithms that are implemented for example in a form of integrated circuits, or internal tables and storage can be used. On the other hand, the inventive design processing arrangement is easily able to convey ATM cells in a conventional manner, ie only the header to read and translate while all data in the information field is unaffected.

p0009A preferred embodiment of the invention is that the second mask means and the associated writer are provided with means for changing the length of a preamble and / or a post-roll. This also means that bias and / or trailer can be attached to an ATM cell. The same applies to a parallel Spann, whose length preferably corresponds to that of the ATM cell with initial and / or credits.

p0010To permit "on the fly" -Einfügen of data in the data structure, the invention provides in a further development that a delay device is arranged in the conduction path between the input interface and the writing device, in which the data structure is undivided readable. Preferably, the delay means is provided with means for setting the delay time. In this way it is possible to only enter the undivided data structure in the writing means when the insert and / or to append data internal and / or external sources have been taken and are to describe the continuous data structure.

p0011Each is provided with the inventive arrangement node is preferably a microprocessor associated, coupled with all the processing units of the array and configured such that it selects prior to editing the cell current input and output interface, the read and write means resets the first and second mask means for selecting to read and write information sets and optionally specifies the delay time of the delay device.

p0012A further increase in the application possibilities results in development of the invention in that are integrated between writer and output interface means for clock decoupling.

p0013Further advantageous embodiments of the invention are characterized in the dependent claims.

p0014In the following the invention with reference to the drawings based on examples in more detail. In the drawings:<dl id="dl0001"><dt>Fig. 1</dt><dd>schematic representations of various binary data structures including a conventional ATM cell, and contrast changes in data structures to illustrate the possibilities offered by the invention processing options; and</dd><dt>FIG. 2</dt><dd>a special data structure and operations of the invention of this data structure; and</dd><dt>Fig. 3</dt><dd>a block diagram of one embodiment of the processing arrangement of the invention.</dd></dl>

p0015Fig. 1 shows a schematic representations of a conventional ATM cell 1a at its entry into a switching node of a network and in the partial diagrams 1b to 1g modified data structures which are created from the ATM cell of FIG. 1 according to the present invention processing in the node.

p0016The ATM cell 1a shown in FIG. 1 is a data packet with a width of 8 bits, an information field 2 of 48 bytes and a header 3 with a length of 5 bytes. This conventional ATM cell can of course also in the node according to the invention processed in a conventional manner in that the head part 3 is read at the input port and determined from a route switching box output port and written a new label in the header. A change in the information field 2 does not take place.

p0017With 1b an edited in the inventive arrangement described below data structure is referred to, 3 'bits and bytes have been changed in the headboard. As can be seen, the length of the cell (as well as the width) 1b unchanged.

p0018In the data structure 1c bytes marked with 20 are changed in the information field 2 '. The facing both sides arrows to make apparent that changing the bytes in the information field 2 'extended or reduced, or in accordance with an appropriate mask over the field 2' may be discontinuously distributed.

p0019In the data structure 1d the head part 3 is preceded by a preamble whose length is selectively adjustable by means of a write mask. This will be explained in more detail with reference to FIG. 3. In the data structure 1e also selectively adjustable trailer 5 is attached; otherwise the ATM cell information field 2 and the head part 3 remains unchanged.

p0020The data structure 1f of the input data structure 1a is a parallel instep 6 of a width of 2 bits is associated, which extends over the full cell length.

p0021In the data structure 1g finally all editing options are summarized as they have been previously explained to the data structures 1b to 1f.

p0022FIG. 2 shows a specific data structure 1h at their entry into the switching nodes and data structures 1i to 1o offered by each different edits with an inventive arrangement at the output of the node.

p0023The specific data structure 1h as core the ATM cell (1a) with the information field 2 and the head part 3. In addition, first, last, and parallel Range 4, 5 and 6 'are provided.

p00241i The data structure has a modified biasing 4 '; the data in all other sections of the data structure 1i correspond to those of the data structure 1h.

p0025In the data structure 1k different 4-bit units are changed in parallel instep 6 ''. These are marked black in the illustrated embodiment.

p0026In the data structure 1l the data of the information field are changed by the arrangement of the invention, wherein the information field 2 was extended 'to the detriment of the trailing end 5'.

p0027In the data structures 1m and 1n respectively of the biasing 4 '' and the trailer 5 'was' reduced by changing the format of the overall cell.

p0028The data structure 1g has opposite the entrance-side data structure simultaneously experienced 1h various changes. The changed data are applied here too black.

p0029Implementations and applications of the various data structures are described below in connection with FIG. 3.

p0030. The embodiment 3, shown schematically in Fig processing arrangement according to the invention comprises the following components: an input unit 10 having a plurality of interface types A, B, C and D, reading means 11 having associated therewith read mask device 12, a downstream in the conduction of the cell current of the input unit 10 delay means 13, a latter downstream writer 14 with associated write mask means 15, an arranged in the main path of the processed data structures clock decoupling means 16 and an output unit 17 with interface types a, B, C and D.

p0031The node according to FIG. 3 further includes an internal RAM 21, on the one hand via a first demultiplexer 22 with the read mask means 12 and a data transfer device 23 and via a second demultiplexer 24 is coupled to the write mask means 15 and the data transfer device 23.

p0032A microprocessor 25 is connected to all processing units, ie, coupled with the units and 10..17 22..24. Its main function is to select mode prior to processing the input and output interfaces in the inputs and outputs 10 and 17, 11 and 14 reset the reading and writing devices, 12 and 15 to be read, the read and write masks for selecting and writing set information and, if necessary, act on the delay means 13 for setting the delay time. Other functions of the microprocessor 25 and associated components are described below.

p0033The read mask 12 is in the illustrated embodiment, with different target components, namely a header goal, a header destination, a Nachspannziel, an information field goal and a parallel clamping goal coupled. The second or write mask means 15 is correspondingly coupled to a bias source, a headboard source, a Nachspannquelle, an information field source and a parallel clamping source 14 serve as external units, the writing device according to selection on the write mask 15 having to be written or inserted data.

p0034The arrangement illustrated schematically in Figure 3 provides a virtually universal processing option for an ATM cell stream.

p0035By means of the combination of reading device 11 and read mask 12 data can be read selectively from any one or more data portions 2, 3, 4, 5 and 6. FIG. The read or extracted from the data stream data can vary from 8 bits to a complete cell. The read data can be used to select or to produce data on demand that are written using the combination of write mask 15 and writing means 14 in the data structure.

p0036The arrangement of Figure 3 is capable of using the write mask and the writing device to write data 15 and 14 in all sections 2 ... 6 each data structure selectively or to remove data when needed. With respect to the length of the data to be inserted, there are no restrictions: a single bit, an arbitrary bit string, and even a complete cell can be inserted. The data to be written to in an internal memory 21 or from external sources are related, and / or they can be reinserted from previously read data. The data of the cell can, however, pass through unchanged nodes also to those on the head part.

p0037At the output 17 idle cells may be generated. About an input pin not shown in the drawing, the arrangement shown in Figure 3 to produce an empty cell can even be caused when a valid cell one will be received. The parallel Spann 6, 6 'and 6' 'in the data structures 1f to 1o serves primarily the transport of additional data that can not be transferred otherwise occupied in the data field. 2 For this purpose, in addition 53 or 106 bits (in one of the ATM cells corresponding length) in parallel instep 6 to be accommodated, depending on whether the parallel clamping receives a width of one or two bits. The additional information can be found on the write mask 15 a parallel span data source. The same is true for the data to be written into the opening and closing credits, and in the head part 3 and in the information field. 2 The write mask is the possibility to select the affected by the write operation information sections and the individual bits or bytes.

p0038The leaders and trailers 4 and 5 can be used as well as the parallel span to transport additional data, if the data field 2 is already fully occupied with data. Especially useful are the leaders and trailers are but to receive testing, inspection and route information. Inserted in the header or trailer bytes (maximum of 15 bytes in the described embodiment) need not be all added at a node. It may rather be prefixed to successively arranged in Zellstromweg nodes each one or more bytes of the incoming data structure.

p0039The arrangement described has in association with the mask device with an starting register and an information section length register. At the locations designated by the start register bytes are inserted according to the setting of the appropriate length register. The values ​​of the start and length registers have little or gle I be the format of zugehörigne Information section, whether bias, information field, credits or parallel Spann.

p0040Usually the assembly of a replacement data from an incoming cell described ensures. If the user wants to insert a new cell in the data stream, sufficient space must first be placed in the data stream for receiving the cell. For this purpose, an appropriate request signal will be applied to the arrangement shown in Fig. 3. Due to this signal, the arrangement monitors the data stream. Once a to insert the new cell, sufficient space is available, a "Gap" will signal developed by the arrangement. The reading unit 11 is deactivated while the writing means 14 inserts the cell into the data stream. The data transfer device 23 is responsible for updating of externally connected sources or the internal RAM of the node. The sources are read during the passage of a data structure as needed and the result of the read access via the reading means 11 from the assembly. In addition, means are provided to fill the tables with new or valid data or occasionally to verify the accuracy of their content. The data transfer device 23 has the following functions: selecting a refresh interval; Insert an address to the read port; Reading data from a source; and writing data to a source. To start a transfer in the drawing, not shown control register is provided. The internal RAM 21 has 256 entries, each with 8 bits in the described embodiment. This small capacitance is sufficient to permit a use of the arrangement according to the invention also without external components in numerous applications. The RAM can be activated during the reading of the information field 2, the head part 3 and the opening credits. 4 With the RAM 21, the signal interruption is controlled. The user can address sources for the different RAM via the internal RAM control register (not shown) to select.

p0041As said above, the delay means 13 between the entrance unit 10 and writing means 14 adjustable for inserting user-selectable delay times via the microprocessor 25th With a simple copying or writing no large delay time is needed. However, if the to be written into the data structure data depend on the read data, the processing of the read data and the dependent production of new data to be written, a comparatively considerably longer time may be necessary. In such a case, a data structure in the delay unit 13 is delayed for a relatively long delay time to ensure that all the data to be inserted are provided to the writing device is available before the data structure output from the delay means thirteenth

p0042According to a particular embodiment of the invention means for checking the data transfer between the microprocessor 25 and processing components of the arrangement described are provided. This review will take place by means of a so-called dual-write mode, which is activated by a common control register. Here, a register is written twice. First, the register is written with the correct data. The second time to invert all the information and the Registeradreßbits. The two data units and the register address are compared. Only if all information is correct and valid, they are transferred to the internal register. In this way various errors in writing data can be avoided.

p0043Next, the operation of the arrangement shown in FIG. 3 is an example will be briefly described.

p0044Prior to processing of the data structures, the microprocessor must be initialized to prepare for the operating phase. For this purpose, the interfaces are selected at the input and output units 10 and 17, read and write units are reset and the read and write masks set to the data structure to be processed. For example, consider the case assumed that a byte is to be changed in the data structure 1i shown in FIG. 2 of the bias by writing 4. (In addition, the arrangement must read the label head 3 and provided with the new ATM address information.) The internal RAM 21 will be described on the data transfer means 23 with valid values. They are used in the operation as a new header information. The delay means is adjusted with respect to the operation to be performed on a relatively small delay of 20 clock cycles.

p0045The cell with pre-, post- and parallel clamping is read by the reading means 11 byte and then read as an undivided data structure in the delay means. 13 The reading device 11 reads in accordance with the read mask 12 on the one hand the bytes 3 and 4 of the head part 3 of the ATM cell and stores these bytes as a pointer via the demultiplexer 1 to the internal memory 21 at. The store delivers to applying this address information and a certain reaction time (less than the preset delay time of 20 clocks is) information as header information via the demultiplexer 24 and the washer mask means 15 of the writing device 14. The latter in turn addressed the bytes 3 and 4 for describing the head part. In parallel, byte 3 of the header 4 is read by the reading means eleventh Either from the internal RAM 21 or from an external bias source to be inserted at the appropriate location information of the write mask are given to the writer and described the bias of the processed data structure accordingly.

p0046After passing through the clock decoupling stage 16, the changed data structure (1i in FIG. 2) is applied to the output unit 17 and is written via the interface mode A byte. The read and write mask means 12 and 15 are in this operation is set so that data is transmitted unchanged in the post and parallel margins and in the information field. 2

p0047Join one of the processing units during their data processing phase an error, it returns an error message signal to the microprocessor 25. Such messages are stored in appropriate buffers. Error messages are passed from the microprocessor to an external control device, which evaluates such error messages and sends appropriate commands via the microprocessor to the processing units. If after failed attempts during a test mode, a cell or data structure is stored, it may be replaced output through the output unit 17 a blank cell.

p0048As noted above, a clock decoupling is integrated in the connection of the data stream after the writer 14th This allows the output rate be made easily higher than the input rate.