Circuit for the attenuation of a digital audio signal during short disturbances.

The invention relates to a circuit arrangement for damping of a digital audio signal during the occurrence of short-term interference, in particular during a temporary trial basis reception of another transmitter.

In particular, the introduction of the radio data system, in addition to the audio data are transmitted in the, it is possible to switch temporarily during the reception of a radio transmitter to a different frequency to check whether the same program cheaper on this other frequency can be received. During the tentatively receive a disturbance of the audio signal occurs, which lasts for example about 25 ms.

Object of the present invention is to provide a circuit arrangement which damps the audio signal for suppressing brief disruptions without creating this additional interference ( "pops"). The inventive circuit arrangement is to be particularly suitable for digital signal processing.

This object is inventively achieved in that the audio signal is multiplied by a factor which is brought prior to the occurrence of a fault after a predetermined time function from a maximum value to a minimum value, and after the disturbance again to the maximum value.

With the inventive circuit arrangement, other short-term disturbances can be hidden. All signals and signal processing steps are time and value-discrete (digital), so that the circuitry is advantageously in a largely digital broadcast receiver.

A development of the invention is that the attenuation on a logarithmic scale, starting initially flat and then increasingly steep and starting with the minimum value steeply at first and then proceeds increasingly flat with the maximum value of the factor. Through this course, a largely "click" -free muting can be achieved.

Another development of the invention consists in that for the derivation of the factor, an integrator is provided, which preferably consists of an adder and a delay of preferably one sampling period.

An advantageous embodiment of this development is characterized in that the adder a respectively a Integrationsinkrement Performing size and the derived factor from the previous sample can be fed, that the output of the adder is delayed by one sampling an input of a multiplier and an input of a comparator can be fed, wherein another input of the comparator with a constant, which represents the minimum value that can be acted upon, and that an output of the comparator is connected to a further input of the multiplier, whereby at the output of the multiplier is present, the derived factor.

Another development of the invention is that the sign of a Integrationsinkrementes is controllable by means of a control signal supplied. A simple control of the circuit arrangement is possible. It is merely a control signal required to have a second signal jump in time before an anticipated fault a first signal jump and at the end of the fault.

If according to another development, the size of a Integrationsinkrementes by means of another control signal supplied is switched, can except the fast increasing and decreasing the damping also take a slower control, for example, when changing the signal source.

In the case of a stereo broadcast radio receiver is preferably provided for the audio signal of a left stereo channel and the audio signal of a right stereo channel are multiplied by the factor.

Embodiments of the invention are shown in the drawing using several figures and explained in more detail in the following description. It shows:<ul><li>Fig. 1 as a block diagram an embodiment of the invention, and</li><li>Fig. 2 is a logarithmic representation of the variation of the factor and hence the attenuation of the audio signal.</li></ul>

The inventive circuit arrangement can be realized in various ways. Thus, can be realized, for example individual or groups of blocks shown by suitable circuits, in particular integrated circuits. At very high degree of integration, it is also possible to realize the recipient's entire digital signal processing in an integrated circuit, signal processing steps such as filtering or non-linear weights, are performed by arithmetic operations. Within an integrated circuit in order to implement a receiver having the circuit arrangement according to the invention also digital signal processors and other digital circuits, such as shift registers, flip-flops etc., be co-located.

The circuit arrangement according to Fig. 1, the audio signals L (left) and R (right) via inputs 1, 2 can be fed. After passing through each of a multiplier 3, 4, the damped th audio signals if necessary and LAMU RAMU outputs 5, 6 are removed. The multipliers 3, 4, a factor K supplied, which has a maximum value of 1 under normal conditions and to hide (muting) is brought to a minimum value of the 0th The transition takes place after a predetermined time function, so that even there are no pops through the transition.

For deriving the factor K, an integrator is provided, which essentially consists of an adder 7 and 8 a delay by one sampling period. The output value of the delay 8 is hereinafter referred to as the integration value and passed over a further multiplier 9, in which a multiplication by 1 or 0 takes place. In the case of multiplication by 1 of the factor K corresponding to the integration value, while in the case of multiplication by the factor 0 K = 0th The latter is required to maintain the factor K to 0 when the integration value should assume negative values. For this, the integration value is fed to an input of a comparator 10, a abuts the minimum value representing constant C1 at whose further input - at a minimum value of 0 is then C1 = 0. The output x&gt; -y of the comparator 10, which is a one-bit signal leads, is then connected via a format converter 11 for conversion to a 16-bit signal to the multiplier. 9 The upper limit of the factor K to the maximum value is not shown in FIG. 1. It is similar to the limitation to the minimum feasible.

The 12 in the adder 7 supplied Integrationsinkrement can be provided with different signs to decrease and to increase the factor K. For this purpose, a negator 13, and a changeover switch 14 is provided which is controllable by a control signal FMU, which is an input 15 supplied.

With another switch 16 which is controlled by means of an insertable at 17 control signal RDS_SO can optionally two different Integrationsinkremente C2 and C3 are used. One Integrationsinkrement C2 with a value of 0.0219 for example causes a rapid change in the factor K, which is favorable for the short-term trial basis switching the reception frequency. In other cases, the muting, for example, during normal channel scan or during a switching between different audio sources, a slower change of the signal K can be carried out, including the Integrationsinkrement C3 is used, for example, has a value of 0.000219.

Fig. 2 shows an embodiment of a mute curve, wherein the abscissa is shown in ms and the ordinate represents the attenuation achieved in logarithmic scale in dB time. At the time of 0 starts the mute operation and reached after 1.5 ms, an attenuation of -40 dB. The complementary process begins at the time 2.5 ms. The curve shown is obtained with a Integrationsinkrement of 0.0146. Especially advantageous is the first flat shape of the curve, and then very steep drop to high attenuation out. Through this course, a largely "click" -free muting can be achieved.