Semiconductor memory system including a flash EEPROM.

0001The present invention relates to a semiconductor memory system equipped with a flash EEPROM (Electrically Erasable and Programmable Read Only Memory) which is a non-volatile memory that is electrically and collectively erasable and rewritable.

0002More particularly, this invention relates to a semiconductor memory system that can realize miniaturization.

0003Most of conventional information processing systems, such as a work station and a personal computer, use a magnetic disk drive as a secondary memory device. The magnetic disk drive has advantages such as a high recording reliability and low bit price while having some shortcomings such as its being large and susceptible to physical impact.

0004The operational principle of magnetic disk drives is to move a magnetic head on a rotating disk to write or read data on or from that disk. The mechanical moving portions, such as the rotatable disk and the magnetic head, may malfunction or may be damaged when a physical shock is applied to the disk drive. Further, the necessity of those mechanical movable portions impedes making the whole drive more compact.

0005Accordingly, these deficiencies represent a significant problem when loading the magnetic disk drive into a small portable computer, such as a note book type or pen type personal computer.

0006Today, therefore, there is a need for a semiconductor memory system which is small in size and not susceptible to physical impact. The semiconductor memory system usually has a plurality of EEPROM chips. The semiconductor memory system can be used as a secondary memory device instead of a magnetic disk drive. A computer system can use the semiconductor memory system by a same method of access for the magnetic disk drive.

0007The semiconductor memory system has several merits in the case of use in a personal computer.

0008As one merit, a size of the semiconductor memory system can be smaller than a size of the magnetic disk drive. However, a EEPROM chip used in the semiconductor memory system is very expensive. Therefore, there is a need for a product and parts cost of a semiconductor memory system that is as low as possible.

0009As another merit, the semiconductor memory system is readily adapted to control EEPROM and is resistant to breakage because it does not include movable parts. However, a cell array of an EEPROM is deteriorated by rewrite operations (erase and write) little by little. In time, one of the flash EEPROMs in the semiconductor memory system will have some memory blocks which cannot be rewritten by the semiconductor memory system, because dispersion of rewrite times varies widely. Therefore the semiconductor memory system will be required to be able to exchange a unit of an EEPROM chip, when the semiconductor memory system is used as the secondary memory device in a computer, such as a portable type of computer.

0010It is an object of the present invention to provide a semiconductor memory system which can achieve minimization and low cost by reducing the number of component parts.

0011In accordance with the present invention there is provided a peripheral semiconductor memory system including first and second memory drives. The system comprises a first flash EEPROM included in the first memory drive, a second flash EEPROM included in the second memory drive, and means for controlling access to the first and second flash EEPROMs. The access controlling means includes an address converting means for converting a logical address from a host system into a physical address, according to first and second file management information which indicates correspondence between logical addresses and physical addresses of the first and second memory drives, respectively. The access controlling means further includes memory accessing means, coupled to each of the first and second flash EEPROMs, for accessing a selected EEPROM according to the physical address from the address converting means.

Brief description of the drawings

0012The present invention will be apparent from the following description, in connection with the following figures, of which:

0013Fig.1a is a block diagram showing an embodiment of a semiconductor memory system according to the present invention.

0014Fig.1b shows an address conversion table, which is referred by an access controller in the semiconductor memory system as shown in Fig.1a for converting logical address into physical address.

0015Fig.1c shows a memory block information table stored in a flash EEPROM chip,

0016Fig.2 shows a conceptual diagram of a semiconductor memory system which is controlled as two drives by a host system.

0017Fig.3 shows a physical arrangement of a part of the embodiment shown in Fig.1

0018Fig.4 shows a type of address conversion table used in the embodiment shown in Fig.1

0019Fig.5 is a flow chart showing access control processing when the semiconductor memory system uses the address conversion table of the Fig.4.

0020Fig. 6 is a flow chart showing a process of exchanging a flash EEPROM chip for another flash EEPROM chip of the same memory capacity.

0021Fig. 7 is a flow chart showing a processing of exchanging a flash EEPROM chip for another flash EEPROM chip of double memory capacity.

0022Fig. 8 is a flow chart showing a process of expanding a flash EEPROM chip without exchanging flash EEPROM chips.

0023Fig.9 is a block diagram of a single package LSI showing another embodiment of the present invention.

0024Fig.10 is a block diagram of the semiconductor memory system using the single package LSI shown in fig.9.

0025Fig 11 is an address conversion table for an access controller shown in Fig.9

0026Fig.12 shows a conceptual diagram of a semiconductor memory system which is controlled as two drives by a host system and which uses the single package LSI shown in Fig.9.

0027Fig.13 shows a physical arrangement of a host system including a semiconductor memory system structured on a memory board.

0028Fig.14 is a block diagram of the host system shown in Fig.13.

0029Fig.15 shows a physical arrangement of a host system including chips of the semiconductor memory system mounted on a mother board of the host system.

0030Fig.16 is a block diagram of the host and semiconductor memory systems shown in Fig.15.

0031Fig.17 shows a physical arrangement of a host system including connectors for inserting the single package LSI chip and a plurality of flash EEPROM chips of the semiconductor memory system, on a mother board in the host system.

0032Fig.18 is a block diagram of the host system having lines for determining whether or not the single package LSI chip shown in Fig.17 is inserted into its connector.

0033An embodiment of the present invention will be described with reference to the accompanying drawings.

0034Fig.1a shows a block diagram of a semiconductor memory system according to an embodiment of the present invention.

0035A semiconductor memory system 100, connected to a personal computer (host system 1), comprises a plurality of flash EEPROM chips 101-106, two IC slots 111 and 112, a host interface 120 and a controller unit 130, and is used as a secondary memory device for the host system in place of a hard disk drive or a floppy disk drive or a memory card, and has a PCMCIA (Personal Computer Memory Card International Association) interface or an IDE (Integrated Drive Electronics) interface, for example.

0036Each of the flash EEPROM chips 101-106 comprises a cell array and a plurality of peripheral logic functions, such as a row address decoder, for the cell array. Each EEPROM chip 101-106 has an input/output (I/O) register, for example structured for 256 bytes. In each flash EEPROM chip 101-106, a minimum unit of data amount handled in a write or an erase operation is determined and the unit amount of data is handled together. For example, it is assumed that the flash EEPROM allows data write operations in pages of 256 bytes and data erase operations in blocks of 4K bytes. In this case, for each of the flash EEPROM chips 101-106, it is preferable to use a Toshiba 16 M-bit NAND flash EEPROM. The flash EEPROM be accessed by providing an initial memory address of an unit of data.

0037Each of the IC slots 111 and 112 is an expansion slot for expanding a flash EEPROM chip.

0038The flash EEPROM chips 101-106 and the IC slots 111 and 112 are connected to the controller unit 130 via a common I/O bus and a common read/write control line (R/W). Further, each flash EEPROM chip 101-106 and each IC slot 111 and 112 independently is connected to the controller unit 130 via a chip select signal (each CS 1-8) line and a ready/busy signal (R/B) line.

0039The host interface 120, like a hard disk drive connectable to a host system, has, for example, a 40-pin arrangement conforming with the IDE interface, or like an IC card installable in an IC card slot, has, for example, a 68-pin arrangement conforming with the PCMCIA interface.

0040The controller unit 130 comprises a host interface controller 131, an access controller 132 and a DRAM 133.

0041The host interface controller 131 controls communication between the host interface 120 and the access controller 132, and has several registers, including a sector number register 141, sector count register 142, data register 143, cylinder register 144, drive/head register 145, command register 146 and status register 147. These registers 141-147 are able to be read and be written by the host system 1. The sector number register 141 stores an access head sector number transmitted from the host system 1. The sector count register 142 stores a number of sectors which indicates a sector size of write or read data. The data register 143 stores write data from the host system 1 or read data to the host system 1. The cylinder register 144 stores an access cylinder number transmitted from the host system 1. The drive/head register 145 stores an access drive number and an access head number transmitted from the host system 1. The command register 146 stores a command, such as read or write, transmitted from the host system 1. The status register 147 stores status of the semiconductor memory system 100.

0042The DRAM 133 has a management area for storing an address conversion table 150, and so on, and a data buffer area for storing write data or read data temporarily.

0043Fig.1b shows the address conversion table 150.

0044When the host system is powered on, the access controller 132 reads memory block information table 191-196 (MBIT, as shown in Fig.1c) which is stored in each EPROM chips 101-106, respectively. The access controller 132 generates an address conversion table 150 in according to the memory block information tables and each chip numbers corresponding to each memory block information tables. The generated address conversion table 150 is stored in DRAM 133.

0045The address conversion table 150, which defines address conversion information for indicating a correspondence between logical addresses from the host system 1 and physical addresses of the flash EEPROM chips 101-106. Herein, the logical address, output from the host system, comprises a cylinder number, a head number, a sector number and a drive number. The physical address comprises a chip number of an EEPROM chip and an initial memory address of a sector block in the EEPROM chip.

0046The address conversion table 150 defines an assigned drive number 0 to the EEPROM chips number 1-3, i,e., chips 101-103 and an assigned drive number 1 to the EEPROM chip number 4-6, i,e., chips 104-106. The host system 1 uses drive number 0 for a master drive, and uses drive number 1 for a slave drive, for example.

0047The access controller 132 has a microprocessor and firm ware for controlling the processor, and provides access control of the flash EEPROM chips 101-106 for the host interface 120 and the host interface controller 131, in response to a disk access request supplied from the host system 1. That is, the access controller 132 reads commands and parameters stored in the registers in the interface controller 131, and controls flash EEPROM chips 101-106 in response to the contents of the registers.

0048The access controller 132 has a function for converting a logical address from the host system 1 into physical address of the flash EEPROM chips 101-106, according to the address conversion table 150 stored in the DRAM 133.

0049In the result of the address conversion table 150, the access controller 132 selects one -of these flash EEPROM chip ( by providing a signal to one of the chip select signal lines CS1-CS6 ) and generates a real memory address. The access controller 132 repeats to generate logical address still times of the value in the sector count register and sequentially provides logical addresses to the flash EEPROM chips 101-106, according to the table 150.

0050The access controller 132 manages rewrite (or erasing) times of each erasable block in each flash EEPROM chip 101-106 by using rewrite count information in each flash EEPROM chips 101-106. Here, a management unit of rewrite count information is an erasable block of the flash EEPROM chip, for example 4K bytes. The access controller 132 further manages attribute information, such as the number of the connected chips and a total memory capacity of the flash EEPROMs, by using a configuration table stored in one or more flash EEPROM chips.

0051The operation of the semiconductor 100 memory system will be described as follows.

0052The host system 1 provides command,sector size and logical address (same HDD address) to the semiconductor memory system 100, if the semiconductor memory system 100 is not of active state. The host system 1 judges whether the semiconductor memory system 100 is active or non-active, by the content of the status register 147.

0053The host interface controller 131 in the semiconductor memory system 100 receives the command, sector size and the logical address, and stores this information in the registers 141-146.

0054The access controller 132 reads the contents of the registers 141-146 in the host interface controller 131, when the host system 1 provides an access request to the semiconductor memory system 100. The access controller 132 determines a physical address from the logical address structured by data in the registers 141,144,145, by referring to the address conversion table 150. The access controller 132 further generates a next logical address by incrementing by '1' the value in the register 141, and determining the next physical address from the next logical address by referring to the address conversion table 150. The access controller 132 sequentially decides physical address, according to repeating the operation still times of the value in the register 142.

0055The access of flash EEPROM can be achieved by a command method where an operation mode of the flash EEPROM is specified by a command.

0056According to a command method, first, the access controller 132 provided a chip enable (CE) signal for indicating an active state of a selected flash EEPROM chip by the address conversion table 150. Next, the access controller 132 provides a memory command for indicating an operation mode(write, read, erase, verify and so on) to the flash EEPROM chips 101-106 via a read/write control line. Next, the access controller 132 provides a memory address for indicating an access start address to flash EEPROM chip 101-106 via the I/O bus. After providing the memory address, if the operation mode is the write mode, then the access controller 132 transfers write data via the I/O bus, and if the operation mode is the read mode, then the access controller 132 receives read data from the selected flash EEPROM via the I/O bus. Here, if the operation mode is the write mode, then the access controller 132 is free from access control for the selected flash EEPROM after transferring write data to the I/O register(for example, 256 byte) in the selected flash EEPROM, and the write operation is run automatically in the selected flash EEPROM only.

0057The host system 1 identifies a first memory block (the flash EEPROM 101-103) with drive number 0, and identifies a second memory block (the flash EEPROM 104-106) with drive number 1. That is, the host system 1 recognizes the semiconductor memory system 100 as having two different secondary memories. The controller unit 130 manages each of the two memory blocks independently. This concept is shown in Fig. 2.

0058As shown in Fig. 2, the semiconductor memory system 100 is handled as two drives, by a File Allocation Table (FAT) file system installed in the host system 1. A first memory block 181 is managed by a FAT1 stored in the flash EEPROM 101 and a second memory block 182 is managed by a fate stored in the flash EEPROM 104. Accordingly, the semiconductor memory system 100 does not write one file to the first memory block 181 and the second memory block 182 separately. That is, for example, the files of the second memory block 182 are not influenced, even if the first memory block 181 is changed or expanded.

0059Accordingly, a user can easily exchange the memory capacity of the first memory block 181 without influencing the files in the second memory block 182. Moreover, each of the first and the second memory block 181, 182 can have total address conversion information for address conversion table 150 without separating address conversion information with respect to association with each of memory block 181,182. In this case, address conversion table 150 generated in the access controller 132 can be selected by the host system 1.

0060Fig.3 shows a physical arrangement of the semiconductor memory system 100 according to an embodiment of the present invention.

0061Fig.3 shows only the flash EEPROMs 101-103 of the first memory block 181, typically.

0062The controller unit 130 and IC slots 201-203 are directly are mounted on a printed circuit board 210, but the flash EEPROM chips 101-103 are mounted on the printed circuit board 210 via IC slots 201-203. As a result, each flash EEPROM chip, the including chips 101-103 can easily be connected and disconnected by user.

0063Fig. 4 shows another address conversion table 250 which can be used in the access controller 132.

0064The address conversion table 250 does not list the drive number, but the flash EEPROM chips 101-103 and the flash EEPROM chips 104-106 have continuously assigned sector numbers. For managing the sector numbers by each drive, each value of the start sector number assigned to each of the first memory block and the second memory block must begin with 0. However, in this case, each value of the sector numbers of the second memory block 182 listed in the address conversion table 250 adds the value 0-m of real sector numbers to an offset value (n+1). As a result, the access controller 132 operates normally.

0065With reference to the flow chart of Fig. 5, operations of the semiconductor memory system 100 using address conversion table 250 of Fig.4 will be described.

0066First, the host system 1 writes a command, such as read or write, in the command register 146 (step 11). Next, the host interface controller 131 sets a busy flag in the status register 147 (step 12). The access controller 132 determines that a command is written in the command register 146, and reads the command in the command register 146 (step 13,14). The access controller 132 evaluates the command (step 15). The access controller 132 generates a sector address for referring to the address conversion table 250, on the basis of the drive number and the sector number from the host system 1. If the drive number is 1, then the sector address is the sector number plus offset value (n+1), else the sector address is the sector number (step 16). The access controller 132 generates a physical address from logical address (having the sector address) on the basis of the address conversion table 250 (step 17). Next, the access controller 132 controls the access of one of the flash EEPROM 101-106, according to a physical address generated by the address conversion table 250 and the command (step 18). Last, the host interface controller 131 resets busy flag in the status register 147 (step 19).

0067In this embodiment, the host system 1 can recognize the first and second memory blocks 181,182 as independent disk drives. The FAT file system in the host system 1 independently can manage data written in the first memory block 181 and data written in the second memory block 182.

0068For example, even though a user replaces at least one of the EEPROM chip 104-106 of the second memory block 182 with another EEPROM chip, the files stored in the fist memory block are not influenced, because the semiconductor memory system does not write separately the first memory block and the second memory block.

0069Accordingly, each memory block 181,182 managed by each drive can easily be able to change capacity of the memory block, such as structuring first memory block 181 to consist of the two EEPROM chip 101,102 only, without influencing the other memory block.

0070More over, each memory block 181,182 managed by each drive can easily be able to replace at least one of the EEPROM chips in either memory block with another EEPROM chip without influencing the other memory block.

0071Next is described a memory management operation when a new flash EEPROM chip is connected to an IC slot 111.

0072Fig. 6 shows a process flow chart for exchanging a flash EEPROM chip, such as a flash EEPROM having an erasable block which has been rewritten more than a desired number of times, with a new flash EEPROM chip of the same size which is connected to the empty slot.

0073The access controller 132 monitors and controls the number of rewrite (or erasing) times of each erasable block in each flash EEPROM chip 101-106 by using rewrite count information in each flash EEPROM chip 101-106. When one of the flash EEPROM chips 101-106 has an erasable block which has been rewritten more than a desired number of times, the access controller 132 provides a chip number of the particular EEPROM chip to the host system 1.

0074The host system 1 displays a message indicating the chip number of the chip which must be exchanged. The user connects a new flash EEPROM chip of the same size into an empty slot, such as the IC slot 111 (step 21). Next, the user inputs a command for running a utility program for enabling the use of the new flash EEPROM chip, and inputs the chip number of the exchanged chip (step 22). Here, the host system 1 provides a command for running the utility program and the chip number to the access controller 132, and the utility program is run by the MPU in the access controller 132. The access controller 132 directly copies all information stored in the exchanged chip (for example, flash EEPROM 101), into the new chip connected to the slot 111 newly (step 23). The number of the IC slot to which the new flash EEPROM chip is connected can be determined by referring to each Ready/Busy signal. For example, when the new flash EEPROM is connected to the IC slot 111, the Ready/Busy signal, indicating a state of high impedance level or ground level, changes the Ready state because of insertion of the new flash EEPROM chip. Thus, the access controller 132 can determine the number of the slot to which the new flash EEPROM is connected by change of the each Ready/Busy signal. Next, the MPU rewrites the rewrite count information in the new flash EEPROM to initialize a value '0', because the controller has copied the rewrite count information of the exchanged flash EEPROM chip into the new flash EEPROM chip, in the previous copy operation (step 24). Next, the MPU writes the address conversion table 150, to correct the chip number registered physical address to the chip number of the new flash EEPROM chip (step 25). For example, when the number of the new chip connected to the slot 111 is 7, the address conversion table 150 of Fig. 1 is connected to change the registered chip number '1' into the chip number '7'. In response to the MPU signaling an end of the exchanging operation to the host system, the host system 1 displays a message indicating an end of the exchanging operation (step 26). The user removes the exchanged flash EEPROM chip, after receiving the message from the host system (step S27).

0075The host system 1 can handle the new EEPROM chip as the drive 0 in the semiconductor memory system 100. Also, the memory capacity of the new flash EEPROM chip can be different from the memory capacity of the exchanged flash EEPROM chip.

0076Fig. 7 shows a process flow chart for exchanging a flash EEPROM chip (chip type 1), such as a flash EEPROM chip having erasable block which has been rewritten more than a desirable number of times, for a new flash EEPROM chip of double memory capacity(chip type 2) connected to an empty slot.

0077The user connects a new flash EEPROM of the chip type 2 to the empty slot, such as the slot 111 (step 31). Next, the user inputs a command for running a utility program for enabling the use of the new flash EEPROM chip, and inputs the chip number of the exchanged chip (step 32). Here, the host system 1 provides a command for running the utility program and the chip number to the access controller 132, and the utility program is run by the MPU in the access controller 132.

0078The access controller 14 recognizes a chip type of the new flash EEPROM chip inserted into the slot 111. A recognizing method for the chip type can be achieved by whether or not the access controller 132 reads an ID stored at a head address (B0B0) of a second chip area of the flash EEPROM. The second chip area is an area in excess of the memory size of the chip being replaced. For example, when an exchanged chip has 4 M byte and a new chip has 8 M byte, a second chip area is the area of the new chip in excess of 4 M byte. If the new flash EEPROM chip does not have a second chip area, then the address B0B0 does not exist. Thus, the access controller 132 determines the chip type (step 33,34). In this case, if the access controller 132 can read the ID, then the access controller 132 determines the new chip is type 2, otherwise the new chip is type 1. In the case of determining that the chip is type 2, the MPU determines a first chip area of the new flash EEPROM as an area for exchanging the exchanged chip, and determines the second chip area as an area for expanding memory area (step S35). The access controller 132 copies all information stored in the exchanged chip (for example, flash EEPROM 101), into the first chip area of the new flash EEPROM connected to the slot 111 (step S36). The MPU rewrites the rewrite count information in the new flash EEPROM to initialize a value '0', because the controller copied the rewrite count information of the exchanged flash EEPROM chip into the new flash EEPROM chip, in the previous copy operation (step 37). Next, the MPU writes the address conversion table 150, to correct the chip number registered physical address to the chip number of the new flash EEPROM chip. Moreover, the MPU enters the second chip area in the address conversion table (step 38). For example, when the number of the new chip connected to the slot 111 is 7, the address conversion table 150 of the Fig. 1 is corrected to change the registered chip number '1' into the chip number '7'. Further, the address conversion table 150 next lists the second chip area as a new logical area. Now, the chip number of the second chip area is #7, but the head address of the second chip area is the next address after the last address of the first chip area. Next, in response to the MPU signaling an end of the exchanging operation to the host system, the host system 1 displays a message indicating the end of the exchanging operation (step 39). The user removes the exchanged flash EEPROM chip, after receiving the message from the host system (step 40).

0079Fig.8 shows a flow chart for expanding flash EEPROM chip memory without exchanging flash EEPROM chips. Hereinafter,the semiconductor memory system has only flash EEPROMs 101-103 as drive #0, and will handle a new expanded flash EEPROM chip or chips as drive #1.

0080The user inserts a new flash EEPROM chip in to an empty slot, for example the slot 111 (step 51). Next, as a result of the host system being turned on by the user, the MPU in the access controller 132 knows the number of the chips in the semiconductor memory system (step 52). The number of chips can be determined by referring to each Ready/Busy signal line. Next, when the MPU determines it is necessary to expand the memory by comparing the number of chips determined to be connected by the Ready/Busy signals, with the number of chips registered in the config. table, the MPU assigns the expanded chip as drive #1 (step 53). The MPU enters logical addresses assigned as drive #1 in the address conversion table 141 (step 54). After this, the MPU rewrite the number of the chips stored in the config. table to include the new value of the expanded flash EEPROM chip (step 55). As a result, the host system 1 handles the semiconductor memory system 100 as two disk devices corresponding to the drives # 0 and 1.

0081Further, the semiconductor memory system 100 can not only add to the number of drives, but also can expand memory capacity of the drive 0 or drive 1 by expanding the flash EEPROM chip. For example, in the case of increasing memory capacity of drive #1, the access controller 132 will assign the new logical address following the last logical address in the drive #1 to the new chip.

0082Accordingly, the semiconductor memory system can exchange memory area of one independent drive, according to replacing and expanding (or reducing) EEPROM chips.

0083Fig.9 shows yet another embodiment of the present invention.

0084The semiconductor disk LSI 300 is structured as a single package. The semiconductor disk LSI 300 comprises a flash EEPROM unit 360, a controller unit 330, a host interface 320, a memory command interface 321, memory data interface 322, and chip enable (CE) interface 323.

0085The flash EEPROM unit 360 comprises an EEPROM cell array and a plurality of peripheral logics, such as a row address decoder,for the cell array. The flash EEPROM unit 360 has an input/output (I/O) register, for example structured 256 byte. In the flash EEPROM unit 360, a minimum unit of data amount handled in a write or an erase operation is determined and the unit amount of data is handled together. For example, it is assumed that the flash EEPROM unit 360 allows data write operations in pages of 256 bytes and data erase operations in blocks of 4K bytes.

0086The controller unit 330 comprises a host interface controller 331, an access controller 332 and a DRAM 333.

0087The host interface controller 331 and the DRAM 333 have functions the same as the host interface controller 131 and the DRAM 133 as shown Fig.1.

0088The host interface 320, like a hard disk drive connectable to the host system 1, has, for example, a 40-pin arrangement conforming with the IDE interface, or like an IC card installable in an IC card slot, has, for example, a 68-pin arrangement conforming with the PCMCIA interface.

0089The memory command interface 321, the memory data interface 322 and the chip enable interface 323 provide access control of expansion flash EEPROM chips, and each interface 321-323 has a plurality of input/output pins for receiving and transferring each signal between each interface 321-323 and expansion flash EEPROM chips 401-403.

0090The access controller 332 provides access control of the flash EEPROM unit 360 via the host interface 320 and the host interface controller 331, in response to a disk access request supplied from a host system 1.

0091There is described a method by which the access controller 332 controls access to the flash EEPROM unit 360.

0092First, the access controller 332 provides chip enable (CE) signal 0 for indicating an active state to the flash EEPROM unit 360. Next, the access controller 332 provides a command for indicating an operation mode (write,read,erase,verify and so on) to the flash EEPROM unit 360 via the read/write control line. Next, the access controller 332 provides a memory address for indicating an access start address to the flash EEPROM unit 360 via the I/O bus. After providing the memory address, if the operation mode is the write mode, then the access controller 332 transfers write data via the I/O bus, and if the operation mode is the read mode, then the access controller 332 receives read data from the flash EEPROM unit via the I/O bus. Here, if the operation mode is the write mode, the access controller 332 releases access control for flash EEPROM unit 360 after transferring write data to the I/O register in the flash EEPROM unit 360, and the write operation is run automatically by the flash EEPROM unit 360 itself.

0093The access controller 332 not only can control the flash EEPROM unit 360 in the semiconductor LSI 300, but also can provide the same access control to a plurality of expansion flash EEPROM 401-403 chips connected to the semiconductor LSI 300, according to need.

0094Referring to Fig.10, a semiconductor memory system structured by a unit which includes the semiconductor disk LSI 300, such as a memory board and a memory card will be described.

0095A semiconductor memory system unit 420 is structured by a printed circuit board 410 or which the semiconductor disk LSI 300 and three flash EEPROM chips 401-403 are mounted. Each flash EEPROM chip 401-403 is connected to the memory command interface 321 via a common read/write control line, and is connected to the memory data interface 322 via a common I/O bus. Each flash EEPROM chip 401-403 independently is connected to the chip enable interface 323 via a chip enable signal line and a ready/busy signal line (not shown), and receives the chip enable signal from the chip enable interface 323. Moreover, the semiconductor memory system unit 420 has a card edge type connector 430 for connecting between the host system 1 and the host interface 320 in the semiconductor disk LSI 300.

0096In response to generating one of the chip enable signals CE1-3, one of the expansion flash EEPROM chips 401-403 is selected. Hereinafter, CE1,CE2 and CE3 are used for selecting each expansion flash EEPROM chip. In the case of selecting the expansion flash EEPROM chip 401, CE 1 is generated. Similarly, in the case of selecting the expansion flash EEPROM chip 402, CE 2 is generated. Similarly, in the case of selecting the expansion flash EEPROM chip 403, CE 3 is generated.

0097The chip enable signal is generated by the access controller 332, on the basis of an address conversion table 350, as shown Fig.11.

0098The address conversion table 350 defines the relation between logical addresses and physical address. The logical addresses has a track (cylinder + head) number and a sector number. The physical address has a chip number and a memory address. The chip number is used for determining the chip enable signal.

0099If the access controller 332 receives a logical address between track number 0 and L, then the address conversion table 350 indicates chip enable signal 0 (CE 0) should be generated for selecting internal flash EEPROM unit 360. Similarly,if access controller 332 receives a logical address between track number L+1 and 2L, the address conversion table 350 indicates chip enable signal 1 (CE 1) should be generated for selecting the first expansion flash EEPROM chip 401. Similarly,if access controller 332 receives a logical address between track number 2L+1 and 3L, the address conversion table 350 indicates chip enable signal 2 (CE 2) should be generated for selecting the second expansion flash EEPROM chip 402. Similarly,if access controller 332 receives a logical address between track number 3L+1 and 4L, the address conversion table 350 indicates chip enable signal 3 (CE 3) should be generated for selecting the third expansion flash EEPROM chip 403.

0100Thus, the semiconductor disk LSI 300 can be structured as a single chip which can control the internal flash EEPROM and the expansion EEPROM chips.

0101Therefore, a semiconductor memory system 420 including the semiconductor disk LSI 300 is able to reduce the number of parts and to achieve miniaturization and low-cost.

0102When the semiconductor memory system 420 is used by the host system 1, the host system 1 further is able to assign the semiconductor memory system unit 420 to two disk drives, as in the above embodiment. This concept is shown by Fig. 12.

0103The host system 1 assigns a first memory block 500 (the flash EEPROM unit 360) the drive number 0, and assigns a second memory block (the expansion flash EEPROM 401-403) the drive number 1. That is, the host system 1 recognizes the semiconductor memory system 420 as two different secondary memories. The semiconductor disk drive LSI 300 manages each memory block independently, according to each MBIT (memory block information table) 491, 494, 495, 496. Moreover, the flash EEPROM chips 401-403 can be connected to the printed circuit board via a slot, in the same manner as IC slots 201-203 as shown in fig.3.

0104Thus, a user can expand memory capacity in the semiconductor memory system unit easily, according to need.

0105The following describes an embodiment of a semiconductor memory system which uses the semiconductor disk LSI 300 as shown fig 9 through fig 12 as secondary memory in a personal computer.

0106Fig.13 and Fig.14 show a host system 600 connected to a semiconductor memory system, which is a memory board type.

0107A CPU 611, main memory 612, two I/O controller 613, 614, a connector 630, etc., mount on a mother board 610 in the host system 600, and each component is interconnected to a system bus 615. The semiconductor memory system is structured to include a memory board 620 on which is mounted the semiconductor disk LSI 300 and three flash EEPROM chips 401-403. The memory board 620 is connected to the host system 600 via the connector 630. The memory board 620 is also connected to the system bus 615. Moreover, the memory board 620 becomes memory card, if the memory board 620 is provided as a package.

0108The following describes another embodiment of a semiconductor memory system which uses the semiconductor disk LSI 300 as secondary memory in a personal computer.

0109Fig.15 and Fig.16 show a semiconductor memory system, which is structured to include the semiconductor disk LSI 300 and three flash EEPROM chips 401-403 mounted on a mother board 710 in the host system 600.

0110A CPU 611, main memory 612, two I/O controllers 613, 614, etc., are mounted on the mother board 710 in the host system 600, and each component is interconnected to the system bus 615. Each of the semiconductor disk LSI 300 and three flash EEPROM chips 401-403 for structuring the semiconductor memory system can be handled as a peripheral chip, such as the CPU chip 611, and can be connected to the system bus 615 directly.

0111The mother board 710 in the host system 600 does not have to have a connector for a memory card or a memory board. Therefore, a mounting layout on the mother board 710 is more flexible.

0112Fig. 17 illustrates a physical arrangement of the mother board 710.

0113A LSI slot 720 and IC slots 721-723 are directly mounted on the mother board 710, but the semiconductor disk drive LSI 300 is mounted on the mother board 710 via the LSI slot 720 and the flash EEPROM chips 401-403 are mounted on the mother board 710 via the IC slots 721-723.

0114Therefore, the mother board adds only four slots 720-723 and lines for interconnecting to each slot, because the semiconductor disk drive LSI 300 and each flash EEPROM chip 401-403 can easily be connected and disconnected by the user. Therefore, the user can select whether the semiconductor memory system is introduced in the personal computer 600 freely.

0115Further, with reference to Fig.18, the host interface 320 in a semiconductor disk LSI 300 may have a signal ID in the case of mounting the semiconductor disk drive LSI 300 on the mother board 710. The signal ID indicates whether the semiconductor disk drive LSI 300 is connected to the LSI slot 720. The signal ID is provided as a high active state by an electrical charge terminal for keeping the high active state. Generally speaking, a magnetic disk interface had by a host system uses the ID signal, for determining whether the magnetic disk drive is connected to the host system. Thus, the magnetic disk interface can be used without exchanging the magnetic disk interface had by the host system.