Ecl-to-bicmos/cmos translator

An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage (42) having an output node (50) and a first output switching means (Q13) for coupling the output node (50) to a first voltage (-VDD) supply and a second output switching means (Q14) for coupling the output node (50) to a second voltage supply (VSS). A first input stage (38) activates the first output switching means (Q13) of the output stage (42) in response to one of the differential ECL signals, and a second input stage (40) activates the second output switching means (Q14) of the output stage (42) in response to the other differential ECL signal. The first input stage (38) includes a first input switching means (MP6) for coupling a first resistive element (R12) between the first voltage supply (-VDD) and the output node (50) of the output stage (42), and the second input stage (40) includes a second input switching means (MP8) for coupling a second resistive element (R14) between the first voltage supply (VDD) and the second voltage supply (VSS).