Circuit for generating a programming voltage for a programmable read-only memory, especially of an EPROM type, and method and memory relating to it.

0001The present invention relates to a device for generating a programming voltage of a programmable permanent memory, in particular an EPROM type memory.

0002It also relates to a method implemented in this device as well as a memory integrating this device.

0003During programming operations of programmable memories, in particular of the EPROM type, the voltage generators with which these memories are provided must deliver, from an applied external voltage, a stabilized programming voltage to memory cells which represent an equivalent charge of substantially variable impedance. However, current generation devices generally have an output impedance that is too high to help limit the programming voltage variations induced by the constraints inherent in manufacturing to reasonable levels.

0004However, excessive voltage variations cause stresses on the components which can lead to their degradation and destruction.

0005The object of the present invention is to remedy these drawbacks by proposing a device for generating a programming voltage of a permanent programmable memory, in particular of the EPROM type, from an external source of direct voltage, comprising means for generating a reference voltage.

0006According to the invention, this device further comprises means for duplicating said reference voltage arranged according to a structure of voltage and current mirror and generating the programming voltage at output, and a follower MOS transistor whose drain and source are respectively connected to the external DC voltage source and to the output of said duplicating means and whose gate is connected to a predetermined internal node of said means for generating a reference voltage.

0007Thus, with the device according to the invention, there is a programming voltage delivered by a generator having a considerably reduced output impedance compared to the devices of the prior art by the use of duplication means implementing a mirror structure. The negative feedback loop produced by the link between the gate of the follower transistor and the reference generation means also contributes to stabilizing the programming voltage. In practice, this loop has a high negative gain compared to variations in the output voltage. This provides self-adaptation of the device according to the invention to variable charging current conditions.

0008According to an advantageous version of the invention, the means for generating a reference voltage comprise a first MOS transistor whose source is connected to the external DC voltage source and a second MOS transistor whose drain is connected to ground, a first , a second and a third resistive element connected in series between the external DC voltage source and the ground, the gate of the first MOS transistor being connected to a junction node between the first and second resistive elements while the gate of the second MOS transistor is connected to a junction node between the second and third resistive elements, and the duplicating means comprise a first mirror MOS transistor whose drain and source are respectively connected to the drain of the first MOS transistor and to the source of the second MOS transistor of said means for generating a reference voltage.

0009According to a preferred embodiment of the invention, the duplication means further comprises a second mirror MOS transistor whose gate is connected to the gate of the first mirror MOS transistor and whose source constitutes the output of said duplication means, and a third mirror MOS transistor whose gate, source and drain are respectively connected to the gate of the first MOS transistor of the generation means, to the external DC voltage source and to the drain of the second mirror MOS transistor.

0010According to another aspect of the invention, the method for generating a programming voltage of a permanent programmable memory, in particular of the EPROM type, from an external source of direct voltage, comprising a first step for generating a reference voltage from a voltage delivered by said external source of direct voltage, implemented in the device according to the invention, is characterized in that it further comprises a second step to duplicate the reference voltage and generate the programming voltage, and a third step to stabilize the programming voltage.

0011According to a preferred form of implementation of the method according to the invention, the third stabilization step includes a feedback step in which the programming voltage is controlled by said reference voltage.

0012In addition, the duplication step includes a reference current and voltage mirror operation.

0013The device according to the invention can be integrated into permanent programmable memories, in particular of the EPROM type, in which the method according to the invention can also be implemented.

0014Other features and advantages of the invention will become apparent in the description below. In the accompanying drawings by way of nonlimiting examples:<ul id="ul0001" list-style="dash"><li>Figure 1 is a diagram of a generator device representative of the prior art;</li><li>FIG. 2 is a diagram of an embodiment of a generator device according to the invention; and</li><li>Figure 3 is a diagram of another embodiment of a generator device according to the invention.</li></ul>

0015We will now describe a practical embodiment of the invention with reference to Figures 1 to 3.

0016The device 10 according to the invention comprises, with reference to FIG. 2, a first stage ensuring the generation of a reference voltage from a direct voltage Vpp delivered by an external source of direct voltage (not shown). This first stage corresponds to the generator assembly 1 shown in FIG. 1 and already known in the prior art. Such a circuit 1 comprises first, second and third resistive elements R1, R2, R3 connected in series between a point at the potential of the external DC voltage source Vpp and the ground, a first MOS transistor TA whose source is placed at potential Vpp and a second MOS transistor TB whose drain is connected to ground and whose source is connected to the drain of the first MOS transistor TA. The gate of the first transistor TA is connected to a junction node between the first R1 and second R2 resistive elements, while the gate of the second MOS transistor TB is connected to a junction node between the second R2 and third R3 resistive elements.

0017The first and second MOS TA, TB transistors are channel transistors <u>p</u> produced by implantation and the substrate of which is connected to the source in order to minimize the threshold voltages.

0018It is easily shown that this circuit 1 generates an output voltage Vs substantially equal to <maths id="math0001"><math display="inline"><mrow><msub><mrow><mtext>V</mtext></mrow><mrow><mtext>pp</mtext></mrow></msub><mtext> * (R1 + R3) / (R1 + R2 + R3)</mtext></mrow></math><img file="EP0538121A1_D0001.tif" /></maths> , which is independent of the manufacturing parameters of the circuit as long as the two transistors TA, TB remain saturated. The output voltage of circuit 1 is hereinafter considered as reference voltage.

0019In the device according to the invention, with reference to FIG. 2, a duplication circuit 20 is placed downstream of the generator circuit with the aim of duplicating the reference voltage without creating an internal load for the generator. It is thus possible to reduce the sensitivity of the output voltage to possible variations in load current.

0020The duplication circuit 20, which implements the known concept in voltage and current mirror electronics, comprises a first mirror MOS transistor 14 inserted between the two first and second MOS transistors TA, TB of the reference voltage generator, a second mirror MOS transistor 16 whose gate is connected to the gate of the first mirror MOS transistor 14 and whose source is at the potential of the output voltage Vp, and a third mirror MOS transistor 15 whose source is at potential Vpp, the gate connected to the gate of the first MOS transistor TA and the drain connected to the drain of the second mirror MOS transistor 16. The drain and the source of the first mirror MOS transistor 14 are respectively connected to the drain of the first MOS transistor TA and to the source of the second MOS transistor TB.

0021The first and second mirror MOS transistors 14, 16 are transistors produced by channel implantation <u>not</u> while the third mirror MOS transistor 15 is a transistor implemented by channel implantation <u>p</u>. It should be noted that the second and third mirror MOS transistors 15, 16 have their respective substrates connected respectively to their source and their drain in order to minimize their threshold voltage.

0022The device 1 according to the invention comprises a native channel follower MOS transistor 12 <u>not</u> whose drain and source are respectively connected to the potential Vpp of the external DC voltage source and to the load supplied by the device according to the invention and represented schematically by an impedance 11. This load is subject to the potential difference Vp stabilized. The gate of the follower transistor 12 is connected at a predetermined point N to the source of the first MOS transistor TA of the reference voltage generator. The connection at this point N ensures the closure of a negative feedback loop of the programming voltage Vp, of which a numerical simulation has shown remarkable stability.

0023For example, in an effective embodiment of the device according to the invention, a generator output resistance equal to 2.7 ohms and a variation in the programming voltage equal to only 81 mV are obtained by computer simulation. typical load current from 0 to 30 mA.

0024The generator device according to the invention can of course be associated with other circuits placed upstream or downstream. By way of example and with reference to FIG. 3, it is possible to provide, within a generator device 30, the addition upstream of a circuit 31 for controlling the supply voltage supplied to the reference voltage generator. This control circuit 31 can for example comprise a symmetrical mounting of two arms of MOS transistors 33a, 34a; 33b, 34b, each arm comprising a first channel MOS transistor<u>not</u> controlled respectively by a control signal S and by its logic inverse generated by an inverting logic gate 35, and a second channel MOS transistor <u>p</u> the gate of which is connected to the drain of the corresponding transistor of the other arm, the latter two transistors each having their substrate connected to their source.

0025The junction point of the two transistors 33b, 34b of the second arm of the control circuit 31 is connected to a first end of a network 32 of resistors R′1, R′2, R′3 implanted in the substrate of the circuit and constituting the three resistors necessary for the reference voltage generator described above. The remaining part of the generator device 30 which includes the duplication stage and the follower transistor is identical to the assembly of FIG. 2 described above.

0026Of course, the invention is not limited to the examples which have just been described and one can imagine many other arrangements and applications without departing from the scope of the invention.

0027Thus, it is possible to envisage various embodiments of the resistive elements included in the reference voltage generator. Furthermore, the device according to the invention can be associated with other shaping or protection circuits according to the constraints specific to the host memory and to its conditions of use.