Arrangement for controlling shared-buffer-memory overflow in a multi-priority environment.

Technical Field

0001The invention relates generally to packet-switching systems and relates specifically to shared-buffer-memory-based ATM switching systems.

Background of the Invention

0002The Asynchronous Transfer Mode (ATM) packet-switching technique is becoming the standard for switched broadband ISDN (BISDN) applications. Of the various ATM switch architectures that have been proposed, the shared-buffer-memory-based architecture appears most promising. In this architecture, incoming ATM cells (the packets) destined for different output ports are buffered on queues that correspond to those ports and that share a common memory. The cells are later retrieved from the queues for transmission on their destination ports, a cell at each port at a time.

0003To implement the queues, it is not practical to use a buffer memory of unlimited size, and hence the possibility of memory overflow must be taken into consideration in the design of the ATM switch. A most efficient approach to handling overflow is disclosed in published international patent application WO 91/04624. This approach initially allows the output port queues to completely consume the buffer memory. Thereafter, when an additional incoming ATM cell is received for which there is no room in the buffer memory, the lengths of the output port queues are compared to determine which is the longest. An ATM cell is discarded from the head of the longest queue, and the vacated memory space is allocated to the just-incoming ATM cell.

0004The ATM standard allows for different ATM cells to have different priorities. The abovementioned international patent application does not take multiple priorities into consideration. However, others do. For example, H. Kuwahara et al., "A Shared Buffer Memory Switch for an ATM Exchange", IEEE International Conference on Communications, Vol. 1 (June 11-14, 1989),pp.4.41-4.4.5, teach that, in a multiple-priority environment, each output port of the ATM switch has associated therewith not one, but a plurality of queues, each for buffering ATM cells of a different priority that are destined for that output port. They propose to deal with the possibility of buffer-memory overflow by allowing each queue to reach only a predetermined maximum size and thereafter discarding any additional incoming ATM cells destined for storage on any queues that have reached that maximum size. Unfortunately, this approach may result in ATM cells being discarded even while empty storage space exists in the buffer memory. It therefore lacks the efficiency of the approach described in the abovementioned international application.

Summary of the Invention

0005This invention is directed to solving these and other disadvantages of the prior art. As in the prior art, a shared-buffer-memory-based switch in a multiple-priority environment has a plurality of queues for each output port, a different queue for cells of each priority. According to the invention, the queues are initially allowed to completely consume the buffer memory, but thereafter, when an additional incoming cell is received for which there is no room in the buffer memory, the lengths of all of the queues of each output port are individually summed and compared to determine which port has the greatest total number of buffered cells, and an ATM cell is discarded from the lowest-priority non-empty queue of that port. The incoming cell is then stored in the memory space vacated by the discarded cell.

0006This approach to handling buffer-memory overflow in a multiple-priority environment brings the efficiency advantages of the approach disclosed in the abovementioned international application to the multiple-priority environment Yet, at the same time, it does not either favor or penalize any port on account of the priority of the cells that are queued up for that port. Rather, it introduces fairness among the ports, by ensuring that the port which is most responsible for the occurrence of the overflow is the one penalized by having one of its cells deleted, irrespective of that cell's priority.

0007These and other advantages and features of the invention will become apparent from the following description of an illustrative embodiment of the invention considered together with the drawing.

Brief Description of the Drawing

0008<ul id="ul0001" list-style="none"><li>FIG. 1 shows an ATM switch module embodying an illustrative example of the invention;</li><li>FIG. 2 shows contents of the buffer memory of the ATM switch module of FIG.1;</li><li>FIG. 3 shows queue length counters of the control of the ATM switch module of FIG. 1; and</li><li>FIG. 4 shows a buffer memory overflow procedure of the control of the ATM switch module of FIG.1.</li></ul>

Detailed Description

0009FIG. 1 shows a shared-buffer-memory-based ATM switch module 1. Such switches are well known in the art. An illustrative example thereof is disclosed in WO 91/04624. Module 1 comprises one or more input ports 7 over which module 1 receives incoming ATM cells. Individual ATM cells can be of any one of a plurality (0-M) of priorities. Input ports 7 are connected to input and output circuitry (I/O) 10 which couples input ports 7 to a control 14, a buffer memory 12, and to output ports 0-N. I/O 10 illustratively comprises phase-alignment circuitry, serial-to-parallel and parallel-to-serial shift registers, and multiplexers and demultiplexers. Copies of header portions of incoming ATM cells received from input ports 7 are sent by I/O 10 to control 14, and the cells are sent by I/O 10 to buffer memory 12 for storage.

0010Buffer memory 12 is shown in FIG. 2. It comprises one or more RAMs that implement a plurality of queues 100 for each output port 0-N. For every individual one of the output ports 0-N, buffer memory 12 provides a separate queue 100 for each one of the ATM cell priorities 0-M. While FIG. 2 suggests that queues 100 are implemented as physical queues, alternatively they may be implemented as logical queues in the form of linked lists or some other data structures. To distinguish between the various queues 100, numerical designations 100-i-j are used in FIG. 2, where i identifies the one of the output ports 0-N with which the queue is associated, and j identifies the ATM cell priority to which the queue corresponds.

0011Returning to FIG. 1, control 14 controls storage of incoming ATM cells in buffer memory 12 and transmission of stored ATM cells at output ports 0-N. Control 14 illustratively comprises a queue processor, a pointer RAM, an output-port counter, and queue-length counters 200 shown in FIG. 3. Counters 200 include one counter 200 for each queue 100. To distinguish between the various counters 200, numerical designations 200-i-j are used in FIG. 3, where i and j have the same meaning as in FIG. 2.

0012Based on the header of an incoming ATM cell, received from I/O 10, control 14 determines the priority and the destination output port of that cell, and then causes the cell to be stored in the corresponding queue 100 in buffer memory 12 and increments that queue's corresponding counter 200. Control 14 also periodically accesses the highest-priority non-empty queue 100 of the one of the output ports 0-N that is identified by the present count of the output-port counter, retrieves therefrom an ATM cell that is at the head of the queue, decrements that queue's corresponding counter 200, and causes I/O 10 to transmit the retrieved cell on the corresponding one of the output ports 0-N.

0013Control 14 allows queues 100 to fully occupy buffer memory 12, in the conventional manner. If an incoming ATM cell is received while buffer memory 12 is fully occupied, buffer-memory overflow occurs. Control 14 deals with the overflow by executing the procedure of FIG. 4. This procedure is illustratively implemented either in hardware or in memory-stored software.

0014Upon detecting the overflow, at step 400, control 14 sums the counts of queue length counters 200 individually for each one of the output ports 0-N, at step 402. This gives control 14 a count of the number of ATM cells that are queued up for each one of the output ports 0-N. Control 14 then compares the sums, at step 404, to determine which one of the output ports 0-N has the most ATM cells queued up, and selects that port, at step 406. Control 14 uses queue-length counters 200 of queues 100 of the selected port to select the lowest-priority non-empty queue 100 of the selected port, at step 408. Control 14 then deletes an ATM cell from the head of the selected queue 100, at step 410. The deletion frees space in buffer memory 12 for the incoming ATM cell whose receipt resulted in the overflow condition. Controller 14 then continues with conventional processing, at step 412, which includes storing the incoming ATM cell in the storage space vacated by the deleted cell and appending that storage space to the tail of the queue 100 to which the incoming ATM cell corresponds.

0015Of course, it should be understood that various changes and modification to the illustrative embodiment described above will be apparent to those skilled in the art. For example, the invention need not be used in conjunction with ATM cells, but may be used in conjunction with any buffered communications, including other packet types. Also, instead of using separate counters for each queue, a single counter may be used for each output port which keeps a count of the total number (i.e., the sum) of cells queued up for the corresponding port in all of that port's queues. A flag per queue in a bit field may then be used to indicate the empty-not- empty status of individual queues. Such changes and modifications can be made without departing from the spirit and the scope of the invention and without diminishing its attendant advantages. It is therefore intended that all such changes and modifications be covered by the following claims.