Wireless data transmission method on a data carrier.

0001The invention relates to a method for the wireless transmission of data to a data carrier having a semiconductor circuit, in particular a chip or IC card, and a circuit arrangement for carrying out this method.

0002In recent years, so-called chip cards or IC cards have increasingly been used, which are to be understood as data carriers which include both the known credit cards for cash dispensers, card telephones and other communication devices as well as identification cards for access control of security-sensitive areas. Such IC cards contain a mechanically protected integrated semiconductor circuit with a non-volatile memory that contains personal and / or non-personal data. Control logic is required to read out the stored data and - if necessary in a modified form - to read in data. As a rule, no separate power supply is provided for the circuit accommodated on the IC card, but the power supply required for reading out the information is carried out wirelessly, for example inductively or capacitively, by the respective reading device which reads out the stored information. At the same time, the data is also transmitted wirelessly by suitable modulation of the voltage supply, so that the circuit can transmit data to the reader, for example by field damping.

0003The present invention has for its object to provide a method for wireless transmission of data to a data carrier of the type mentioned, which is easy to carry out and requires little energy for operation. Another object is to provide a circuit arrangement for performing this method.

0004The first-mentioned object is achieved by the characterizing features of patent claim 1.

0005According to this, the essence of the invention is to carry out an amplitude keying for data transmission by means of the high-frequency field. Here, the information lies in the number of periods of the high-frequency field between two transmission breaks. This enables various agreements to be made for the data to be transmitted. In addition to the transmission of the logic levels "0" and "1", command commands or start sequences can be transmitted. The fact that the clock signal is at rest during the transmission pauses minimizes the energy consumption. The transmission method according to the invention permits very simple control of the transmitter, after which a square-wave signal is sufficient to control the transmitter coil.

0006According to an advantageous further development of the method according to the invention, for the purpose of assigning the number of periods of the periods of the radio-frequency field transmitted between two transmission pauses to the logic levels or the command instructions, this number of periods is compared with disjoint number ranges, a logic level or a command instruction being assigned to each number range. This results in a particularly secure transmission method, since in order to identify the information on the basis of the number of periods, it does not have to correspond exactly to a single numerical value, but rather only has to be assignable to a specific, contiguous range of numbers.

0007In a further preferred embodiment of the invention, the transmission pauses are short compared to the transmission times, so that only a storage capacitor with low capacitance is required to bridge the voltage failure.

0008The clock signal required for the counter and the control unit can, on the one hand, be derived from the received high-frequency field according to one embodiment of the invention, or, on the other hand, can be obtained from an oscillator signal in another embodiment.

0009The other object of the invention is achieved by the characterizing features of claims 6 and 7.

0010According to claim 6, the receiving unit controls both a voltage detector and a clock generating device. The voltage detector detects the transmission pauses, while the clock generating device generates a clock signal for a counter and the control unit from the received signal. In addition, the voltage detector controls the clock generating device as well as the counter and an evaluation unit. This evaluation unit generates the data from the counter readings supplied to it by the counter and feeds them to the control unit. The data are then stored in a memory, for example an EEROM memory.

0011In contrast, according to claim 7, the clock signal is derived from an oscillator signal, the voltage detector only controlling the clock generating device to switch it on and off.

0012Since only one storage capacitor with low capacitance is required to bridge the voltage failure, according to a further embodiment of the circuit arrangement according to the invention, this capacitor is designed as an on-chip capacitor with the semiconductor circuit as an integrated circuit.

0013The method according to the invention is to be illustrated and explained below using an exemplary embodiment in conjunction with the drawings. Show it:<dl id="dl0001"><dt>Figure 1</dt><dd>2 shows a block diagram of a data carrier with an exemplary embodiment of the circuit arrangement according to the invention,</dd><dt>Figure 2</dt><dd>Pulse diagrams to explain the function of the data transmission according to the invention,</dd><dt>Figure 3</dt><dd>another pulse diagram to explain the operation of the circuit according to the invention,</dd><dt>Figure 4</dt><dd>further pulse diagrams to explain the operation of the method according to the invention and</dd><dt>Figure 5</dt><dd>2 shows a block diagram of a variant of the exemplary embodiment according to FIG. 1.</dd></dl>

0014FIG. 1 shows the block diagram of an integrated circuit 1, as implanted in an IC card, for example. The reading out or control device 9 with a high-frequency transmitter 9 a generating a high-frequency field 10 is used for wireless reading (reading mode) of the information stored in an EEPROM memory 8. Data can also be written into said memory 8 (write mode) via this reader 9, for which purpose the circuit arrangement according to the invention is used, the exemplary embodiment of which is designated by reference number 1a. This circuit arrangement 1a for carrying out the method according to the invention decrypts the information contained in the radio-frequency field 10 and feeds it to the control unit 7, for example a microprocessor, which is why this circuit arrangement 1a can also be referred to as a decoder. The functional units required for reading are not shown in FIG. 1.

0015The IC card is inductively coupled to the reader 9 via the radio-frequency field 10 for energy and data transmission. For this purpose, a receiving unit 2 contains a resonance circuit 2a, the output signal of which is fed to a voltage supply unit 11, which in turn provides the required operating voltage for the individual components of the IC card.

0016In addition, the output signal of the receiving unit 2 is fed to both a voltage detector 3 and a clock generating unit 4. The clock generation unit 4 generates the system clock from the received signal and feeds it to a counter 5 and the control unit 7. The voltage detector 3, the clock generating unit 4, the counter 5 and an evaluation unit 6 form the above-mentioned decoder 1a, while this decoder 1a together with the receiving unit 2, the voltage supply unit 11, the control unit 7 and the memory 8 form the integrated circuit 1 of the IC - Form card.

0017Instead of deriving the clock from the received high-frequency field 10, it can also be generated by means of an oscillator 4a according to FIG. 5. For this purpose, only the oscillator signal is supplied to the clock generating unit 4, a direct connection to the receiving unit 2 is therefore not necessary.

0018The method according to the invention consists of clocking the high-frequency field 10 for the transmission of data from the transmitter 9 to the IC card, that is to say switching it off and on again at certain intervals, the coded information in terms of the number of transmitted periods of the high-frequency field 10 between two Broadcasting breaks. For example, the agreement can be made that a logical "0" should be present for transmission of 8 to 15 periods and a logical "1" for transmission of 16 to 23 periods. The decoder 1a can thus decrypt the transmitted information by counting the periods transmitted between two transmission pauses. Additional codes for transmitting additional information are also conceivable, for example for start sequences or command commands. It is advantageous in this method to choose the OFF time short compared to the ON time, for example, at a field frequency of 125 kHz, an OFF time comprising 10 periods is 80 µsec.

0019Diagrams a to d of FIG. 2 show the transmission of a "0" sequence. Here, diagram a shows the high-frequency field 10 generated by the transmitter 9a of the reading device 9, which comes about by activating the transmitter coil with a square-wave signal. Thereafter, the transmitter 9a is switched off after 10 periods and switched on again after 10 periods. So a break lasts 10 periods. Diagram b shows the voltage curve at the resonant circuit 2a of the receiving unit 2. After this, the resonant circuit voltage is constant during the transmission times, but assumes a damped course during the transmission pauses. Diagram c now shows the envelope curve rectified from the curve according to diagram b for detecting the switch-off times of the high-frequency field 10. The switch-off times are fed via a line 12 (FIG. 1) as a reset signal to the counter 5 and as a latch signal to the evaluation unit 6 . Furthermore, this signal is used by the clock generating device 4 to stop the clock via a line 18 according to FIG. 1, see also FIG. 3, diagrams a and d, where the times t 1, t 3 and t 4 mark these switch-off times. A buffered supply voltage is generated from the pulsating DC voltage according to the diagram c in FIG. 2 by means of the voltage supply unit 11 and the on-chip capacitor C, as shown in diagram d. The voltage failure during the transmission pauses can thus be brought about with the on-chip capacity, since no clock is generated during the transmission pauses and only the counter readings of the counter 5 accumulated at the time the high-frequency field is switched off need to be recorded in the evaluation unit 6. The integrated circuit 1 of the IC card thus manages without external elements, for example backup capacitors for the voltage supply.

0020As has already been mentioned, the counter readings of the counter 5 up to a switch-off time of the high-frequency field 10 are stored in the evaluation unit 6 for later evaluation. For this purpose, the counter 5 according to FIG. 1 is connected to the evaluation unit 6 via lines 14. If the high-frequency field 10 is used again - see times t₂, t₄ and t₆ according to FIGS. 3a and d -, the counter 5 is reset and starts counting up again.

00213a shows again the principle of data transmission by means of the high-frequency field 10. Thereafter, the high-frequency field 10 is switched off at a time t 1 and is only switched on again, for example after 10 periods at the time t 2. The duty cycle is then, for example, 16 to 23 periods, which is why this means a transmission of a logical "1". At time t₃ the field is switched off again for 10 periods, so that it can be detected again by the receiving unit 2 at time t₄. Now, however, to transmit a logical "0", the radio frequency field remains switched on for only 8 to 15 periods, that is to say it is switched off at the time t₅ and is only switched on again after 10 further periods, that is to say at the time t₆. The control signal (CLK-ENABLE) for the clock belonging to this transmission of the logical “1” and “0” is shown in FIG. 3d, according to which no clock signal is generated during these transmission pauses.

0022The integrated circuit 1 according to FIG. 1 must distinguish between two operating modes, namely the read mode and the write mode. This is what the<maths id="math0001"><math display="inline"><mrow><mover accent="true"><mrow><mtext>RD</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0502518A2_D0001.tif" /></maths>/ WR signal, which is fed via a line 15 from the evaluation unit 6 to the control unit 7. Thereafter, the control unit 7 must be informed whether the data stored in the memory 8 must be sent to the reader 9 or whether data can be received from this reader 9. Begins to transmit again after an interruption of the transmitter 9a at a time t 1, the counter is reset to 0 and the signal on line 15 is set to H level. This means that the control unit 7 is ready to receive data. If the high-frequency field 10 is not switched off again, the counter counts to the counter reading 24 and then resets the H level on line 15. Since the transmission of a logical "1" value can take a maximum of 23 periods, no information can be transmitted after 24 periods. This is shown in Figures 4a and b. However, if the high-frequency field 10 switches off at the time t 3 according to FIG. 3, the counter reading reached up to this point in time is recorded in the evaluation unit 6. If the clock turns on again at time t₄, this counter reading is further processed by now detecting a logical "1". A strobe command is now generated on line 17, so that the information present on the data line 16 according to FIG. 3b is transferred from the control unit 7 into the memory 8.

0023The method according to the invention permits reliable transmission of the data even with changing distances to the reading device 9 on the integrated circuit 1. In particular, the frequency used is not critical, so that it can be selected from a wide frequency range.

0024The integrated circuit 1 for an IC card shown in FIG. 1 can also be used in a variety of ways in identification systems, further functions not shown in FIG. 1, for example a clock, being installable.

0025As has already been pointed out, the current consumption for the integrated circuit 1 according to FIG. 1 is very low, in particular if the circuit is implemented as a CMOS circuit. Thus, the current state of the circuit can be kept with a relatively small on-chip capacitor during the pauses in transmission.