Pager.

The present invention relates to a pager, in particularly to a pager which receives a message of a set phrase transmitted in code and displays it as the set phrase by display thereof.

Fig. 1 shows a block diagram of a pager of the conventional type which has a display and regenerates a set phrase on the display by receiving a set phrase designation character (e.g., numeral) in the message data.

Hitherto, with this kind of the pager, as shown in Fig. 1, modulated signal a which has been received by antenna 1 is demodulated by radio section 2, and is sent out as demodulated signal c from radio section 2 to decoder 3. Here, radio section 2 operates intermittent reception according to control signal b which comes from decoder 3 for battery saving .

Decoder 3 collates a selective address code included in demodulated signal c with that of the pager which is read out from EEPROM (electrically erasable programmable read only memory)15. When these data coincide, decoder 3 informs microprocessor 4 of the detection of the assigned selective address code by means of interruption signal d through address bus e and data bus f. Thereafter, decoder 3 corrects errors of message data which follow the selective address code in demodulated signal c, and then transmits only message data bits to microprocessor 4 with the assistance of interruption signal d through address bus e and data bus f. An appropriate selective address number is assigned to each pager, and the selective address code of each pager is produced by BCH (Bose-Chaudhuri-Hocquenghem) coding for each selective call number.

On receiving detection information of a selective address code from decoder 3, microprocessor 4 stores the detection information in a RAM (not shown) in microprocessor 4 or in RAM 7. Also microprocessor 4 decides whether data which is successively transmitted after the detection information from decoder 3 is message data or a selective address code.

When the data from decoder 3 is message data, microprocessor 4 stores the message data in the buffer area of the RAM in microprocessor 4 or of RAM 7. Microprocessor 4 processes this storing operation according to reference clock signal g which is inputted from reference clock 13 through decoder 3.

When the data is a selective address code, then microprocessor 4 stops receiving of the data. In the case of message data, microprocessor 4 starts MPU operation clock 14 and processes the data stored in the above buffer area by using MPU operation clock 14. The data processed by microprocessor 4 is stored as a message (character data) in the message memory area of RAM 7. Further, when microprocessor 4 detects a set phrase designation character included in the data which is stored in the buffer area, microprocessor 4 converts the set phrase designation character portion to the set phrase of the designated number. This set phrase to be converted is stored in advance in EEPROM 15.

When the processing of the received message data is finished, microprocessor 4 drives speaker 10, LED (light emitting diode) 11 or vibrator 12 through driver 9 and alerts the carrier of this pager. At the same time, microprocessor 4 displays the received message on LCD (liquid-crystal display) 5. Designation of speaker 10, LED 11 and vibrator 12 for alerting device is set by recording the device mode in EEPROM 15 through function switch 8. The message stored in the message memory area of RAM 7 can be displayed again on LCD 5 by function switch 8.

In other words, the set phrase function of the conventional pager acts to display the set phrase of the number designated by the set phrase designation character based on EEPROM 15 on LCD 5, when the set phrase designation character is received. In this case, since recording of the set phrase into EEPROM 15 is conducted by means of writing terminal 16 of EEPROM 15, an input device other than this pager is additionally needed.

The conventional pager of this kind has no recording function per se for recording the set phrase, so another writing device is needed for recording the set phrase. Since this writing device is very costly compared with the pager per se and its handling is also a problem, there is a problem that the use of an input device is not popular with users.

Pagers are usually delivered for users after their preferred set phrases have been recorded thereinto. When the user want to add other set phrase, it is necessary to ask the paper system operator to record the new set phrases. Accordingly, the adding of new set phrases is very inconvenient for the user.

SUMMARY OF THE INVENTION

The present invention has been developed to remove the problems of the conventional type pagers described above, and its object is to provide a pager which enables the user to record new set phrases as desired, thereby enabling the user to improve the usability thereof.

In order to achieve the above-mentioned object, the pager of the present invention comprises a detection means to detect a selective address code assigned to the pager, a message processing means to process a message data which follows said selective address code when said selective address code is detected by means of said detection means, a message memory which stores a message processed by said message processing means, and a set phrase memory which stores a plurality of set phrases, and further comprises a designation means which designates one of the messages stored in said message memory and a recording means which records the message designated by said designation means as a set phrase into said set phrase memory.

Also in the pager of the present invention, said designation means may be operated by a function switch and is able to designate a portion of the received message, and said recording means also may be started by a function switch which is operated by touching the menu screen on the display showing delete, protect and record.

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a block diagram of a pager of a conventional type which has a display and display a set phrase on the display by receiving a set phrase designation character in the message data.

Fig. 2 shows a block diagram of an embodiment of the pager of the present invention.

Fig. 3 shows a detailed block diagram of decoder 3 which is shown in Fig. 2.

Fig. 4 shows a flow chart of a message processing operation to be conducted by microprocessor 17 shown in Fig. 2.

Fig. 5 shows a time chart of operation of decoder 3 and microprocessor 17 shown in Fig. 2.

Fig. 6 is a view which shows the recording area of set phrase in EEPROM 15 shown in Fig. 2.

Fig. 7 is a view which shows examples of conversion of the phrases.

Fig. 8 is a view which shows recording operation of set phrase with reference to the embodiment shown in Fig. 2.

Fig. 9 shows a flow chart of operation of the embodiment shown in Fig. 2.

Fig. 10 is a view which shows the format of a POCSAG signal to be used for calling of the pager.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Next, a preferred embodiment of the present invention will be described with reference to the drawings.

Fig. 2 shows a block diagram of an embodiment of the pager of the present invention. This pager is of a similar composition to that of the conventional type shown in Fig. 1, except for a recording function which records a message on the display screen into EEPROM 6 using microprocessor 17 which provides with the recording function in addition to the function of microprocessor 4 of conventional pager. The same reference numbers are assigned for function blocks having the same functions in Figs. 1 and 2.

When the recording of a new set phrase is ordered through function switch 8, microprocessor 17 records the message designated by the function switch 8 among the messages stored in the message memory area of RAM 7 into EEPROM 6 as a set phrase. Therefore, users can easily record new set phrases as desired, by transmitting the set phrase by telephone to this pager.

Fig. 3 is a block diagram of decoder 3 shown in Fig. 2. Bit synchronizing circuit 31 of decoder 3 generates regenerated clock m from demodulated signal c and a reference clock signal from oscillation circuit 39. Bit synchronizing circuit 31 outputs regenerated clock m to synchronization control circuit 32, preamble and SC (synchronizing signal) detection circuit (hereinafter referred to as "synchronizing signal detection circuit") 33, BCH (Bose-Chaudhuri-Hocquenghem) error correction circuit 34, selective call code detection circuit 35 and baud rate monitor circuit 36.

Synchronization control circuit 32 controls battery saving operation which operates intermittent reception of radio waves. Synchronization control circuit 32 is in the battery saving mode while it does not receive any POCSAG (Post Office Code Standardization Advisory Group) signal, and starts continuous reception upon receiving preamble detection signal i from synchronizing (SC) signal detection circuit 33 or baud rate detection signal k from baud rate monitor circuit 36. Synchronization control circuit 32 resumes battery saving operation by receiving synchronizing signal detection signal j sent from preamble and SC signal detection circuit 33 after detection of the synchronizing signal, and successively receives signals in accordance with the timing shared to the group to which the pager belongs. Further, when synchronization control circuit 32 receives detection signal o which is generated by the coincidence of the selective address code at selective address code detection circuit 35, radio section 2 keeps receiving the following message data. Furthermore, when synchronization control circuit 32 starts battery saving, it outputs battery saving signal h to selective address code detection circuit 35 and battery saving control signal b to radio section 2.

Preamble and SC signal detection circuit 33 performs a sampling of demodulated signal c from radio section 2 by means of regenerated clock m from bit synchronizing circuit 31, and generates preamble detection signal i by detecting a preamble signal and outputs preamble signal i to synchronizing control circuit 32. Additionally, when preamble and SC signal detection circuit 33 detects a synchronizing signal in succession to the preamble signal, it generates synchronizing signal detection signal j and outputs it to synchronization control circuit 32.

BCH error correction circuit 34 performs an error correction of demodulated signal c which comes from radio section 2, and outputs message data p to microprocessor 17 by way of MPU interface circuit 37 and data bus f.

Selective address code detection circuit 35 performs collation of selective address code in demodulated signal c from radio section 2, in accordance with the timing of battery saving signal h from synchronization control circuit 32. When coincidence of the received selective address code in demodulated signal c and the selective address code of the pager is detected by collation, selective address code detection circuit 35 outputs coincidence detection signal o to synchronization control circuit 32. Simultaneously, selective address code detection circuit 35 outputs coincidence detection signal o to microprocessor 17 through MPU interface circuit 37 and data bus f. In addition, the selective address code of the pager is set by microprocessor 17 in selective address code detection circuit 35 through MPU interface 37, data bus f and selective address code setting signal q.

Baud rate monitor circuit 36 compares regeneration clock m from bit synchronizing circuit 31 with demodulated signal c from radio section 2 and detects whether it is a baud rate of the POCSAG signal to be received. Baud rate detection signal k sent from baud rate monitor circuit 36 to synchronization control circuit 32 is used as an activation factor for starting operation for receiving of the synchronizing signal in the condition of the battery saving operation state. And this signal k is also used, as well as the preamble signal, for canceling battery saving operation.

MPU interface circuit 37 outputs interruption demand signal n to interruption control circuit 38, when message data p from BCH error correction circuit 34 or coincidence detection signal o from selective call code detection circuit 35 is transmitted thereto. Interruption control circuit 38 outputs interruption signal d to microprocessor 4 when it receives interruption demand signal n from MPU interface circuit 37.

Oscillation circuit 39 passes reference clock signal from reference clock 13 to bit synchronizing circuit 31 as is and at the same time outputs it as reference clock signal g to microprocessor 17.

Fig. 4 is a flow chart showing message processing operation by microprocessor 17. Message processing operation will be described with reference to Fig. 4.

When interruption signal d which is generated by the detection of a selective address code is sent from decoder 3 (step 21), microprocessor 17 stores selective address code detection information from decoder 3 in RAM 7 (step 22). Further, when interrupt signal d from decoder 3 is message data (step 23), microprocessor 17 stores the data in a buffer area of RAM 7 (step 24). At this time microprocessor 17 performs the above processing in accordance with the operation clock i.e., output of oscillation circuit 39 transferred from reference clock signal g which is inputted from reference clock 13 through decoder 3.

Further, when interruption signal d from decoder 3 does not indicate reception of message data (step 23), that is, interruption signal d from decoder 3 shows detection of the selective address code, at that time microprocessor 17 stops receiving the data and starts MPU operation clock 14 (step 25). Thereafter, microprocessor 17 processes the data stored in the above buffer area in accordance with MPU operation clock 14 (step 26). Microprocessor 17 stores the processed data as a message (character data) in the message memory area of RAM 7.

Fig. 5 is a time chart along the operation of decoder 3 and microprocessor 17. Case (a) of Fig. 5 shows the timing of battery saving control signal b when no selective address signal of the pager is found in the received POCSAG signals. Case (b) shows the timing of battery saving control signal b when the selective address signal in the received POCSAG signals coincides with the selective address signal of the pager.

Further, case (c) shows the timing of interruption signal d after having received the selective address signal of the pager. Microprocessor 17 reads the message data from decoder 3 with this timing and stores it in the buffer area of RAM 7.

Moreover, case d shows the timing of MPU operation clock 14 which generates oscillation. In this oscillation timing chart, the high level portion represents the oscillation by the clock. Microprocessor 17 processes the data stored in the above buffer area with this timing in accordance with MPU operation clock 14 as the operation clock, and stores the processed data as a message (character data) in the message memory area of RAM 7.

Fig. 6 is a view showing recording area of set phrases in EEPROM 6 shown in Fig. 2. In set phrase recording area 6a of EEPROM 6, set phrases are recorded in each of the numbered areas corresponding to the set phrases. Namely, in the area corresponding to the set phrase number "01", set phrase "CALL OFFICE" is recorded. Also in the area corresponding to set phrase number "02", set phrase "URGENTLY CONTACT" is recorded. Further, in the area corresponding to set phrase number "03", set phrase "PLEASE PICK UP AT" is recorded. In the area corresponding to set phrase numbers "04", "05",----, no set phrases are as yet recorded.

Fig. 7 is a view showing two conversion examples of set phrases. Here the conversion examples are shown for the case in which the set phrases shown in Fig. 6 are recorded in the set phrase recording area 6a in EEPROM 6. As shown in Fig. 7 (a), when a row of characters such that "--01" is received, microprocessor 17 refers to set phrase number "01" in set phrase recording area 6a in EEPROM 6, and then displays set phrase "CALL OFFICE" on LCD 5.

Also as shown in Fig. 7 (b), when a row of characters such as "--03YOKOHAMA STATION" is received, microprocessor 17 refers to set phrase number "03" in set phrase recording area 6a in EEPROM 6, and then displays set phrase "PLEASE PICK UP AT YOKOHAMA STATION" on LCD 5.

Fig. 8 is a view showing set phrase recording operation according to the embodiment of the present invention, while Fig. 9 is a flow chart showing operation of the embodiment of the present invention. Operation of the embodiment of the present invention will be described with reference to the drawings Fig. 2 through 9.

When the display of LCD 5 is off and the pager is in a waiting mode (step 41), and then SW3 of function switch 8 (hereinbelow referred to as "switch SW3") is depressed, microprocessor 17 reads out the latest message from RAM 7 and displays it on LCD 5 [refer to Fig. 8 (a)] (step 42). Message number 1 is assigned to the top of the latest message. That is, the message "1:YOUR NEXT APPOINTMENT IS AT 9:00" is displayed on LCD 5. When a message is displayed on LCD 5, the pager enters the display waiting mode (step 43).

Whenever switch SW3 is depressed in this mode, successive pictures are displayed on LCD 5 (step 45). Further, received messages are stored in the message memory area of RAM 7 in order of reception, so when there is no successive picture, the next message is displayed on LCD 5, by depressing the switch SW3 [ refer to Fig. 8 (b) ] (step 44). That is, the next message "2:PLEASE RETURN TO YOUR OFFICE" is displayed on LCD 5. Further, when SW2 of function switch 8 (hereinbelow referred to as "switch SW2") is depressed, the preceding message is displayed on LCD 5 (step 46). At that time, if the prescribed time is passed, the display of LCD 5 turns off and the pager returns to the waiting mode (step 41).

When the SW1 of function switch 8 (hereinafter referred to as "switch SW1") is depressed while a message is displayed on LCD 5, the expression (MENU) is shown on LCD 5 [refer to Fig. 8 (c)] (step 47). This time the pager enters the menu selection waiting mode (step 48).

Here, a cursor on the screen of LCD 5 is moved by pressing down switch SW3 (step 49), and switch SW2 is depressed when the cursor comes to the position of DELETE, when it changes to the DELETE MODE. Also if switch SW2 is pushed down when the cursor is moved to the PROTECT position, then it becomes the PROTECT MODE. Further, when the cursor is moved to the PROGRAM position and then switch SW2 is depressed, it changes to the PROGRAM MODE [refer to Fig. 7(d)] (step 50). In this case, if switch SW1 is pressed down or it passed the prescribed time, then the display of LCD 5 goes off and the pager returns to the waiting mode (step 41).

When the screen shows the PROGRAM MODE, microprocessor 17 reads out the set phrase with the set phrase number "01" from RAM 7 and displays the set phrase on the second line of LCD 5 together with the set phrase number [refer to Fig. 8 (e)]. That is, on the second line of LCD 5, a set phrase such as "1:CALL OFFICE" is displayed. Now, although the set phrases are stored in set phrase recording area 6a of EEPROM 6, the read rate from EEPROM 6 is slow, so that microprocessor 17 copies the set phrases and set phrase numbers from set phrase recording area 6a of EEPROM 6 into RAM 7 at the time of power input to the pager. When the set phrase and set phrase number are displayed on LCD 5, then the pager enters the waiting mode for recording of a set phrase (step 51).

Whenever switch SW3 is depressed in this state, the set phrase stored in set phrase recording area 6a is displayed on LCD 5 (step 52). When no set phrase is recorded in set phrase recording area 6a, then only the set phrase number is displayed on LCD 5 [refer to Fig. 8 (f)].

If only this set phrase number is displayed on LCD 5 and then switch SW2 is depressed, a message such as "PLEASE RETURN TO" displayed on the first line of LCD 5 will be recorded in the blank line of set phrase number "04" [refer to Fig. 8 (g)] (step 53). That is, when switch SW2 is depressed, microprocessor 17 reads out the message displayed on the first line of LCD 5 from the message memory area of RAM 7, and writes said message into set phrase recording area 6a and the set phrase recording area of RAM 7. However, when there is a set phrase displayed on the second line of LCD 5 and then switch SW2 is pressed down, the message displayed on the first line of LCD 5 is superposed on the already recorded portion in set phrase recording area 6a. In this case, if the switch SW1 is pressed down or the prescribed time is passed, the display of LCD 5 goes off and the pager returns to the waiting mode (step 41).

In the case where a set phrase such as "PLEASE RETURN TO" is recorded by means of the above processing operation, in the position of set phrase number "04" in set phrase recording area 6a and thereafter a row of characters such as "--04YOUR HOME" is received, the microprocessor 17 refers to the set phrase number "04" of set phrase recording area 6a in EEPROM 6 and thus the set phrase such as "PLEASE RETURN TO YOUR HOME" is displayed on LCD 5 [refer to Fig. 8 (h)].

Fig. 10 is a view showing the format of the POCSAG signal to be used for calling a pager. In Fig. 10 (a), the POCSAG signal comprises a 576 bit preamble signal with a pattern such as "101010----", a synchronizing signal (SC) for synchronizing a code word, a selective address signal which shows a selective address code, a BCH coded message data of a message to be transmitted and batches.

In Fig. 10 (b), the batch consists of a 32 bit synchronizing signal (SC) provided at the top thereof and code words from CW1 to CW16 divided into eight groups which are intermittently received by each addressed pager of each corresponding group. Further, the code word comprises two types, one an address code word (paging number), the other a message code word (message data).

In Fig. 10 (c), code words are arranged in order from the highest rank bit (MSB : Most Significant Bit) to the lowest rank bit (LSB : Least Significant Bit), i.e., in order an information bit with 21 bits, a check bit with 10 bit and a parity bit.

This POCSAG signal is described in detail in "STANDARD MESSAGE FORMATS FOR DIGITAL RADIO PAGING" and "Post Office Code Standardization Advisory Group (POCSAG), Autumn 1980". POCSAG is a time sharing system, in which battery saving operation is effectuated to reduce the electric current consumption by the system so that each pager turns its receiving circuit on only within the time of transmitting duration shared for the group to which the pager per se belongs, and turns its receiving circuit off during the time shared by groups other than its own group.

Thus, arranging by means of the microprocessor 17 in such a way that, when the selective address code is detected by decoder 3 that it is for its own pager, the message signals which follow this selective address code can be processed and stored in the message memory area of RAM 7 and the message designated by the function switch 8 among the messages stored in said message memory area is able to recorded in set phrase recording area 6a of EEPROM 6 as the set phrase, then the user can record the message which the user transmitted, that is, the user can record the message which he wants to record as a set phrase. Thus it becomes possible to record the set phrase easily, and this function suits the user's requirement and improves of the usability of the system.

While certain representative embodiments have been described for the purpose of illustrating the invention, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit or scope of the invention.