Delay line calibration circuits

Calibration loops for a delay line (12'), for example, for digital phase locked logic circuitry for use in ascertaining the phase offset between a data signal and a local clock (10) and to produce a series of phase shifted clocks (f(i)'), are described. The calibration loops include a phase detector (14) coupled to receive as a first input the local clock applied to the delay line and as a second input the delay clock (f(n)') produced by the nth delay element (Dv) of an n element delay line. At least one of the delay elements (Dv) of the delay line is a variable delay element. The detector outputs a phase difference signal derived from the clocks applied at the first and second inputs. Control circuitry receives the phase difference signal from the detector and produces therefrom a corresponding control signal (CONTROL) which is applied to the at least one variable delay element to vary the delay through the delay line. Specific control circuitry embodiments are provided in the disclosure.