Image signal recording apparatus and methods.

This invention relates to image signal recording apparatus and methods, for example, in which a still image is recorded digitally in a pulse code modulation (PCM) audio recording area of a magnetic tape by an 8mm video tape recorder (VTR).

Several forms of apparatus are available for recording still video pictures on recording media, such as magnetic media. For example, an electronic still camera records video images on a still video floppy disk. Another such device is the 8mm VTR which is provided with a built-in camera.

Figure 1 illustrates a standard format employed by an 8mm VTR for recording signals on a magnetic tape 170. The tape 170 is wound circumferentially about a rotary head drum of the 8mm VTR to an angular extent of 211 degrees. The head drum includes a pair of diametrically opposed rotary heads which scan the tape 170 along helically extending paths in order to form obliquely extending recording tracks 171 on the tape 170. Each of the tracks 171 includes a video area 172 extending for 180 degrees of the 211 degree extent of each track 171. The VTR records frequency multiplexed signals in the video area 172 including frequency modulated (FM) luminance signals, sub-carrier chrominance signals which have been shifted to a lower frequency band, FM audio signals, and a plurality of pilot signals provided for tracking control. The remaining portion 173 of each track 171 extending for approximately 30 degrees is set aside for recording PCM audio signals digitized at 8 bits per sample and processed by non-linear quantization. The PCM audio signals are cross-interleaved for error correction, and synchronizing signals, parities and identification signals are added thereto prior to recording. A cue track 174 is recorded longitudinally on a first lateral edge of the tape 170 by a fixed head, and an audio track 175 is recorded longitudinally by another fixed head along the opposite lateral edge of the tape 170. The cue track 174 as well as the audio track 175 may be used to record cue or editing signals for locating previously recorded information.

Japanese published patent specification 58/164383 describes a technique for recording still pictures such as letter or character information by after-recording in the PCM audio area 173 to superimpose titles, casts or explanatory text on moving pictures recorded in the video area 172.

If it is desired to record a high resolution still picture with the use of the 8mm VTR by recording digitally in the PCM audio area of the tape 170, it is necessary to employ a relatively high sampling frequency and a suitable imaging device such as a charge coupled device (CCD) image sensor having a relatively large number of photoelectric converting elements. Such apparatus, referred to hereinafter as an "upper level system", is relatively complex and costly. Less expensive 8mm VTRs, referred to hereinafter as "lower level systems", employ CCD image sensors having a relatively smaller number of photoelectric converting elements so that a lower sampling frequency is used thereby.

Due to the disparity in data rates between the upper and lower level systems, it is difficult to realize interchangeability of recordings, so a tape recorded with the use of an upper level system may not be reproduced by a lower level system without processing the recorded signals, for example, by interpolation, in order to derive picture data having the necessary low data rate. An example of such an interpolation process is illustrated in Figure 2 wherein the picture data a₁, a₂, ... a₁₁₅₂ of each line of a first video signal are recorded by an upper level system and are to be combined by interpolation to form picture data b₁, b₂, ... b₇₆₈ in each line of a converted video signal having a data rate which is compatible with that of a lower level system. In the example of Figure 2, therefore, the ratio of the data rate of the upper level system to that of the lower level system is 6 : 4. The interpolation process is carried out by combining selected pairs of the data a₁, a₂, ... a₁₁₅₂ to form corresponding ones of the data b₁, b₂... byes. For example, pixel b₂ is obtained by calculating an average of the pixels a₂ and a3. Other interpolation formulae may instead be employed; for example, pixel b₂ may be derived instead as follows: <ul id="ul0001" list-style="none"><li>b₂ = (a₁ + 3a₂ + 3a3 + a4) /8</li></ul>

It will be appreciated that in order to carry out the necessary conversion of the video signals generated by the upper level system for reproduction by the lower level system as described above, a signal processing system must be provided having a memory capability in order to carry out the interpolation process. This results in increased complexity and cost of the lower level system.

According to the present invention there is provided an image data recording apparatus for recording first and second image data on a record medium, the first image data being obtained through sampling of image signals at a first data rate and the second image data having a second data rate lower than the first data rate such that the second image data may be reproduced by apparatus operating at the second data rate, the apparatus comprising: <ul id="ul0002" list-style="none"><li>data forming means for forming the second image data from the first image data;</li><li>data recording means for recording the second image data and at least a portion of the first image data in predetermined areas of said recording medium, the portion of the first image data recorded on said recording medium being selected such that the first image data may be derived by reproducing means operating at the first data rate from said second image data and said portion of the first image data; and area discriminating code recording means for recording area discriminating code data on said recording medium for identifying said predetermined areas in which said second image data and said portion of the first image data are recorded.</li></ul>

According to the present invention there is also provided a method of recording first and second image data on a recording medium, the first image data being obtained through sampling of image signals at a first data rate and the second image data having a second data rate lower than the first data rate such that the second image data may be reproduced by apparatus operating at the second data rate, the method comprising the steps of: <ul id="ul0003" list-style="none"><li>forming the second image data from the first image data;</li><li>recording the second image data and at least a portion of the first image data in predetermined areas of said recording medium, the portion of the first image data recorded on said recording medium being selected such that the first image data may be derived by reproducing means operating at the first data rate from said second image data and said portion of the first image data; and</li><li>recording area discriminating code data on said recording medium for identifying said predetermined areas in which said second image data and said portion of the first image data are recorded.</li></ul>

Embodiments of the invention can provide improved image signal recording apparatus and methods which enable relatively simple and low cost reproducing systems utilizing relatively low data rates to reproduce images recorded at relatively higher data rates.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: <ul id="ul0004" list-style="none"><li>Figure 1 illustrates a tape recording format employed by a known 8mm VTR;</li><li>Figure 2 is a diagrammatic view of a spacial array of pixel data for illustrating a method of forming pixel data having a relatively low data rate by interpolating other pixel data having a relatively higher data rate;</li><li>Figure 3 is a circuit block diagram of an 8mm VTR having a built in camera and functioning as an upper level system, according to one embodiment of the present invention;</li><li>Figure 4 is a flow chart for illustrating a process carried out in the course of recording still image data with the use of the upper level system of Figure 3;</li><li>Figure 5 is a diagrammatic view of a spacial array pixel data stored in a video memory of the upper level system of Figure 3 and divided into respective data areas in a first exemplary manner;</li><li>Figure 6 is a flow chart for illustrating a process of storing still picture data performed in the course of data reproduction by the upper level system of Figure 3;</li><li>Figure 7 is a circuit block diagram of an 8mm VTR having a built in camera and functioning as a lower level system;</li><li>Figure 8 is a flow chart for illustrating a process for storing still image data performed in the course of a reproduction operation by the lower level system of Figure 7;</li><li>Figure 9 is a diagrammatic view of a spacial array of pixel data stored in a video memory of the upper level system of Figure 3 and divided into respective areas in a second exemplary manner;</li><li>Figure 10 is a diagrammatic view of a spacial array of pixel data stored in a video memory of the upper level system of Figure 3 and divided into areas in a third exemplary manner;</li><li>Figure 11 is a circuit block diagram of a filter circuit employed in an upper level system;</li><li>Figures 12A and 12B are diagrammatic views of spatial arrays of pixel data divided into overlapping areas for illustrating the operation of the filter of Figure 11;</li><li>Figures 13A, 13B and 13C are diagrammatic views of spatial arrays of pixel data for illustrating a process of forming pixel data having a relatively low data rate by interpolating pixel data having a relatively higher data rate;</li><li>Figure 14 is a circuit block diagram of a still video data processing circuit for forming pixel data having a relatively low data rate by interpolation of pixel data having a relatively higher data rate and for data compression of the so formed pixel data;</li><li>Figure 15A to 15D are timing charts for illustrating the interpolation process carried out by the data processing circuit of Figure 14;</li><li>Figure 16 is a diagrammatic view of a spatial array of pixel data arranged in blocks of data to enable data compression by adaptive dynamic range coding;</li><li>Figure 17 is a timing chart for illustrating the operation of a data rearranging circuit included in the data processing circuit of Figure 14;</li><li>Figure 18 is a circuit block diagram of a decoding circuit for adaptive dynamic range decoding provided in a still picture video processing circuit of a lower level system; and</li><li>Figure 19 is a circuit block diagram of a circuit for adaptive dynamic range decoding and deinterpo- lation provided in a still picture video processing circuit of an upper level system.</li></ul>

Referring to Figure 3, the 8mm VTR illustrated therein is an upper level system capable of recording still picture data on a magnetic tape 1 so that it may be reproduced either as a first data signal having a data rate SCK₁ of a relatively high frequency f₁ or as a second data signal having a relatively lower data rate SCK₂ having a frequency f₂. More specifically, in the embodiment of Figure 3, the frequency f₁ of the first data rate SCK₁ is selected as 6fsc, whereas the frequency f₂ of the sampling clock SCH₂ is selected as 4fsc.

The VTR of Figure 3 includes a camera and signal preprocessing sub-system 10 for converting images into digital video signals having a data rate which is selectively either SCK₁ or SCK₂ and for carrying out video signal preprocessing, and a moving picture video signal processing sub-system 20 for converting the digital video signals from the sub-system 10 into analogue video signals for recording on the tape 1, and for converting playback RF signals from the tape 1 into NTSC-type analogue video signals. The VTR of Figure 3 also includes a still picture video signal processing sub-system 30 for forming digital video image signals having the data rate SCK₂ from digital video image signals supplied by the camera and signal preprocessing sub-system 10 and having a data rate SCK₁ for recording on the tape 1 and for reproducing digital video image signals from reproduced RF signals from the tape 1. The VTR further includes a recording and reproducing sub-system 40 which is operative in a recording mode for time division multiplexing analogue video signals from the moving picture video signal processing sub-system 20 and the digital video image signals from the still picture video signal processing sub-system 30 for recording separately in the video area (area 172 in Figure 1) and the PCM audio area (area 173 in Figure 1) of the tape 1 and in a reproducing mode for reproducing playback RF signals from the tape 1. The VTR finally includes a control subsystem 50 for exercising control of the signal processing operations of the still picture video signal processing sub-system 30.

The camera and signal preprocessing sub-system 10 includes a CCD image sensor 11 which provides a video image signal at an output thereof coupled with an input of a sample-and-hold and automatic gain control circuit 12 which samples the image signals at a rate determined by a selected one of the sampling rates SCK₁ and SCK₂. The sample signals are provided at an output of the circuit 12 coupled with an input of an analogue-to-digital (A/D) converter 13 which converts the sampled signals to digital form and provides the digitized video image signals to a camera processing circuit 14 which carriers out knee and gamma processing of the digitized video image signals.

The moving picture video signal processing sub- system 20 includes a video processing circuit 21 having an input coupled with the camera processing circuit 14 to receive the digitized video image signals for producing NTSC video signals therefrom which it provides to a first fixed terminal of a changeover switch 22. A movable terminal of the switch 22 is coupled with the input of a digital-to-analogue (D/A) converter 23 which, when coupled by the switch 22 to its first fixed input terminal, is operative to convert the NTSC signals from the video processing circuit 21 to analogue form for supply to an output terminal 26 of the VTR.

The video processing circuit 21 is further operative to convert NTSC video signals to a format referred to hereinafter as "moving picture data" in a form suitable for recording in the video areas of the oblique recording tracks of the tape 1. That is, the video processing circuit 21 serves to frequency modulate luminance signals included in the digitized video image signals supplied from the camera processing circuit 14 and to shift sub-carrier chrominance signals included therein to a lower frequency band in order to produce the moving picture data in the form of frequency multiplexed signals. The video processing circuit 21 provides the moving picture data to the input of a D/A converter 24 for conversion to analogue form for recording on the tape 1. The video processing circuit 21 is also coupled with the output of an A/D converter 25 from which it receives digitized moving picture data played back from the tape 1 and converts the received signals into the same format as the digitized video image signals received from the camera processing circuit 14.

The still picture signal processing sub-system 30 includes a video RAM 32 having a 1152 sample by 484 line by 8 bit storage capacity which stores the digitized video image signals received from the camera processing circuit 14 provided either in the form of a single field or a single frame thereof as video image data. The video RAM 32 is coupled to a still picture video processing circuit 31 which serves to read the stored video image data from the video RAM 32. If the stored image data were provided at a data rate of SCK_i, the still picture video processing circuit 31 serves to form video image data having a data rate SCK₂ from the signals read from the video RAM 32. In a first example of the still picture video processing circuit 31, this process is carried out by selecting predetermined pixels of the data stored in the video RAM 32 on a line-by-line basis totalling two thirds of the stored data, thereby permitting the data rate of the newly formed video image data to be selected as 4fsc instead of 6fsc. In accordance with a second example of the still picture video processing circuit 31, the formation of the image data having the sampling rate SCK₂ is carried out by interpolating at least selected ones of the image data stored in the video RAM 32.

The still picture video processing circuit 31 is further operative to compress the newly formed video image data by dividing the data into blocks representing spatially adjacent pixels and carrying out adaptive dynamic range coding of the data in each block in accordance with the number of bits per pixel allocated in accordance with the dynamic range of each block. Significant data compression is achieved in this manner due to the strong correlation of the video signals in time and space.

The compressed data produced by the still picture video processing circuit 31 is supplied thereby to a PCM processing circuit 33 which stores the compressed data temporarily in a RAM 34. The PCM processing circuit 33 is operative to append synchronization signals, error correction code data and identification data (ID) supplied by the control sub-system 50 to the compressed data in order to produce still picture data for recording on the tape 1. In a reproduction mode, the PCM processing circuit 33 serves to separate and detect the ID from the reproduced still picture data to determine whether the signals received upon playback represent data having a data rate of SCK₂, or only data having a data rate of SCK_i. The playback signals which were recorded in compressed form are supplied by the PCM processing circuit 33 to the still picture video processing circuit 31 which expands the received compressed signals to reproduce the video image data therefrom.

The recording and reproducing sub-system 40 includes a time division multiplexer (MUX) 41 which serves to time divisionally multiplex the analogue video signals provided by the moving picture video signal processing sub-system 20 for recording in the video areas of the tape 1, and the compressed still picture data provided by the still picture video signal processing sub-system 30 for recording in the PCM audio areas of the tape 1. The sub-system 40 also includes a recording amplifier 43 coupled to a first fixed terminal of a changeover switch 42 to receive the time divisionally multiplexed analogue and digital signals from the multiplexer 41 to supply the time multiplexed signals in amplified form to a rotary recording head 45 for recording on the tape 1. The sub-system 40 further includes a playbackamplifier44 having an inputcoup- led with the head 45 for amplifying playback signals received therefrom and supplying the amplified signals to a second fixed terminal of the switch 42 to be provided in a reproduction mode through the multiplexer 41 to the appropriate ones of the sub-systems 20 and 30 for processing as reproduced signals.

The control sub-system 50 includes a system controller 52 for controlling recording and reproducing modes and generating the ID for recording with the still picture data. The sub-system 50 also includes a memory controller 53 which is operative to generate write and read addresses for the video RAM 32 under the control of the system controller 52.

In operation during a still picture photographing mode, the user actuates a shutter control (not shown for purposes of simplicity and clarity) in order to select an image to be recorded by the VTR as a still picture. Actuation of the shutter control is detected by the system controller 52 upon receipt thereof of a corresponding signal at an input terminal 54. The system controller 52 is also provided with a further control signal produced by the actuation of a further control (not shown for purposes of simplicity and clarity) which determines whether the still picture is to be generated at a data rate of SCK₁ or SCK₂. When the system controller 52 senses that the shutter control has been actuated, it causes a frame or a field of the digital video signal supplied by the camera processing circuit 14 to be processed by the still picture video signal processing sub-system 30 for recording as digital image signals in the PCM audio area of the tape 1 by means of the recording and reproducing sub-system 40.

In greater detail, the digital video signals supplied by the camera processing circuit 14 are supplied to the video RAM 32 via the still picture video processing circuit 31. The video RAM 32 stores the received signals sequentially in memory locations determined by write addresses produced by the memory controller 53 in synchronism with the line-sequential scanning of the CCD image sensor 11. Subsequently, the video RAM 32 reads the stored image data signals sequentially to the still picture video processing circuit 31 utilizing read-out address data produced by the memory controller 53 synchronized with the data compression operations of the circuit 31. If the stored image data were produced at a data rate SCK_i, the circuit 31 then proceeds to generate video image data having the data rate SCK₂ from the image data read sequentially from the video RAM 32 either by selecting predetermined pixel data therefrom, by interpolation or both, and compresses the thus produced video image data together with the remaining portions of the data stored in the video RAM 32 or such portions thereof as may be necessary to reconstruct the data having the data rate SCK₁ upon reproduction by an upper level system. The compressed data thus produced by the circuit 31 is supplied thereby to the PCM processing circuit 33 which temporarily stores the compressed data in the RAM 34. The PCM processing circuit 33 subsequently reads the data stored in the RAM 34 sequentially and appends synchronizing signals, error correction code data and ID indicating a recording configuration of the still picture data supplied from the system controller 52 (as described below) to generate the still picture data to be supplied to the multiplexer 41.

At the same time, the video processing circuit 21 processes the digitized video signals supplied by the camera processing circuit 14 for conversion into NTSC-type signals which it supplies, in turn, to the D/A converter 23 by means of the switch 22. The NTSC-type video signals are converted by the D/A converter 23 into analogue signals which are supplied to a video monitor by way of the output terminal 26, thus enabling the user to monitor the image recorded as a still picture by the VTR. If a moving picture is being recorded simultaneously with a recording of the still picture, the video processing circuit 21 simultaneously produces the frequency-multiplexed moving picture data which it supplies to the D/A converter 24 for conversion into analogue video signals supplied thereby to the multiplexer 41.

The multiplexer 41 multiplexes the received signals as described above to supply them to the rotary head 45 via the switch 42 and the amplifier 43 for recording in the respective areas of the tape 1. As a result, the still picture data is recorded in a number of from ten to several hundreds of tracks of the PCM audio area of the tape 1 in digital form simultaneously with the ID indicating the recording configuration of the still picture data. It is noted that the number of tracks employed to record the still picture data depends on the data compression ratio. The analogue video signals produced from the moving picture data are selectively recorded in the corresponding tracks of the video area. However, if the user chooses to record still picture data in the PCM audio area without recording the analogue video signals in the video area of the tape 1, the moving picture video signal processing sub-system 20 is then disabled.

With reference now to the flow chart of Figure 4, a process for forming video image data having a data rate SCK₂from stored image data having the date rate SCK₁ is illustrated therein. With reference also to Figure 5, a spatial array of respective pixel data of the video image data having a data rate of SCK₁ and produced in a 6fsc mode of the VTR of Figure 3 is illustrated therein. The pixel data as illustrated in the array of Figure 5 are designated a¡,j where i represents a line number of the array from 1 to 484 and j represents a number of from 1 to 1152 representing the position of each of the pixel data in its respective line in ascending orderfrom left to right, as supplied by the sub-system 10 in the 6fsc mode. It will be appreciated that, if the VTR were operating in a 4fsc mode such that the data rate were equal to SCK₂, the spatial array of pixel data supplied by the sub-system 10 would instead include 768 samples in each of the 484 lines or two thirds the amount of data contained in the array in Figure 5.

With reference again to Figure 4, in a step ST1 thereof, a user selects the mode in which the sub-system 10 either produces high resolution image data having a data rate of 6fsc (the 6fsc mode) or relatively lower resolution image data having a data rate 4fsc (the 4fsc mode). In a step ST2, the system controller 52 detects the mode thus selected by the user in step ST1 for determining a sequence in which the image data shall be read from the video RAM 32 and the ID to be appended thereto in order to enable subsequent reproduction of the image data produced either with a data rate of 6fsc or 4fsc by a lower level system operating at a dat of only 4fsc. If the image data were produced in the 6fsc mode, the video RAM 32 stores image data having 1152 samples per line, as illustrated in Figure 5. In order to permit reproduction of an image by a lower level system from the image data thus stored in the video RAM 33, the system controller 52 generates ID to be appended to each of samples a₁,₁₉₃ to a₁,₉₆₀ of the image data as illustrated in Figure 5, which will be detected by the lower level system upon playback thus enabling it to reproduce a central portion indicated as area CB in Figure 5 of the corresponding image.

Accordingly, in the 6fsc mode, in a step ST3 the system controller 52 generates an ID of "10" to be appended to the data a_1,1, to a₁,₁₉₂ of each line of the stored image data indicating that such data fall within an area LB of the image, as depicted in Figure 5, and that the same are required only by an upper level system upon reproduction. The ID are provided by the system controller 52 to the PCM processing circuit 33, whereupon the step ST4 is carried out. In step ST4, the image data corresponding with the area LB of Figure 5 are read from the video RAM 32 with the use of read-out addresses produced by the memory controller 53 in response to control signals from the system controller 52. The still picture video processing circuit 31 thereupon compresses the pixel data a_¡,₁ to a_l,₁₉₂ and supplies the compressed data to the PCM processing circuit 33 which proceeds to append the ID "10" to the compressed data for recording by means of the sub-system 40 in the PCM audio areas of the tape 1.

Subsequently, the system controller 52 generates ID "00" in a step ST5 for identifying the 768 samples of each line of the data array illustrated in Figure 5 corresponding with the area CB for indicating that such data are to be reproduced both by upper and lower level systems operating with respective data rates of 6fsc and 4fsc when reproducing such data. The system controller supplies the ID "00" to the PCM processing circuit 33 in step ST5 and then proceeds to the step ST6. In step ST6, the pixel data a_l,₁₉₃ to a_i,960 of the Figure 5 array are read from the video RAM 32 to the still picture video processing circuit 31 under the control of read-out addresses produced by the memory controller 53 in response to corresponding control signals from the system controller 52. Once again, the circuit 31 compresses the received data and supplies them to the PCM processing circuit 33, which then appends the ID "00" to the compressed data for recording in respective predetermined areas of the tape 1.

Subsequently in a step ST7, the system controller 52 generates ID "11" indicating that the corresponding pixel data includes data a_i,961 to a_i,1152 corresponding to image area RB of Figure 5. The ID "11" indicate that the data a_i,961 to a_l,₁₁₅₂ are not to be reproduced by a lower level system capable of reproducing image data with a data rate of 6fsc. Thereafter, in a step ST8 the video RAM 32 reads out the data a_i,961 to a_i1152 to the circuit 31 in response toread-out addresses produced by the memory controller 53 under the control of the system controller 52. As before, the circuit 31 compresses the received pixel data and supplies the compressed data to the PCM processing circuit 33. The compressed data corresponding to pixels a_i,961 to a_l,₁₁₅₂ received by the circuit 33 are then supplied with appended ID "11" and are subsequently recorded in predetermined areas of the tape 1 by the sub-system 40.

If, however, in the step ST2 the system controller 52 determines that the image data were produced in the 4fsc mode, the process branches to a step ST9 in which the system controller 52 produces ID "00" and supplies them to the PCM processing circuit 33 before proceeding to a step ST10. As the step ST10, the system controller 52 provides control signals to the memory controller 53 causing it to produce appropriate read-out addresses which it supplies to the video RAM 32 so that it will then read out all of the pixel data stored therein. It will be appreciated that since the image data were produced in the 4fsc mode, an array of 768 samples by 484 lines was thereupon stored in the video RAM 32, so that the entire image thus produced may be recorded for reproduction by either an upper or lower level system operating in the 4fsc mode. Accordingly, after compression of the data read from the video RAM 32 by means of the circuit 31, the PCM processing circuit 33 appends the ID "00" to the compressed data which are recorded on the tape 1 by the sub-system 40.

It will be appreciated, therefore, that image data having a data rate SCK₂ (that is 4fsc) are formed by the RAM 32 and still picture video processing circuit 31 in cooperation with the system controller 52 and memory controller 53. It will be appreciated further that the PCM processing circuit 33 and the sub-system 40 together serve as a means for recording image data having a data rate SCK₂ to permit reproduction thereof by a lower level system, as well as for recording high resolution image data having a data rate SCK₁ which is reproducible by an upper level system operating in a 6fsc mode. It will also be seen that the PCM processing circuit 33 and sub-system 40 in cooperation with the system controller 52 serve as a means for recording area discriminating code data in the form of the ID for identifying predetermined areas of the tape 1 in which image data having respective data rates SCK₂ and SCK₁ are recorded.

A still picture reproducing mode of the upper level system VTR of Figure 3 is initiated by a user through the actuation of an appropriate control (not shown) which generates a corresponding signal received by the system controller 52 which, in turn, generates further necessary controls signals for governing the operation of the VTR in the selected mode. Accordingly, the sub-system 40 proceeds to reproduce the recorded still picture data from the PCM audio areas of the tape 1 and provides them through the multiplexer 41 to the PCM processing circuit 33 which separates and detects sync signals and IDs in the reproduced still picture data and carries out error correction. The error corrected data, which is still in compressed form, are then stored in the RAM 34 and subsequently read therefrom to be supplied to the still picture processing circuit 31. The ID detected from the reproduced data by the circuit 33 are supplied through the system controller 52.

The circuit 31 processes the compressed data by data expansion to reproduce the image data which it stores in the video RAM 32 under the control of write addresses supplied by the memory controller 53. Such write addresses are produced by the memory controller 53 in response to control signals from the system controller 52 which it generates on the basis of the ID received from PCM processing circuit 33 so that the reproduced image data will be stored in predetermined regions of the video RAM 32, as explained in greater detail below.

When either a complete field or a complete frame of the image data has been stored in the video RAM 32 in the manner described above, the stored data may then be read from the video RAM 32 in response to read out addresses which are synchronized with NTSC-type video signals are supplied to the still picture video processing circuit 31 which, in turn, provides them to the D/A converter 23 through the switch 22. The analogue video signals thus produced by the converter 23 are supplied to a monitor for viewing, via the output terminal 26.

The manner in which the system controller 52 controls storage of the image data in the video RAM 32 will be explained in connection with the flow chart of Figure 6. In a step ST1a of Figure 6, the system controller 52 determines whether the data were recorded in a 6fsc mode. If so, the process continues in a step ST2a in which the ID of the reproduced image data are determined by the system controller 52.

In the exemplary process illustrated in Figure 6, it is assumed that the data were arranged upon recording in the manner illustrated in Figure 5. Accordingly, if ID "00" have been received by the system controller 52, this indicates that the reproduced image data correspond with pixels a_l,₁₉₃ to a_l,₉₆₀ in the array of Figure 5. Therefore, the system controller 52 causes the memory controller 53 to generate appropriate write addresses for storing the received data from the circuit 31 in the portion of the video RAM 32 corresponding to the region CB as illustrated in Figure 5. The system controller 52 then proceeds to step ST6a.

If instead the system controller 52 receives ID "10" in the step ST2a, this indicates that the reproduced image data corresponds to the data a_¡,₁ to a_l,₁₉₂ corresponding to the region LB illustrated in Figure 5. Accordingly, the controller 52 then proceeds to a step ST4a wherein it causes the memory controller 53 to generate appropriate write addresses for storing the image data from the circuit 31 in a portion of the video RAM 32 corresponding to the region LB as represented in Figure 5. Thereafter the system controller 52 proceeds to the step ST6a.

However, if the system controller 52 receives ID "11" in the step ST2a, this indicates that the image data correspond with the data a_l,₉₆₁ to a_l,₁₁₅₂ 2 of the region RB illustrated in Figure 5. In that event, the system controller 52 proceeds to a step ST5a wherein it causes the memory controller 53 to generate appropriate write addresses for storing the image data in that portion of the video RAM 32 corresponding to the area RB of the array illustrated in Figure 5. Once again, the system controller 52 then proceeds to the step ST6a.

In step ST6a the system controller 52 determines whether image data constituting an entire field or frame of the still picture have been reproduced from the tape 1 and stored in the video RAM 32. If so, the controller 52 terminates the process, but if not, the process returns to the step ST2a for deciphering the ID of subsequently received image data in order to continue the storage of the received data in the video RAM 32. In this manner, the video RAM 32 stores the reproduced image data in a manner conforming with their corresponding pixel locations so that the data may subsequently be read from the RAM 32 in proper order for generating an NTSC video signal therefrom which can be viewed with the use of a monitor.

If, however, it is determined in the step ST1a that the image data have been recorded on the tape 1 in the 4fsc mode, the process branches to a step ST7a in which the system controller 52 determines whether the received ID are "00". If not, the ID do not indicate that the accompanying data are reproducible as a still image according to the 4fsc mode, and the process is then terminated. If on the other hand the received ID are "00", this indicates that the reproduced data were recorded as still image data in the 4fsc mode and the controller proceeds to step ST8a.

In step ST8a, the system controller 52 directs that all of the reproduced image data, after expansion by the circuit 31, be stored in the video RAM 32, after which the process is terminated. Accordingly, in this step ST8a the reproduced image data which were recorded in the 4fsc mode are stored as a complete image including 768 samples by 484 lines in the video RAM 32.

Upon completion of the data storage process illustrated in Figure 6, the stored image data are read from the video RAM 32 as described above under the control of read-out addresses provided by the memory controller 53 and synchronized with NTSC-type synchronizing signals preliminary to their conversion into NTSC analogue video signals which are suitable for image reproduction by a monitor coupled with the output terminal 26 of the VTR.

A technique by which a lower level system reproduces a still picture recorded on the tape 1 in the manner described above by an upper level system, will now be explained in connection with the circuit block diagram of a lower level system in Figure 7. The lower level system of Figure 7 is constructed in a manner similar to that of the upper level system illustrated in Figure 3, provided however that the lower level system of Figure 7 is operable only in a 4fsc mode. Accordingly, the lower level system of Figure 7 includes a camera subsystem 10a including a CCD image sensor 11a, sample-and-hold and automatic gain control circuit 12a, A/D converter 13a and camera processing circuit 14a operating in the same manner as the corresponding elements of the sub-system 10 in Figure 3, but which operate solely at a data rate of SCK₂ equal to 4fsc.

The lower level system of Figure 7 also includes a moving picture video signal processing sub-system 20a including a video processing circuit 21a, D/A converters 23a and 24a and an A/D converter 25a, and functioning in the same manner as the sub-system 20 of Figure 3, but operating at a data rate SCK₂ for converting digital video signals supplied by the camera sub-system 10a into analogue video signals to be recorded on the tape 1 and for reproducing NTSC analogue video signals from RF signals reproduced from the tape 1. The system of Figure 7 also includes a still picture video signal processing sub-system 30a operable in the same manner as the subsystem 30 of Figure 3 functioning in the 4fsc mode, and including a still picture video processing circuit 31a, a video RAM 32a, a PCM processing circuit 33a and a RAM 34a. The sub-system 30a is operative for compressing digital video signals provided in units of fields or frames from the camera sub-system 1 Oa for recording on the tape 1, and operable in a reproduction mode for reproducing still image data reproduced from the tape 1. The sub-system 40a which carries out the same signal multiplexing, amplification and recording functions as the sub-system 40 of Figure 3 by means of a time division multiplexer 41a, a changeover switch 42a, a recording amplifier 43a, a playback amplifier 44a and a recording and reproducing head 45a. Finally, the system of Figure 7 includes a control sub-system 50a for controlling the still picture video signal processing sub-system 30a by means of a system controller 52a and memory controller 53a operating in the manner described below.

Since the lower level system of Figure 7 operates only at the data rate SCK₂, the video RAM 32a has a capacity of only 768 samples of 484 lines by 8 bits. In addition, the still picture video processing circuit 31a a is not provided with the capability of forming image data having a sampling rate SCK_Zfrom the image data having a data rate SCK₁ as in the upper level system of Figure 3.

The manner in which the lower level system of Figure 7 reproduces still image data from the tape 1 will now be explained in connection with the flow chart of Figure 8. The system controller 52a determines in a step ST1 b of Figure 8 whether a 6fsc recording mode was in use when reproduced still image data were recorded. If so, the process continues to a step ST2b in which it is determined by the system controller 52a whether the ID of the reproduced image data are "00" indicating that they correspond with data reproducible by the lower level system. If so, and assuming that the data were assigned ID in the manner illustrated in Figure 5, it is known that the reproduced image data correspond with the pixel data a_l,₁₉₃ to a_i,960 of the Figure 5 spatial array. Accordingly, in the step ST3b the system controller 52a directs the memory controller 53a to generate write addresses for storing the reproduced image data after expansion by the circuit 31a in the video RAM 32a.

If in step ST2b it is determined that the ID are not "00" or upon completion of the step ST3b, the controller 52a determines in a step ST4b whether the last of the image data have been reproduced. If so, the controller 52a terminates the process, but if not, the controller returns to the step ST2b to process further reproduced image data. Accordingly, in the loop comprising steps ST2b-ST4b, the system controller 52a utilizes the ID recorded simultaneously with the image data in order to direct the memory controller 53a to cause the image data necessary for reproduction of the still image by the lower level system to be stored in the video RAM 32a.

If, however, in the step ST1 b, the controller 52a determines that the reproduced image data were not recorded in the 6fsc mode, processing continues a step ST5b to determine whether the corresponding ID are "00". If not, this indicates that the reproduced data are not suitable for still image reproduction by the lower level system of Figure 7. If, however, the ID are "00" as determined in step ST5b, in a step ST6b the system controller 52a controls storage of the reproduced image data in their entirety in the video RAM 32a before terminating the process illustrated in Figure 8. That is, since the image data were recorded in the 4fsc mode, the reproduced image data may be stored. in their totality in the video RAM 32a in a form of a data array of 768 samples by 484 lines.

After the image data have been thus stored in the video RAM 32a as described above, the stored data may then be read out on a line-by-line basis according to read out addresses produced by the memory controller 53a synchronized with the NTSC standard for conversion into NTSC-type video signals for supply to a monitor. Consequently, the still image recorded in the PCM audio area of the tape 1 is thus displayed on a monitor screen for viewing. It will be appreciated that, in the foregoing manner, a still image recorded by an upper level system on the tape 1 at a data rate of SCK_i, may be reproduced easily by a lower level system, such as that illustrated in Figure 7. It will also be appreciated that the interchangeability of recordings between upper and lower level systems may thereby be obtained without increasing the complexity of the lower level system.

With reference now to Figure 9, a further exemplary manner of dividing high resolution image data generated by an upper level system at a data rate of SCK₁ is illustrated therein. As shown in Figure 9 pixel data a_i,1 to a_i,768 correspond with an image area CB representing a left-hand portion of the corresponding image and allocated ID "00". The remaining image data, namely data a_i,769 to a_l,₁₁₅₂ correspond with an image portion RB to the right of the image portion CB and allocated ID "11". During reproduction by the lower level system of Figure 7, therefore, the image data a_i,1 to a_i,768 will be stored in the video RAM 32a in response to the ID "00" for reproducing a still image corresponding with the portion CB.

With reference now to Figure 10, a still further exemplary technique for dividing a spatial array of image data a_i,1 to a_i,1152 produced at a sampling rate SCK₁ in the 6fsc mode is illustrated therein. As shown in Figure 10, the spatial array is divided into three areas, namely, an area LB including data a_i,1 to a_i,194, an area CB including data a_l,₁₉₃ to a_i,960 and an area RB including data a_l,₉₅₉ to a_i,1152. Accordingly, it will be seen that two-pixel overlapping portions exist between the areas LB and CB as both include the data a_l,₁₉₃ and a_i,194, and again between areas CB and RB as both include the data a_l,₉₅₉ and a_l,₉₆₀. Respective ID "10", "00" and "11" are assigned to the data within the areas LB, CB, RB, respectively.

According, when reproduction of the recorded still picture data is undertaken by a lower level system, detection thereby of the ID "00" designating the data a_l,₁₉₃ to a_i,960 for reproduction of a still image thereby is facilitated. However, since the data areas overlap, it is possible for an upper level system to carry out filtering operations performed by combining values of adjacent pixels obtained from a single one of the areas LB, CB and RB to provide filtered data for the entirety of the data a_i,1 to a_l,₁₁₅₂. That is, data from the areas LB, CB and RB may be processed independently of each other which advantageously includes data filtering operations.

An exemplary data filtering operation may be carried out utilizing the digital filter circuit illustrated in Figure 11. The filter circuit of Figure 11 is provided with a filter input 141 coupled with a series combination of one pixel interval delay devices 142 and 143. The filter circuit of Figure 11 further includes a multiplier 144 coupled to the output of the delay device 143 and operative to multiply the input data delayed by two-pixel intervals by a coefficient of one quarter, a multiplier 145 coupled to the output of the delay device 142 and operative to multiply the input data delayed by one-pixel interval by a coefficient of one half, and a multiplier 146 coupled to the input terminal 144 and operative to multiply 146 coupled to the input terminal 144 and operative to multiply the input data by a coefficient of one quarter. The filter circuit further includes an adding circuit 147 having a first input terminal coupled to the output of the multiplier 144, a second input terminal coupled to the output of the multiplier 145, and a third input terminal coupled to the output of the multiplier 146, and operative to sum the outputs of the three multipliers 144 to 146 which is supplies as output pixel data b¡,j to an output terminal 148 of the filter circuit. The filter circuit of Figure 11, therefore, serves to produce a weighted mean b¡,j of three adjacent data a_i,j-1, a_i,j and a_i,j+1.

In the absence of an overlap between adjacent data areas as illustrated in Figure 10, it is necessary to combine data from two different areas when carrying out filtering operations at the edges of each area, as illustrated in Figure 12A. By providing a two-pixel overlap, as illustrated in Figure 12B, filtering may be carried out with the use of the circuit illustrated in Figure 11 by combining sequentially available data a_i,j even at the edges of the three areas LB, CB and RB whereby filtered data representing the entirety of the image may be provided while in all instances utilizing only data from a single area in carrying out each filtering operation. It will be appreciated that the overlapping portions need not be limited to two horizontally adjacent pixels but may be advantageously selected in size to accommodate the filtering technique in use.

As mentioned above, it is also possible to form image data reproducible at a lower sampling rate SCK₂ by interpolation technique is illustrated in Figure 13A to 13C and described below. Referring first to Figure 13A, a first line of image data from an array of 1152 samples by 484 lines is illustrated therein including data values arranged sequentially as a_1,1 to a_1,1152- As shown in Figure 13B, selected ones of the samples a_1,1 to a_1,1152 are combined by interpolation and substituted for predetermined ones of the samples. For example, as shown in Figure 13B, sample a₁,₂ has been replaced by an interpolated value (a_1,2 + a_1,3)/2. It will be appreciated, however, that the values of the selected samples which have been replaced by interpolated values may be recovered through a linear combination of the interpolated values and certain ones of the uninterpolated sample values. For example, the value of sample a₁,₂ may be recovered by a linear combination of the interpolated value (a₁,₂ + a₁,₃)/2 and the sample a_l,₃, as discussed in greater detail below.

As a final step in this process, the data as illustrated in Figure 13B are arranged so that the data a;,3k, where k is an integer, are removed to a separate data area assigned ID "01 whereas the remaining data are assigned ID "00" thus to form a data area identified by the ID "00" including corresponding values bp,q where p = 1 to 484 and q = 1 to 768, as illustrated in Figure 13C. It will be appreciated that the data area identified by the ID "00" is dimensioned appropriately for reproduction by a lower level system operating at a data rate of SCK₂. It will also be appreciated, therefore, that the data bp,q is derived in the process illustrated by Figures 13A to 13C according to the following formulae:

<maths id="math0001" num=""><img file="EP0486185A2_D0001.tif" /></maths><maths id="math0002" num=""><img file="EP0486185A2_D0002.tif" /></maths>It will further appreciated that still other interpolation techniques may be employed for deriving the data bp,q ; for example interpolation may be carried out according to the following formula instead of the foregoing formulae:<maths id="math0003" num=""><img file="EP0486185A2_D0003.tif" /></maths>

In certain advantageous embodiments, the still picture video processing circuit 31 of Figure 3 includes a data processing circuit as illustrated in Figure 14 which serves to carry out the interpolation process illustrated in Figures 13A to 13C as well as to carry out adaptive dynamic range coding of the image data to achieve data compression. The data processing circuit of Figure 14 includes an interpolation circuit 60 which serves to form pixel data reproducible at a data rate of SCK₂ from the image data having a data rate SCK₁ by interpolation of certain ones of the image data. The circuit of Figure 14 further includes an adaptive dynamic range coding (ADRC) circuit 70 for carrying out adaptive dynamic range coding of data supplied by the interpolating circuit 60, and a rearraying circuit 80 for rearranging the compressed data supplied by the ADRC circuit 70 in accordance with a predetermined format.

More particularly, the interpolation circuit 60 has an input terminal 61 coupled to the input of a delay device 62 which serves to delay input data having 8 bits per pixel and supplied from the video RAM 32 of Figure 3 by one-pixel interval, an adding circuit 63 having a first input coupled to the input terminal 61 and a second input coupled to the output of the delay device 62, a multiplier 64 having an input coupled to an output of the adding circuit 63 and operative to multiply the output thereof by a coefficient of one half, and a selector 65 having a first fixed terminal coupled to an output of the multiplier 64, a second fixed terminal coupled to the output of the delay device 62 and a moveable terminal at which the output of the interpolating circuit 60 is provided.

The ADRC circuit 70 includes a RAM 71 for temporarily storing image data supplied by the interpolating circuit 60. The circuit 70 also includes a maximum/minimum detection circuit 72 coupled with a data output of the RAM 71 and operative to detect a maximum value and a minimum value of a block image data read from the RAM 71 thus to produce respective maximum value data MAX and minimum value data MIN. Also included in the circuit 70 is a subtracting circuit 73 having a non-inverting input coupled with the circuit 72 to received the maximum value data MAX therefrom and an inverting input coupled with the circuit 72 to receive the minimum value data MIN therefrom and operative to produce dynamic range data DR for each block by subtracting the minimum value data MIN thereof from the maximum value data MAX thereof. The ADRC circuit 70 further includes a subtracting circuit 74 having a non-inverting input coupled to the output of the RAM 71 and an inverting input coupled to the circuit 72 to receive the minimum value data MIN therefrom, and operative to provide difference data at an output thereof representing difference between the values of each of the image data in a given block and the minimum value data MIN thereof. The ADRC circuit 70 still further includes an adaptive encoder 75 supplied with the dynamic range data DR of each block from the output of the subtracting circuit 73 and the difference values from the output of the subtracting circuit 74, and operative to quantize the difference values of each block based on the dynamic range data DR thereof to supply the quantized difference values as quantized data Q.

The rearraying circuit 80 includes a register 81 operative to store a predetermined number, namely, 384, of the quantized data Q supplied by the adaptive encoder 75 of the ADRC circuit 70 and a selector 82 operative to provide a selected one of the dynamic range data DR, the minimum value data MIN, the quantized data Q from the ADRC circuit 70 and the quantized data Q from the register 81 at a given instant to an output terminal 83 of the circuit of Figure 14.

The operation of the circuit of Figure 14 will be described in conjunction with Figures 15A to 15D, 16 and 17. The digital video signals as supplied from the camera sub-system 10 of the VTR of Figure 3 constituting a single frame of an image are supplied in line-sequential fashion in accordance with the NTSC system. The pixel data as thus supplied are illustrated in Figure 15A as the data a¡,j where i indicates a line number of from 1 to 484 and j indicates a sequence or order of the pixels within each line. The data a¡,j are supplied via the terminal 61 of the Figure 14 circuit to the input of the delay device 62, and to a first summing input of the adding circuit 63. As shown in Figure 15B, the data a_i,j as supplied by the delay device 62 are delayed by one-pixel interval. The adding circuit 63 and the multiplier 64 cooperate to form interpolated data at the output of multiplier 64 by adding a delayed pixel a_i,j with a currently received pixel a_i,j+1 and multiplying the sum by a coefficient of one half thus to produce interpolated data (a_i,j + a_i,j+1)/2 as illustrated in Figure 15C, which are supplied to the first fixed input terminal of the selector 65. With reference also to Figure 15D, it will be seen that the selector 65 selects the pixel data a_i,j from the delay device 62 and the interpolated data (a_i,j + a_i,j+1)/2 from the multiplier 64 at a ratio of 2 : 1 and supplies the selected pixel data to the RAM 71.

RAM 71 stores the selected pixel data from the selector 65 sequentially to form a spatial array of data constituting 1152 samples by 484 lines of pixel data as illustrated in Figure 16. The memory controller 53 of Figure 3 generates read-out addresses which it supplies to the RAM 71 to cause the pixel data stored therein to be read out in blocks B_m,_n each including a rectangular array of six samples by four lines where m = 1 to 121 and n = 1 to 192 which are supplied to the maximum and minimum circuit 72 and subtracting circuit 74. As noted above, the circuit 72 produces the maximum value data MAX_m,_n and the minimum value data MIN_m,_n representing the maximum and minimum values among the 24 pixels in each corresponding block B_m,_n and supplies these values as described above to the subtracting circuits 73 and 74 and the selector 82.

The adaptive encoder 75 quantizes the difference data of each block supplied by the subtracting circuit 74 with, for example, 0-4 bits, depending on the corresponding dynamic range data DRmn and supplies the quantized data to the register 81 and the selector 82. More specifically, the pixel data a_i,j are each converted into from 0-4 bits of quantized data Q_i,j, while the interpolated data (a_i,j + a_i,j+1)/2 are each converted into from 0 to 4 bits of quantized data (Q_i,j + Q_i,j+1)/2. In the foregoing manner, the ADRC circuit 70 carries out a compression of the pixel data and the interpolated data.

The register 81 of the rearraying circuit 80 has a capacity of 4 bits by 384 stages by 4 lines in order to store the quantized data Q_i,3k, where k is an integer, in order to store all of the quantized data of the blocks B_i,1 to B_i,192 which is to be assigned ID "01" and which, thus, will not be reproduced by a lower level system. The operation of the register 81 is controlled in accordance with clock signals provided by the memory controller 53 of Figure 3. The selector 82 of the rearraying circuit 80 serves to arrange quantized data Q,j and (Q_i,j + Q_i,j+1)/2 from the adaptive encoder 75, the dynamic range data DR_m,_n from the subtracting circuit 73 and the minimum value data MIN_m,_n from the circuit 72, under the control of the memory controller 53 of Figure 3. More specifically, as illustrated in Figure 17, the selector 82 arrays the quantized data Q_i,j and Q_i,j and (Q_i,j + Q_i,j+1)/2, with the exception of Q;,_3k, where k is an integer, for each of the first four lines, together with the dynamic range data DR_m,_n and minimum value data MIN_m,_n where m = 1 and n = 1 to 192, that is, for the blocks B_1,1 to B_1,192 as illustrated in Figure 16 and which bear the ID "00", which are thus reproducible both by upper and lower level systems after recording on the tape 1. The selector 82 then arrays the quantized data Q_i,3k of the blocks B_1,1 to B_1,192 which are assigned an ID "01" as shown in Figure 17 and which are, thus, not to be reproduced by the lower level system. This process is repeated until all of the blocks B_m,_n where m = 1 to 121 and n = 1 to 192 have been thus arrayed.

The rearrayed data as provided by the selector 82 are supplied by the output terminal 83 to the PCM processing circuit 33 of Figure 3. The PCM processing circuit 33 proceeds to append the ID "00" and "01" to the data as noted above and as indicated in Figure 17, and supplies the thus appended data to the multiplexer 41 of the sub-system 40. The sub-system 40 proceeds to record the data thus supplied by the circuit 33 in the PCM audio areas of the tape 1.

A technique for reproducing interpolated data recorded by an upper level system in the manner described above in connection with Figures 14 to 17 with the use of a lower level system of the type illustrated in Figure 7 will be explained in connection with Figure 18. Referring to Figure 18, a data processing circuit provided in certain advantageous forms of the still picture video processing circuit 31a of Figure 7 is illustrated therein. The circuit of Figure 18 includes an adaptive dynamic range decoding (ADRD circuit 90 operating under the control of a control circuit 100 in order to reproduce the image data bp,q, where p = 1 to 484 and q = 1 to 168, which are utilized by the lower level system operating at a data rate of SCK₂.

More particularly, the ADRD circuit 90 includes a serial to parallel converter 92 for converting the quantized data Q¡,j and the quantized interpolated data (Q¡,j + Q_i,j+1)/2 together with the dynamic range data DR_m,_n and the minimum value data MIN_m,_n which are received at a terminal 91 in serial format into a parallel format. The ADRD circuit 90 also includes a changeover switch 93 coupled to an output of the converter 92 operative to supply the quantized data Q¡,j and the quantized interpolated data (Q_i,j + Q_i,j+1)/2 at a first fixed,terminal thereof and the minimum value data MIN_m,_n at a third fixed terminal thereof. The ADRD circuit 90 further includes an adaptive decoder 94 coupled to the first and second fixed terminals of the switch 93 to receive the quantized data, quantized interpolated data and dynamic range data therefrom and operative to decode the quantized data and quantized interpolated data which it then supplies to a first input of an adding circuit 95 having a second input coupled with the third fixed terminal of the switch 93 to receive the minimum value data MIN_m,_n which is added to the decoded data to reproduce the image data bp,q.

The control circuit 100 includes a gate circuit 103 which is operative to gate clocking signals supplied via a clock input terminal 101 to the circuit 90 under the control of a signal supplied by a counter 104. The counter 104 is operative to count the clock signals received at the terminal 101 and is reset by a reset pulse received thereby from a reset input terminal 102. The reset pulse is provided at the terminal 102 from the system controller 52a of Figure 7 upon the first detection of the ID "00" in the reproduction mode, whereupon the counter 104 is initialized. The counter 104 then proceeds to count a predetermined number of clock signals corresponding with an interval during which the quantized data, quantized interpolated data, dynamic range data, and minimum value data which are required by the lower level system to reproduce the data bp,q are received. At this time, the gate circuit 103 is enabled to pass the clock signals supplied via the terminal 101 to the circuit 90 for this purpose. The counter 104 also serves to count the number of tracks in which the data so required by the lower level system are recorded.

The adaptive decoder 94 receives the clock signals from the gate 103 which control the adaptive decoding thereby of each of the quantized data and quantized interpolated data in each respective block B_m,_n to supply decoded difference data to the first input of the adding circuit 95. The circuit 95 adds the minimum value data MIN_m,_n to the decoded data in order to reproduce the image data a¡,j and the interpolated data (a_i,j + a_i,j+1)/2 corresponding with the image data bp,q which are utilized by the lower level system. As thus reproduced, the data bp,q are supplied via the output terminal 96 to the video RAM 32a of Figure 7.

In the lower level system, therefore, the control circuit 100 operates the circuit 90 in response to the ID to produce the image data bp,q useable by the lower level system. It will be appreciated that the circuit of Figure 18 is able to produce the image data bp,q without the need to employ circuitry to derive such data by carrying out an inverse of an interpolation process, so that the lower level system is thereby advantageously simplified.

The image data recorded on the tape 1 by the upper level system as illustrated hereinabove in connection with Figures 14 to 17 is likewise reproducible by the upper level system with the use of the data processing circuit illustrated in Figure 19 which is included in certain advantages forms of the still picture processing circuit 31 of Figure 3. The data processing circuit of Figure 19 serves to carry out an operation which is the inverse of the above described interpolation process, in addition to decoding the quantized data reproduced from the tape 1. Accordingly, the data processing circuit of Figure 19 includes a rearraying circuit 110 which serves to rearray the quantized data Q¡,j and quantized interpolated data (Q,j + Q_i,j+1)/2 in the manner illustrated in Figure 16 for the corresponding image data. The data processing circuit of Figure 19 further includes a circuit 120 which carriers out adaptive dynamic range decoding and deinterpolating circuit 130 which serves to reproduce the image data a_i,j having the data rate SCK₁ from the decoded data produced by the circuit 120. More particularly, the rearraying circuit 110 includes a serial to parallel converter 112 for converting the quantized data, quantized interpolated data, dynamic range data and minimum value data supplied in serial form at an input terminal 111 into parallel form. An output of the converter 112 is coupled to a RAM 113 to supply the parallel data thereto which it stores temporarily before decoding by the circuit 120.

The circuit 120 includes a changeover switch 121 having a moveable terminal coupled to a data output of the RAM 113 and having first and second fixed terminals coupled to an adaptive decoder 122 to supply the quantized data, quantized interpolated data and dynamic range data thereto. The decoder 122 serves to decode the quantized data and the quantized interpolated data based on the dynamic range data and supplies the decoded data to a first input of an adding circuit 123. The switch 121 has a third fixed terminal coupled to a second input of the adding circuit 123 to provide the minimum value data thereto.

The deinterpolating circuit 130 includes a delay device 131 coupled to an output of the summing circuit 123 and operative to delay data supplied thereto by one pixel interval. An output of the delay device 131 is coupled to an input of a multiplier 132 and a first fixed terminal of a selector switch 135. The multiplier 132 is operative to multiply the delayed data from the device 131 by a coefficient of two, and outputs the multiplied data to a non-inverting input of a subtracting circuit 134. An inverting input of the subtracting circuit 134 is coupled to the output of the tiding circuit 123 and an output of the subtracting circuit 134 is coupled to a second fixed terminal of the switch 135. A moveable terminal of the switch 135 is coupled to an output terminal 136 of the deinterpolating circuit 130, so that the switch 135 is operative to provide thereto either the output of delay device 131 or that of the subtracting circuit 134.

The quantized data Q¡,j and quantized interpolated data (Q_i,j + Q_i,j+1)/2, the dynamic range data DR_m,_n and the minimum value data MIN_m,_n are supplied as serial data in the form illustrated in Figure 17 to the input terminal 111 from the PCM processing circuit 33 of Figure 3. The serial to parallel converter 112 converts the received data into parallel data which it supplies to the RAM 113 for storage temporarily therein. The RAM 113 stores the data Q¡,j and (Q¡,j + Q_i,j+1)/2 in a manner corresponding with the spatial positions of their respective image data a¡,j and (a¡,j + a_i,j+1)/2 as illustrated in Figure 16. On a block by block basis, the quantized data, quantized interpolated data and the dynamic range data are read from the RAM 113 and supplied via the switch 121 to the adaptive decoder 122, while the minimum value data of each block is supplied via the switch 121 to the adding circuit 123.

The adaptive decoder 122 serves to decode the quantized data and quantized interpolated data in each respective block B_m,_n based on the dynamic range DRmn thereof to supply decoded difference data to the adding circuit 123. The adding circuit 123 thereupon adds the corresponding minimum value MIN_m,_n to the decoded difference data to reproduce the image data a_i,j and (a_i,j + a_i,j+1)/2 as illustrated in Figure 16, which in turn are supplied by the adding circuit 123 to the delay device 131 and the subtracting circuit 134 of the deinterpolating circuit 130.

The delay device 131 delays the image data a_i,j and interpolated data (a_i,j + a_i,j+1)/2 by one pixel interval as supplied thereby to the multiplier 132. It will be apparent, for example, that when the image data a₁,₃ are supplied at the output of the adding circuit 123 to the inverting input of the subtracting circuit 134, the non-inverting input thereof receives the delayed and multiplied interpolated data ((a_l,₂ + a_1,3)/2)x2, so that the subtracting circuit 134 supplies the reproduced image data a_1,2 at the output thereof. Accordingly, the original pixel data a_i,j are recovered by the deinterpolating circuit 130 from the interpolated data (a_i,j + a_i,j+1)/2 and the image data a_i,j+1. At other times the selector switch 135 selects the image data a_i,j which were not replaced by interpolated data when recorded on the tape 1 from which they are now reproduced by the upper level system. The reproduced image data a,j are supplied by the selector switch 135 via the output terminal 136 to the video RAM 32 of Figure 3.

While it is necessary in the circuit of Figure 19 to provide the RAM 113 for rearraying the quantized data and to provide the deinterpolating circuit 130 to reconstruct the original data a_i,j from the interpolated data, it will be appreciated that the upper level system does not become unduly complex as a consequence since it is intrinsically a highly functional and expensive apparatus.

According to the disclosed embodiment of the present invention, second image data having a data rate SCK₂ are formed from first image data having a relatively higher data rate SCK₁ by means of the still image video processing circuit 31 and the video RAM 32 of Figure 3. The recording and reproducing sub- system 40 of Figure 3 records the second image data together with at least a portion of the first image data on the tape 1, as well as corresponding area-discriminating ID in the respective recording areas of the first and second image data on the tape 1, the area-discriminating ID being produced by the system controller 52 and the PCM processing circuit 33 of Figure 3. Accordingly, recordings made in the foregoing manner on the tape 1 by an upper level system may be reproduced by a lower level system operating at a slower data rate, thus to achieve interchangeability of recordings between upper and lower level systems. This capability is realized without the necessity to provide processing circuitry, such as an interpolator, to form the image data having a suitably low data rate from image data produced by the upper level system having a higher data rate, since the accompanying ID recorded on the tape permit the ready selection of image data in a form which may be reproduced by the lower level system.

It will be appreciated that the signal processing functions of the present invention may be carried out either by hardwired circuits or with the use of microprocessor, microcomputer or the like. It will also be appreciated that the flow charts shown in the figures and described herein are intended to provide general explanations of the manner in which the disclosed apparatus operate. The particular steps as set out in these flow charts may be varied; their particular order or sequence may be modified; and various steps may be omitted or added.