Nova Patents
EP0484652A3

First-in-first-out buffer

Abstract

A first-in-first-out buffer is described for transferring data between two asynchronous clock regimes. The buffer comprises a first register file, for transferring data from the slow to the fast clock regime, and a second register file for transferring data in the opposite direction. The write addresses for the first register file are produced by a counter in the slow clock regime, and converted back to standard binary, and a predetermined offset is added to the result, so as to produce a read address for the first register file. This is also used as the write address for the second register file. The read address for the second register file is produced by adding a predetermined offset to the output of the counter. Thus, the read and write addresses of the two register files are always in a fixed relationship, so that it is not necessary to provide special logic for detecting the buffer full and buffer empty conditions.

Term

Term ended

Projected expiry passed 6 September 2011, 15 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

Every citation, both ways

Citations
DocumentRelationOfficeCategoryCited during
EP0383260A2CitesEuropean Patent Office (EPO)ASearch report
EP0391584A2CitesEuropean Patent Office (EPO)ASearch report
US4393482ACitesUnited States of AmericaASearch report
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 16, no. 8, January 1974, NEW YORK US pages 2459 - 2460 CHRISTENSEN ET AL 'Simplified control of memory arrays'Non-patent––Search report