Data processing system with display terminals.

p0001The invention relates to a data processing system having a plurality of display units according to the preamble of claim 1.

p0002The inventive system is particularly intended for data processing equipment such as personal computers, which typically is driven by a processor unit such as a microprocessor, via a system different units, inter alia, a single screen device, ie, a monitor which is connected to the system via a video adapter. There are various systems such as ISA, MCA or EISA and various standard video adapter such as VGA or EGA common.

p0003Usually the system on transmissible addresses is limited, for example, 1 Mbyte, the first 640 Kbytes of data and further address areas is reserved for the system BIOS and other controls so that available for a monitor addresses just for driving a single monitor suffice.

p0004In practice, more and more cases where a screen display at more than one place, ie more than is needed on a monitor, the information presented should be quite different result. This meant until now that, in the usual use of the same standard video adapter at each location at least one equipped with a microprocessor and sufficient memory display unit had to be disposed, which is connected via a network to the central data processing device.

p0005The invention is therefore based on the object with multiple display units to provide a data processing system in which, despite limited address capacity of the system bus of a data processing device to control several display devices is made possible by a data processing device via standard video adapter. This can be done also in the Einplatzbetrieb.

p0006This object is achieved by a system having the features of claim 1.

p0007The inventive control binds in a flexible manner to multiple display devices via standard video adapter to the system.

p0008Preferred embodiments of the invention are characterized in the remaining claims.

p0009Further features and advantages of the invention will become apparent from the following description of embodiments of the inventive control circuit based on the drawing. Show it:<dl id="dl0001"><dt>Fig. 1</dt><dd>a basic block diagram of the inventive control circuit used data processing equipment;</dd><dt>FIG. 2</dt><dd>a drive circuit used in the apparatus of Fig. 1;</dd><dt>Fig. 3</dt><dd>is a diagrammatic representation of the address allocation in a system of a device according to Fig. 1;</dd><dt>Fig. 4</dt><dd>Timing charts for explaining the operation of the drive circuit of Fig. 2; and</dd><dt>Fig. 5</dt><dd>a comparison with FIG. 1 modified embodiment of the invention.</dd></dl>

p0010Fig. 1 shows schematically the block diagram of a data processing system, wherein the drive arrangement according to the invention with advantage is used.

p0011In a housing 10, a microprocessor 12 and a system bus 14 are preferably applied on a mother board through which the microprocessor 12 can contact information associated with the various units of the system. As an example, a peripheral unit 16, as shown, a hard disk, which is driven via corresponding lines 15th

p0012Normally in such a system, a single monitor 26 is provided as a separate unit, which is addressed by the system bus 14 via a standard video adapter 24, such as a VGA or EGA, which is located on an expansion card in the housing 10th

p0013The system 14 has, for example, a range of addresses of 1 MB, of which generally only about 50 to 100 Kbytes for the video adapter 24 are available, sufficient just for the addressing and modulation.

p0014The invention now provides the opportunity to address by inserting at least one drive circuit MVA 20 multiple monitors via their associated video adapter, each MVA-circuit the link of this video adapter produces the system 14th

p0015In the embodiment of FIG. 1, two drive circuits are shown MVA 20 and 30, each of two video adapters 24, 25 and 36, respectively, to address 37 on the VGA 24, 25 and VGA 34, 35. The number of MVA 20 and the number of them operated video adapter 24, 25 is not limited to two. For example, to use readily eight video adapter from an incinerator 20, which in turn produce the exchange of information about the system bus 14 via branched bus 17 and 18 respectively.

p0016FIG. 2 shows an exemplary embodiment of the inventive control the MVA 20 in greater detail. In particular, it can be seen that the branched bus 17 continues from the system bus 14 in the MVA 20 as a bus line 50 and branched into Teilbusleitungen 58 and 59, respectively, through which the screen display corresponding address, data and control signals to the two VGA 24 and 25 via respective lines 22, 23 can be applied.

p0017Whether or not a particular one of VGA 24 and 25 (and the associated monitor 26 or 27) is addressed, decides the circuit arrangement shown in Fig. 2.

p0018Each MVA 20 and 30 is an I / O address of the system bus address space associated with that is adjustable in a memory circuit 41, such as a register or the like (mainly permanent). A comparison circuit 42 provides over diverted from the system bus 50 address lines 52 is the incidence of data stored in the memory circuit 41 I / O address and activates a selection register 44, in the above lines 54 a selection identifier is entered. In an n-number of monitors on the associated MVA 20 is this selection identifier, a binary 1-of-n, in the case of the embodiment thus "01" or "10".

p0019Should one of four monitors are driven by a MVA 20, then won the selection register 42 has a capacity of four bits by, for example, "0100" to take a 1-of-4 code. When operating several MVA receive all except one, ie the activated the identifier "0000".

p0020Each bit position corresponds to a different video adapter and is provided with a associated therewith activation circuit 48 or 49 connected via a line 45 or 56, which circuit 48, 49 may be a gate circuit in the simplest case, the output of the associated VGA 24 or 25 is activated or disabled to be forwarded to her pending on lines 58 and 59 of information (addresses and data). The actual timing for this via line 57 leading from the bus 50 to both circuits 48 and 49th

p0021On the basis of Figures 3 and 4 will be explained below 20 the corresponding address mapping as well as the timing in the control of VGA 24 and 25 on the MVA.

p0022As mentioned above, consists in the operation of multiple VGA monitors, or a problem that in the definition of the address space only an address area was provided for a video adapter, that is that several different address window can not simultaneously for multiple VGA be accommodated in the address space of the system bus.

p0023According to the invention the address window will now be addressed for multiple video adapter in an additional second dimension, wherein the addressing in the second dimension of the drive circuit of the present invention MVA is carried out 20 and 30 respectively.

p0024Fig. 3 shows in the Y direction, the usual division of the address space (first pillar) with addresses of registers that can be addressed via I / O signals. Above and beyond the actual data address space is the address window for the video RAM of the VGA and above a range of addresses for the BIOS it is finally provided that the data processing device's firmware to perform the basic operations.

p0025As previously mentioned, a second dimension in the direction of the X-axis will now be introduced, so that in each case the same Y-addresses are valid for a plurality of VGA 24, 25 and monitors 26, 27, the assignment to a specific VGA However, by means of the MVA and corresponding I / O register contents occurs, which can directly assign the programmer.

p0026In this context it should be noted that the selected by the microprocessor 12 to a video adapter, z. B. VGA saved 24 transmitted image information therein and is transmitted continuously from this image forming on the associated monitor under Refresh (refreshing), so that a still image is shown. Meanwhile, the microprocessor 12 enough time with appropriate register selection to supply on the same Y address more VGAs and monitors with image information.

p0027Referring to Figures 2 to 4, a selection and transfer process for the image information to a plurality of adapters to be described now summarized.

p0028As mentioned previously each MVA 20, 30 an I / O register address is assigned. Once it appears on the bus 50 and thus on lines 52, the comparison circuit 42, coincidence with the address stored in the memory circuit 41 and also enables the register 44, in which then appropriate via the lines 54 of the I / O register address register content is written in the form of "01" or "10". Reconciliation 45 is a signal of Fig. 4a is applied to the gating circuit 48, while over line 56 complementary thereto as shown in FIG. 4b, no signal occurs. Alternatively, could the register be downstream of a 1-of-n decoder that activates the desired VGA.

p0029As soon as via the bus 50 on line 57 which is removed from the bus 50, a corresponding timing signal (Fig. 4c) is applied to the circuits 48 and 49 outputs the gating circuit 48 is a signal shown in FIG. 4d from, whereby via the manifolds 22 of the VGA 24 is activated for receiving the respective adapter-Adreßfensterbereich image information.

p0030In a reverse identifier, the same process occurs as shown in FIG. 4b, c and e for the units 49 and 25. It should be noted that when a plurality of MVA 20, 30 are not exactly mentioned MVA 30 in its associated register 44, the identifier "00" receives, so that both control circuits 48 and 49 and therefore also the associated VGA 34 and VGA 35 remain inactive ,

p0031Thus it is possible, no video adapter VGA 24, etc. to control. In this case, the register 44 of all MVA are assigned the identifier "00".

p0032Alternatively to the gate effect of the gating circuits 48 and 49 can also be formed such that a deactivation of the VGAs the addresses supplied via the bus 50 are pushed out by addition of the address window of the associated adapter.

p0033Fig. 5 shows a relation to Figures 1 and 2 modified embodiment, in which each MVA 120 exactly one VGA 24 selects and controls. In this case, the MVA may be 120 advantageously placed on the circuit board 110 of the video adapter VGA 24th The circuit of MVA 120 very simplified, since only an ON / OFF state must be generated upon activation of the desired MVA 120th