EP0472941A2

VHF/UHF plasma process for use in forming integrated circuit structures on semiconductor wafers.

Abstract

A method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm. By carrying out plasma-assisted processes using plasma operated within a range of from about 50 to about 800 MHz, the electrode sheath voltages are maintained sufficiently low, so as to avoid damage to structures on the wafer, yet sufficiently high to preferably permit initiation of the processes without the need for supplemental power sources. Operating in this frequency range may also result in reduction or elimination of microloading effects.

EP0472941A2, drawing sheet 1
Sheet 1 of 4

Term

Term ended

Projected expiry passed 31 July 2011, 15.2 years ago.

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48 claims: 21 independent, 27 dependent

  1. 1
    A process for fabricating integrated circuit devices on semiconductor wafers in a vacuum chamber containing an electrode upon which a semiconductor wafer is mounted which comprises maintaining a plasma in said chamber energized by one or more power sources connected to said electrode and operated within a frequency range of from 50 MHz to 800 MHz.
  2. 4
    The process of one of the preceding claims, wherein said plasma is also coupled to another power source operated outside the frequency range of from 50 MHz to 800 MHz.
  3. 5
    A plasma-assisted RIE process for etching materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using a power source having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 76 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from 2 to 500 milliTorr. **
  4. 8
    The process of one of claims 5 to 7, wherein said pressure in said chamber ranges from 20 to 200 milliTorr.
  5. 9
    The process of one of claims 5 to 8, wherein said power density ranges from 45 to 56 watts/inch² of wafer area.
  6. 10
    The process of one of claims 5 to 9 wherein said RIE process comprises a process for etching silicon oxide at an etch rate of from 0.3 to 0.75 µm/minute.
  7. 12
    The process of one of claims 5 to 11, which further comprises flowing a source of fluorine, an optional source of hydrogen, a source of carbon, an optional source of oxygen, and an optional inert gas through said chamber while said plasma is ignited therein.
  8. 14
    The process of one of claims 5 to 8 wherein said RIE process comprises a process for etching polysilicon and/or aluminum at an etch rate of from 0.2 to 1.0 µm/minute.
  9. 17
    The process of one of claims 14 to 16 which further comprises flowing a chlorine-containing gas and an optional inert gas through said chamber while said plasma is ignited therein.
  10. 18
    A plasma-assisted high pressue process for etching materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 15 to 76 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of over 500 milliTorr to about 50 Torr.
  11. 23
    The process of one of claims 20 to 22 which further comprises flowing a source of fluorine, a source of carbon, an optional source of hydrogen, and an optional inert gas through said chamber during said etch.
  12. 24
    The process of one of claims 20 to 23 wherein said high pressure plasma process comprises a selective process for etching silicon oxide in preference to polysilicon or photoresist wherein the atomic ratio of carbon to fluorine ranges from 0.1:1 to 2:1 and the atomic ratio of hydrogen present to fluorine ranges from 0.1:1 to 0.5:1 to obtain a ratio of silicon oxide etch (thickness) rate to polysilicon or photoresist etch (thickness) rate of from about 2:1 to over 30:1.
  13. 28
    The process of one of claims 25 to 27 which further comprises flowing a source of chlorine and an optional inert gas through said chamber during said etch.
  14. 29
    A plasma-assisted low pressure CVD process for depositing materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 76 watts/inch² of wafer area in a vacuum deposition chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from 2 to 500 milliTorr.
  15. 34
    The process of one of claims 31 to 33 wherein said power density ranges from 45 to 56 watts/inch² of wafer area.
  16. 35
    The process of one of claims 31 to 34 which further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through said chamber while said plasma is ignited therein.
  17. 39
    The process of one of claims 36 to 38 wherein said power density ranges from 30 to 76 watts/inch² of wafer area, preferably from 45 to 56 watts/inch² of wafer area.
  18. 40
    The process of one of claims 36 to 39 which further comprises flowing one or more sources of silicon, one or more sources of nitrogen, an optional source of hydrogen, and an optional inert gas through said chamber while said plasma is ignited there.
  19. 41
    A plasma-assisted high pressure CVD conformal isotropic process for depositing materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 38 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of over 500 milliTorr to about 50 Torr.
  20. 44
    The process of one of claims 41 to 43 wherein said process further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through the chamber.
  21. 46
    The process of one of claims 41 or 42 wherein said plasma-assisted high pressure conformal isotropic deposition process comprises a process for depositing silicon nitride at a deposition rate of from 0.5 to 1.0 µm/minute.
Independent claims21