Programmable power reduction circuit for programmable logic device

The present invention relates generally to integrated circuit devices and more specifically to programmable logic devices which are configurable by a user.

Programmable logic devices are becoming increasingly popular in the electronics industry because of their flexibility. These devices allow a user to configure a standard part to perform a wide variety of standard logic functions. Since a single standard device can be configured many different ways, the total cost of using such a device in a system can be significantly less than the cost of custom design parts, especially when the product volume is not large. If changes or update are needed to the programmed logic function, some types of devices can be reprogrammed.

Typically, a logic function for a programmable logic device will not utilize all the input lines of the programmable logic device. These unutilized input lines are termed "don't care" inputs because they do not have an effect in the logic functions programmed in the programmable logic device.

As is known in the art, the components which define a logic device as well as the device itself consume power during operations of the device. The problem with the unutilized or "don't care" inputs is that the components corresponding to those inputs consume power during normal operation of the device, even though the inputs are not used in the programmed logic function. Consequently, the actual power needed by the programmable logic device to perform its logic function is unnecessarily increased by the components of the unutilized inputs.

Thus a need exists for a mechanism which shuts off power to the circuitry corresponding to an unused input, thus lowering the power consumed by a programmable logic device. Moreover, it is desirable that such a mechanism not adversely effect normal operation of the device.

US-A-4763020 discloses a programmable logic array with a plurality of pairs of input lines. One of the lines of each pair carries a non-inverted signal whilst the other line of each pair carries an inverted signal. If a pair of input lines is connected to a non-used input, the pair of input lines is set to a low level.

It is therefore an object of the present invention to provide a method to determine if an input will be used in a logic device.

It is another object of the present invention to provide a method to disable an input buffer when an input will not be used in a logic device.

It is another object of the present invention to disable an input buffer without adversely affecting normal operation of the device.

Therefore, in certain embodiments of the present invention, during programming of a programmable logic device, programming information corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.

The present application contains subject matter in common with copending EP Application No 90314143.0 published under EP-A-0 448 879.

According to a first aspect of the present invention, there is provided a programmable logic device comprising: <ul id="ul0001" list-style="none" compact="compact"><li>a plurality of inputs;</li><li>a logic array, connected to said inputs, to define a logic function thereof;</li><li>a storage element connected to each input for storing configuration information for selectively disabling its associated input;</li><li>a plurality of outputs connected to said array, characterised in that there is provided;</li><li>a programming buffer for holding programming data to program a portion of the device;</li><li>a plurality of memory elements connected to said programming buffer for storing a copy of the programming data held previously by the programming buffer;</li><li>comparison circuitry connected to said programming buffer and said memory elements for generating a comparison signal indicative of a match between data in said programming buffer and data in said plurality of memory elements; and</li><li>means for storing configuration information in said storage elements based upon the comparison signal.</li></ul>

According to a second aspect of the present invention, there is provided a circuit block for a programmable logic device, comprising: <ul id="ul0002" list-style="none" compact="compact"><li>a programming buffer for holding programming data to program a portion of the device;</li><li>a plurality of storage elements connected to said programming buffer for storing a copy of the programming data held previously by the programming buffer; and</li><li>comparison circuitry connected to said programming buffer and said storage elements for generating a comparison signal indicative of a match between data in said buffer and data in said plurality of storage elements, the said programming of a portion of the device being enabled or disabled based on said comparison signal.</li></ul>

According to a third aspect of the present invention, there is provided a method for determining whether an input to a programmable logic device will be used in a logic function, comprising the steps of: <ul id="ul0003" list-style="none" compact="compact"><li>loading programming data for a first row corresponding to the input into a programming buffer;</li><li>comparing the loaded data to data previously loaded corresponding to a different row which is complementary to the first row; and</li><li>if the loaded data matches the row which is its complement, then generating a signal indicating that the input will not be used for programming said first row.</li></ul> will remain low, indicating the two groups of programming data are needed in the programmed logic function. Alternatively, if the address comparator <b>108</b> indicates that the elements <b>88</b>, <b>90</b> and elements <b>92</b>, <b>94</b> are not complements of each other, the signal match will remain low.

If the AND/OR array <b>10</b> is constructed using EPROM or EEPROM technology, the memory cell <b>28</b> should be an EPROM or EEPROM component as well. Alternatively, if the AND/OR array <b>10</b> is an SRAM based device, the memory cell <b>28</b> should be SRAM also. If desired, the SRAM memory cell can have a battery back-up, so that when the device is turned off the data stored in the memory cell <b>10</b> will be saved. Co-pending application EP 90 314 143.0 describes the design and operation of a preferred design for an SRAM based programmable logic device.

The invention is described in terms of an automatic method for determining whether an input signal is used, and then enabling or disabling an input buffer based on the use or non-use of its corresponding signal line. However, the enable/disable information could be programmed directly into the memory cell <b>28</b> when programming the programmable logic device <b>11</b>. Furthermore, the invention is not limited to use with logic devices containing AND/OR arrays. This invention could be used with other types of logic devices.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: <ul id="ul0004" list-style="none"><li><b>Figure 1</b> is a simplified block diagram of a programmable logic device embodying the invention;</li><li><b>Figure 2</b> is a block diagram of a logic circuit for disabling an input buffer embodying the present invention;</li><li><b>Figure 3</b> is a block diagram of an alternative logic circuit for disabling an input buffer embodying the present invention;</li><li><b>Figure 4</b> is a simplified block diagram of comparison circuitry used to determine if an input and its complement are unutilized; and</li><li><b>Figure 5</b> is a block diagram of a logic circuit for determining if an input and its complement are unutilized.</li></ul>

Referring to <b>Figure 1</b> a portion of a programmable logic device <b>11</b> is shown. Input pads <b>24</b>, <b>26</b> are connected to input buffer <b>20</b>, <b>22</b> respectively. Each input buffer <b>20</b>, <b>22</b> provides a true signal line <b>14</b>, <b>18</b> and a complement signal line <b>12</b>, <b>16</b>. Only two input pads <b>24</b>, <b>26</b> and input buffers <b>20</b>, <b>22</b> are shown in Figure 1, but an actual device typically has a much larger number.

Each of the signal lines <b>12-18</b> is connected to an AND/OR array <b>10</b>. A user can configure the AND/OR array <b>10</b> to perform a particular logic function. When programmed, it is common to have input signal lines which are not utilized in the logic function. According to the present invention, memory cells <b>28</b>, <b>30</b> are used to store a bit indicating use or nonuse of a signal line <b>14</b>, <b>18</b> and its complement <b>12</b>, <b>16</b>. If a signal line <b>14</b>, <b>18</b> and its complement <b>12</b>, <b>16</b> will be used, the bit in the memory cell <b>28</b>, <b>30</b> will enable the input buffer <b>20</b>, <b>22</b>. If however, the signal line <b>14</b>, <b>18</b> and its complement <b>12</b>, <b>16</b> will not be used in the logic function, the input buffer <b>20</b>, <b>22</b> that corresponds to the unused lines will be disabled.

Output signal lines <b>32</b>, <b>34</b> from the AND/OR array <b>10</b> are connected to output logic macrocells <b>36</b>, <b>38</b>. Output buffers <b>40</b>, <b>42</b> are connected between the output logic macrocells <b>36</b>, <b>38</b> and the output pads <b>44</b>, <b>46</b>.

Should a user require feedback or additional input lines, signal lines <b>48</b>, <b>50</b> are connected to the output logic macrocells <b>36</b>, <b>38</b>. Once again, input buffers <b>52</b>, <b>54</b> are connected to the output logic macrocells <b>36</b>, <b>38</b> and generate signal lines <b>62</b>, <b>66</b> and complements <b>60</b>, <b>64</b> respectively. Memory cells <b>56</b>, <b>58</b> store a bit which can enable or disable the input buffers <b>52</b>, <b>54</b> based on the signal lines used in by programmed logic function.

<b>Figure 2</b> illustrates one implementation of the input buffer <b>20</b>. A NAND gate <b>70</b> is connected to the memory cell <b>28</b> and input pad <b>24</b>. When a signal line <b>14</b> and its complement <b>12</b> are not used by the programmed logic function, a bit MATCH <b>74</b> is generated and stored in the memory cell <b>28</b>. The signal DISABLE is preferably taken from the complement output of cell <b>28</b>, so that DISABLE is complementary to MATCH. The signal DISABLE <b>68</b> is set low thereby keeping the output of the NAND gate <b>70</b> high. An inverter <b>72</b> is connected to the NAND gate <b>70</b>, and the output of the inverter <b>72</b> is signal line <b>14</b>. To get the complement of signal line <b>14</b>, an inverter <b>76</b> is connected to inverter <b>72</b>, and a signal is generated on line <b>12</b> is generated.

<b>Figure 3</b> shows an alternative input buffer <b>52</b> which can be used when either an input signal line <b>24</b> or a feedback line <b>110</b> is needed. Input line, or pad, <b>24</b> is connected to NAND gate <b>112</b>, which in turn is connected to NAND gate <b>114</b>. The DISABLE signal from storage element <b>28</b> is connected to NOR gates <b>116</b>, <b>118</b>. A signal FB Enable is connected to NOR gate <b>116</b> and inverter <b>120</b>, which is in turn connected to NOR gate <b>118</b>. The feedback signal on line <b>110</b> is connected to NAND gate <b>122</b>, as is the output of NOR gate <b>118</b>. NOR gate <b>116</b> is connected to NAND gate <b>112</b>, and NAND gate <b>122</b> is connected to NAND gate <b>114</b>.

For this buffer <b>54</b>, DISABLE has the same value as MATCH. If DISABLE is high, both NOR gate outputs are held low, holding NAND gates <b>112</b> and <b>122</b> low, and the output of NAND gate <b>114</b> high. If DISABLE is high, either the signal on pad <b>24</b> or the FB signal is connected to the output of gate <b>114</b>, depending on the value of FB Enable. Thus, DISABLE disables both input signals, or neither, depending on its value.

<b>Figure 4</b> depicts a simple block diagram of circuitry used for determining whether signal lines are used by the programmed logic function. Programming data is shifted into the serial shift register <b>82</b> as known in the art. A copy of the data is stored in the random access memory <b>84</b> while the data is programmed into the AND/OR array <b>10</b>. Then a second group of programming data is loaded into the shift register <b>82</b>. The addresses of the two groups of programming data are compared to insure the two groups are complementary. Addressing of the programming data is known in the art. If the two groups are complements of each other, the comparison circuitry <b>86</b> compares each element of the first group of programming data with corresponding elements in the second group of programming data. If the two groups of data are identical, they are not needed by the programmed logic function and the bit MATCH <b>74</b> is set. The second group of programming data is then programmed into the AND/OR array <b>10</b>. The value of MATCH is programmed into the enable/disable bit for the input buffer corresponding to the first and second groups at the time the second group is programmed into the array <b>10</b>.

<b>Figure 5</b> illustrates the shift register <b>82</b>, the random access memory <b>84</b>, and the comparison circuitry <b>86</b> in greater detail. Only two elements <b>88, 90</b> in the shift register and two elements <b>92, 94</b> in the random access memory are shown in <b>Figure 5</b>, but an actual device typically has a much larger number.

Exclusive NOR gates <b>96, 98</b> in the comparison circuitry <b>86</b> are connected to elements <b>88, 90</b> in the shift register <b>82</b> and elements <b>92, 94</b> in the random access memory <b>84</b>. If elements <b>88, 90</b> have the same values as elements <b>92, 94</b> respectively, the output <b>100, 102</b> of the exclusive NOR gates <b>96, 98</b> will be high. Outputs <b>100, 102</b> are connected to AND gate <b>104</b>. When outputs <b>100, 102</b> are both high, indicating elements <b>88, 90</b> and elements <b>92</b>, <b>94</b> match, the output of AND gate <b>104</b> is high. AND gate <b>106</b> is connected to AND gate <b>104</b> and an address comparator <b>108</b>. If the address comparator <b>108</b> indicates elements <b>88, 90</b> are complementary to elements <b>92, 94</b>, the signal MATCH <b>74</b> is generated indicating the two groups of programming data are not used in the programmed logic function. MATCH is inverted to generate the signal MATCH of <b>Figures 2</b> and <b>3</b>, and, is connected to the memory cell <b>28</b> corresponding to the input addressed by the groups of programming data currently found in the shift register <b>82</b> and the memory <b>84</b>.

If any pair of the elements <b>88, 90</b> and elements <b>92, 94</b> have different values and thus do not match, the output <b>100, 102</b> of one or more of the exclusive NOR gates <b>96, 98</b> will be low. In this case, the signal MATCH <b>74</b>