Method and apparatus for correcting for clock and carrier frequency offset, and phase jitter in multicarrier modems.

0001The invention pertains generally to data transmission and reception, and, more particularly, to the reception of high speed data that has been used to modulate many carriers. This method of modulation is know by many names-Orthogonally Multiplexed Quadrature Amplitude Modulation (OMQAM), Dynamically Assigned Multiple QAM (DAMQAM), Orthogonal Frequency Division Multiplexing (OFDM); herein it is referred to as multicarrier modulation.

0002In general, oscillators (frequency sources) in the transmitting and receiving modems of a data communication link cannot by synchronized, and the receiving modem must use special circuitry or signal processing algorithms to of the received signal; this task is often referred to as clock and carrier recovery.

0003The task is complicated by the introduction in some transmission media, most notably the General Switched Telephone Network (GSTN), of frequency offset and phase jitter as shown in Fig. 1. Frequency offset, designated herein as f, is the difference between the frequency(ies) of the received carrier(s) and the reference carrier(s) generated in the local receiver; it may be caused by (a) a frequency difference between the carrier(s) used in the transmitter and the reference carrier(s) in the receiver and/or (b) a mismatch between the frequencies of the modulating and demodulating carriers in Frequency Division Multiplexing (FDM) equipment in the network; on the GSTN the resultant combined offset may be as much as 5 Hz. Phase jitter is seen as phase modulation of the received signal, and often has a few discrete, identifiable frequency components; the power supply frequency and telephone ringing frequency (60 Hz and 20 Hz, respectively, in the U.S.A.) are common components. The carrier recover circuitry or algorithms must track, or follow frequency offset and phase jitter in order to ameliorate their effect on the received signal.

0004Circuitry and algorithms for recovering clock and carrier (including tracking frequency offset and phase jitter) from data-modulated single-carrier signals have been well documented in the literature (see J.A.C. Bin- gham, The Theory and Practice of Modem Design, John Wiley, 1988). Nearly all of the prior art uses phase-locked loops (PLLs) of one form or another, and designers have long recognized the harmful effects of delay inside those loops. For carrier recovery it was agreed that tracking of phase jitter is made much more difficult, maybe even impossible, if the delay of an adaptive equalizer (typically about 10 ms) is included in the loop; therefore special algorithms (see, for example, D.D. Falconer, "Jointly Adaptive Equalization and Carrier Recovery in Two-Dimensional Communications Systems", Bell Syst Tech J., vol. 55, pp. 317-314, March 1976) were developed to remove this delay from the loop.

0005In multicarrier modulation, data are grouped into blocks of bits; in the systems described by Baran (U.S. Patent 4,438,511) and Hughes-Hartogs (U.S. Patent 4,679,227) the blocks may comprise more than one thousand bits. Each carrier is modulated by just a few of those bits, and the modulation is held constant for the duration of one block; this duration, or symbol period, may therefore be several hundred times the symbol period of a single-carrier modem. Furthermore, the symbol period may be much greater than the periods of the components of the phase jitter that are to be tracked.

0006Signal processing in the multicarrier receiver must be performed at the symbol rate, and information about the received signal-data contained therein and imperfections (frequency offset, phase jitter, etc.) thereof-is available only after each block has been performed at the symbol rate, and information about the received signal-data contained therein and imperfections (frequency offset, phase jitter, etc.) thereof-is available only after each block has been processed. This delay of one symbol period, which may be as large as 130 ms (more than ten times the delay through most adaptive equalizers), therefore appears inside the carrier recovery loop, and makes conventional jitter tracking impossible.

0007The long symbol period associated with multicarrier modulation makes the tracking of phase jitter imposed on multi-carrier signals a much more difficult problem than forsingte-carrier signals. One proposal (B. Hirosaki, et al, "A 19.2 kbit/s Voiceband Data Modem Based on Orthogonally Multiplexed QAM Techniques", IEEE Intl. Conf. Commun. Rec., pp. 661-665, Aug. 1985) was to input an unmodulated pilot tone to a set (one for each carrier) of adaptive jitter predictors, and feed the output signals forward to cancel the jitter on each modulated carrier. This approach has several disadvantages: the amount of information about the jitter available from one pilot placed at the edge of the available frequency band is very small, the tapped-delay-line form of the predictors is poorly suited to filtering single-tones, and the approach requires a large amount of computation-particularly if a large number of carriers is used.

0008Another problem is that the jitter frequencies are not Subspace Approach to Multiple Emitter Location and Spectral Estimation", Ph.D. Thesis, Stanford University, 1981, and the ESPRIT algorithm described by R. Roy, A. Paulraj and T. Kailath in "ESPRIT-A Subspace Rotation Approach to Estimation of Parameters of Cisoids in Noise", IEEE Trans. ASSP, vol. ASSP-34, p. 1340-1342, Oct 1986) but they all require a very large amount of computation, and the particular problem of determining the frequencies of phase jitter has not been addressed.

0009Many of the early objections to multicarrier modulation were based on the assumption that correction for phase jitter was impossible because the problems of long symbol time and unknown jitter frequencies had not been, and probably could not be, satisfactorily solved.

0010In accordance with the preferred embodiment of the present invention, the problem of the symbol delay occurring inside the carrier recovery loop is solved by combining the concepts of the block processing needed for the efficient detection and decoding of multi-carrier signals with those of the serial processing needed to generate the local correcting signals that have the required compensating offset and jitter. In the present invention this is done by using feed-back (also known as closed-loop) algorithms or circuits in a combination of serial and block modes.

0011These feedback algorithms are designed, however, primarily for continuous operation while receiving data-modulated signals; their adaptation is fairly slow, and they presuppose a knowledge of the frequencies of the phase jitter components that are to be tracked.

0012Therefore, upon connection of a channel forthe transmission of data, the data signal is preceded by a training signal comprising a few pilot tones. In the receiver these tones are separated by filtering, their phases are calculated as functions of time, and those functions are analyzed to form initial estimates of (a) clock offset, (b) carrier offset, and (c) the amplitudes, frequencies and phases of all significant components of phase jitter.

0013These estimates are then used to initialize the circuits or algorithms which generate a phase-correcting signal. This signal is used during the reception of data-modulated signals as follows: <ul id="ul0001" list-style="none"><li>1. In the serial mode, samples of the received signal are multiplied by the phase-correcting signal, which comprises components at the jitter and offset frequencies, to produce samples of a corrected signal.</li><li>2. A block of these corrected samples is then demodulated and decoded (as described, for example, in U.S. Patent 4,679,227) to produce a block of estimated received data. These data, togetherwith the demodulated (but not decoded samples), are used both to update the estimates of the amplitude and phase characteristics of the channel, and as inputs to the algorithm orcircuitfor estimating carrier and clock offsets described in paragraph 5 below.</li><li>3. The block of received data is then remodulated to produce a sequence of samples of a reference signal, and in a serial mode the phases of these samples are compared to the phases of the corrected samples to generate a sequence of samples of phase error.</li><li>4. These samples of phase error are then analyzed to calculate required updates for the parameters of the algorithm or circuit that is used to generate the phase-correcting signal.</li><li>5. The differences between the demodulated and the decoded data are analyzed and filtered to form estimates of the remanent carrier and clock frequency offsets. The estimate of carrier offset is used to update a parameter of the circuit or algorithm that generates the phase-correcting signal and similarly, the estimate of dock offset is used to control either the original sampling time of the received signal or an interpolator which operates upon the samples.</li><li>6. The phase-correcting signal and sampling time thus updated are then used for reception of the next block of data signals, and steps 1 through 5, described above, are repeated for each subsequent block of data signals.</li></ul>

0014For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings in which: <ul id="ul0002" list-style="none"><li>Fig. 1 is a schematic block diagram representation of a data transmission link su bjected to clock and carrier frequency offsets and carrier phase jitter.</li><li>Fig. 2 is an overall block diagram of an embodiment of the present invention showing the feed-forward training mode and the feed-back data mode.</li><li>Fig. 3 shows a typical phaseltime plot for the two pilot tones for the case of just one jitter component</li><li>Fig. 4 shows a look-up table implementation of a generator of one sinusoidal component of the phase-correcting signal, with means for updating the amplitude and phase.</li><li>Fig. 5 shows a typical phase/frequency plot for many carriers.</li></ul>

0015The transmitter and receiver of a data transmission link, such as is shown in Fig. 1, each include an oscillator (usually crystal-controlled) to control the frequency at which the transmit and receive signals are sampled, the data rates of those signals, and the frequencies of the carriers that are used for modulation.

0016Circuitry or signal processing algorithms are used in the receiver to lock the sampling rate in the receiver to that in the transmitter. Clock offset, s, is defined by the ratio of the natural (i.e., unlocked) sampling rate in the receiver, fan to that used in the transmitter, f_a:<maths id="math0001" num=""><img file="EP0453203A2_D0001.tif" /></maths>

0017Circuitry or algorithms are also used to lock the frequencies of the carriers used for demodulation to those inherent in the received signal. The common frequency difference (offset) between the received carriers and the natural, unlocked frequencies of the receiver, which may be caused by a combination of the differences between the frequencies of (a) the transmitter and receiver oscillators, and (b) the oscillators in the modulator and demodulator of the FDM equipment (shown as fern and fed), is defined as Af.

0018The oscillators in the FDM equipment may be subjected to phase jitter; the sources are typically additive and their sum affects the phase of the modulating and/or demodulating carrier as shown in Fig. 1. To simplify the explanation of the invention, it will be assumed that there is significant phase jitter at only two frequencies, f₁ and f₂, and that the jitter components have amplitudes A₁ and A₂, and phases Θ₁ and Θ₂. Each component of the received signal at a frequency f, could then be represented: <ul id="ul0003" list-style="none"><li>without iitter:<maths id="math0002" num=""><img file="EP0453203A2_D0002.tif" /></maths></li><li>with jitter<maths id="math0003" num=""><img file="EP0453203A2_D0003.tif" /></maths></li><li>where, for all frequencies (of signal and jitter),<maths id="math0004" num=""><img file="EP0453203A2_D0004.tif" /></maths></li></ul>

0019As shown in Fig. 2, a real received signal, x(t), which may have been corrupted in this way, is first sampled by switch 10 at a rate f_sr (= 1/Tr) and with a timing offset, _T, and converted to a complex signal, x_p(nT_r+τ) + jx_q(nT_r+τ), by a Hilbert transformer 20 (see, for example, L.R. Rabiner and R.W. Schafer, "On the Behavior of Minmax FIR Digital Hilbert Transformers", Bell Syst. Tech. J., vol. 53, pp. 363-390, Feb. 1974). Upon first connection of a data channel the training algorithm is used; this is represented symbolically in Fig. 2 by switch 30 in the "Training" position.

Training Mode

0020The training signal, from the transmitter of Fig. 1, comprises two pilot tones at frequencies f₁ and f₂ (1000 and 2000 Hz in the first embodiment). It is sampled by switch 10, transformed by the Hilbert transformer 20, and then processed as follows: <ul id="ul0004" list-style="none"><li>1. The real and imaginary parts (also shown as the in-phase and quadrature components) of these tones are separated by band-pass filters 40-70 to generate the sampled signals y_p1(n), y_q1(n), yp₂(n), and yq₂(n). Ideally the response of each of these filters should be maximum at one of the pilot tone frequencies and zero at the other. Typical transfer functions-in terms of the z-transform variable, z, are<maths id="math0005" num=""><img file="EP0453203A2_D0005.tif" /></maths>and<maths id="math0006" num=""><img file="EP0453203A2_D0006.tif" /></maths>where Θ₁ = 2πf_i/f_s for i = 1, 2.</li><li>2. The output signals of the four filters are applied to arctangent operators 75 and 80, which calculate the phases of each pair of samples, taken at times t = nT_r+τ, the two separated tones according to φ_i(n) = arctan(yqi(n) /y_Pi(n) ); (3) The phases of a number (preferably an integer power of 2, and equal to 1024 in the preferred embodiment) of samples are calculated sequentially and stored; they are then processed as a block in processor 85 as described in steps 3-5.</li><li>3. Each phase, φ_i(n) and φ₂(n), is fitted to a linear function of time (measured in increments of T_r by the variable n) using the well known Least Mean Squared Error (LMSE) criterion (see, for example, B. Widrow and S.D. Steams, Adaptive Signal Processing, Prentice Hall, 1985); that is, φ_i(n)≈α_1n+P_i for i=1,2, (4) where α₁, p₁, a₂, and p₂ are the LMS estimates of the slope and zero-time intercept of each phase. An example of phases φ₁ and φ₂ and the best linear fit to them is shown in Fig. 3 where, for sake on clarity, only one jitter component is shown.</li><li>4. The carrier and clock frequency offsets, A f and s, are then estimated from the slopes, α₁ and α₂:<maths id="math0007" num=""><img file="EP0453203A2_D0007.tif" /></maths>and<maths id="math0008" num=""><img file="EP0453203A2_D0008.tif" /></maths></li><li>5. A spectral analysis (a Fast Fourier Transform (FFT) was used in the first embodiment) is then performed on the residual, non-linear parts of the phase functions, φ_i(n)= φ_i(n)- a,n - p₁ for i = 1, 2 to estimate the amplitude, A_jk, frequency, f_jk, and phase, Θ_jk, of the components of phase jitter (k =1, 2 for the illustrated case of two components).</li><li>6. After a few blocks (the first embodiment uses just one) of the two pilot tones have been transmitted, received, and processed the estimated values of A_jk, f_jk, and Θ_jk are used to calculate the coefficients and initial states of the sinewave generators 100 and 105. This completes the training mode.</li></ul>

0021Switch 30 is then placed in the data position, and processing continues with the reception of data modulated onto multiple carriers.

Data Mode

0022Carrier Recovery: <ul id="ul0005" list-style="none"><li>1. Hilbert-transformed samples of the data-modulated multicarrier signal, x(t), which is assumed to be impaired by carrier frequency offset and phase jitter, are sequentially applied to multiplier 110, and there multiplied by samples of the correcting signal, cosφ_c + jsinφ_c. which are generated by the look-up table 260. The output signals of multiplier 110 (the corrected samples) are assembled into a block, which is stored in delay 270 and also processed as follows:</li><li>2. The block of output signals from multiplier 110 is input to demodulator 120, which performs an FFT on the block of samples of the corrected signal, as described by E.O. Brigham in The FFT and Its Applications, Prentice Hall, 1974 (a general theory of FFTs), and by D. Hughes-Hartogs in U.S. Patent 4,679,227 (the application of FFTs to multicarrier modulation). The output from 120 is applied to decoder 130, which estimates the transmitted data, as also described in U.S. Patent No. 4,679,227.</li><li>3. The output signals from demodulator 120 and decoder 130 are applied to subtractor 125; the output signals from 125, which are the amplitude and phase differences between the demodulated and the decoded signals, are applied to processor 140, where a subroutine estimates the characteristics of the channel as described in U.S. Patent 4,679,227.</li><li>4. The estimates from the sub-routine of processor 140, which are updated after the reception of each block of data, are then applied, together with the estimates of the transmitted data from decoder 130, to a remodulator 150 which performs an inverse FFT and generates a reference signal B.</li><li>5. The phase differences from subtractor 125 are also applied to processor 160, where a linearfit subroutine calculates an LMSE fit of the phases to a linear function of frequency, af + b, as illustrated in Fig. 5. The constant term, b, is attributed to an error in the phase of the synthesized correcting signal, and a signal representative of b is applied to low-pass filter 170.</li><li>6. Phase comparator 190 then calculates, sequentially, samples of a phase-error signal which is the difference in phase between the corrected signal, A, which has been stored in delay 270, and the reference signal, B, from remodulator 150. If the two signals are represented as (xp(n) + jxq(n)) and (yp(n) + jyq(n)), respectively, then this phase difference is given exactly by<maths id="math0009" num=""><img file="EP0453203A2_D0009.tif" /></maths>However, because the loop was initializing during the training phase, the differences between the corrected and reference signals are small, and the arctangent function of equation (8) can be approximated by its argument. Furthermore it was found that the division operation in the argument of the arctangent function can be dispensed with, and a simplified indicator of the phase-error, φ_e(n) ≈ x_q(n)y_p(n) - x_p(n)y_q(n) (9) can be used; this is applied to multipliers 200 and 210.</li><li>7. In multipliers 200 and 210 the samples of the phase-error signal, φ_e, are multiplied by samples of cosine and sine waves (i.e., complex samples) at the identified jitter frequencies, which are generated by look-up tables 90 and 95. The complex products of these multiplications are then applied to low-pass filters 220 and 230, respectively. Filters 220 and 230 typically have transfer functions of the form<maths id="math0010" num=""><img file="EP0453203A2_D0010.tif" /></maths>and the gain, zero, and pole (K, z_r, and z₂) are chosen according to conventional PLL theory, as described by F.M. Gardner in Phaselock Techniques, John Wiley, 1979, so as to optimize the transient response of the loop. The operations of multiplying and low-pass filtering together constitute a correlation of the phase error signal with each of the complex jitter components. 8. Steps 6 and 7 are performed for the duration of one block, and then the output signals of filters 220 and 230 are sampled by switches 240 and 250, respectively, to produce an estimate of each component of the phase error of the correcting signal. These error components, which are calculated during one block will be used, however, to update the parameters of the correcting signal that will be used for the subsequent block. Therefore, because the block period is not necessarily an interger multiple of the period of either of the jitter components, each component must be shifted, in rotators 245 and 255, by an angle ω_jkT (=2πf_jkT), which is the angle by which each identified jitter component will rotate in one block period. The sampled and rotated error components are then used to update the parameters of sinewave generators 100 and 105, which then continue undisturbed during the next block. Sinewave generators 100 and 105 may be implemented in several different ways, and the preferred method of updating them depends on the implementation. In the preferred embodiment, shown in Fig. 4 the real and imaginary parts of the error components, ε_p and ₈q are converted to amplitude and phase errors, ₈A and ε_φ, and these errors are then used to increment the amplitude, A_lk and phase, φ_jk, of each component of the correcting signal according to<maths id="math0011" num=""><img file="EP0453203A2_D0011.tif" /></maths>and<maths id="math0012" num=""><img file="EP0453203A2_D0012.tif" /></maths>where δ is a small step-size multiplier. The updated phase, φ_jk, is then used as an address for a cosine and sinewave look-up table, and the two output signals are multiplied by the updated amplitude.</li><li>9. The real output signals of sinewave generators 100 and 105 and of filter 170 are applied to a summer 175 to form a composite correcting phase angle,<maths id="math0013" num=""><img file="EP0453203A2_D0013.tif" /></maths>which is the estimate of the phase shift required to compensate for offset and jitter. This φ_c is then applied to the sine and cosine look-up tables 260 in order to generate samples of a complex correcting signal. Clock Recovery:</li><li>The slope term, a, calculated by the linear fit algorithm 160, (described in Data Mode paragraph 5), is attributed to an error in the sampling phase, τ, and is applied to low-pass filter 180. A typical transfer function of this filter, in terms of the z variable, is<maths id="math0014" num=""><img file="EP0453203A2_D0014.tif" /></maths>and the zero, z_r, and pole, z₂, can be chosen according to standard PLL theory so as to achieve a compromise between transient response and noise bandwidth.</li><li>The output signal of this filter may be used in one of two ways (as indicated by the dotted lines in Fig. 2): <ul id="ul0006" list-style="none"><li>(a) it may be fed back to a Voltage Controlled Oscillator (VCO) 300, which is used to control the first sampling switch 10, or</li><li>(b) the switch 10 may be controlled by an unadjusted (open-loop) oscillator, and the output of the filter integrated in integrator 290 and then used to control an interpolator 310 as described, for example, in R.W. Schaferand L.R Rabiner, "A Digital Signal Processing Approach to Interpolation-, Proc., IEEE, June 1973. It will be apparent to those skilled in the art that the invention disclosed herein may be embodied in other specific forms without departing from the spirit and essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting of the scope of the invention that is set out in the following claims.</li></ul></li></ul>