Device for transmitting a pulse-width modulated electrical input signal.

p0001The invention relates to a means for transmitting a pulse width modulated electrical input signal from a source of the signal via a transformer and a threshold value to an evaluation circuit for the pulse-pause ratio of the signal that supplies an analog, the DC component of the input signal proportional output signal.

p0002If the measurement signals to be transmitted galvanically separated, it has proved to be advantageous to transmit these signals in the form of pulse width modulated signals. Commercially available devices of the type mentioned have been developed.

p0003In such devices, it may lead to distortions of the pulse-pause ratio, since not only the waveform of the pulse pause-modulated signal is modified by the einzuschleifenden transformer and since the conversion back into a binary signal the requisite threshold stage having a non-ideal switching behavior.

p0004The object of the invention is a device of the type described above so that the most accurate implementation of the pulse width modulated input signal is provided in a this proportional analog output signal.

p0005According to the invention, this object on the one hand is achieved in that with the aid of a second secondary winding of the transformer, a relative to the signal inverse to a first secondary winding signal is detected and that the two signals are respectively fed to the control input of a respective associated threshold value, wherein both threshold value stages at a defined first voltage a predetermined first output voltage and deliver a predetermined second, opposite the first output voltage at a defined second voltage and wherein the DC component of the first output voltage determines the output signal and the sum of the DC components of the first and second output voltages corrects the output signal.

p0006A further teaching of the present invention is characterized in that with the aid of a second secondary winding of the transformer, a relative to the signal inverse to a first secondary winding signal is detected and that the two signals are respectively fed to the control input of a threshold stage, wherein both threshold value stages at a defined first voltage a predeterminable first output voltage and emit at a defined second voltage a predetermined second, opposite to the first output voltage, wherein the DC component of the first output voltage determines the output signal and a controller to which the sum of the DC components of the output voltages is supplied, the output voltages in terms of elimination of the sum signal be managed.

p0007An advantageous embodiment of the invention is characterized in that both threshold value stages are integral components of a threshold. The fact that both threshold circuits therefore have a largely identical electrical behavior, the quality of gesamen reaction can be increased again.

p0008An embodiment of the invention is illustrated in the drawing and is explained in more detail below. They show:<ul><li>Figure 1 is a commercially available circuit,</li><li>2 shows the associated signal waveforms,</li><li>3 shows the inventive circuit and</li><li>4 shows the associated waveforms.</li></ul>

p0009In the illustration shown in FIG 1 is a source of pulse width modulated signals U_PBM1 shown, which signals the primary side of a transformer TR1 are fed. At the output of the transformer TR1 is then a voltage U_PBM2 , which is referenced to ground potential on the one hand and which is guided to the another via a coupling capacitor C connected to the junction of two diodes D1 and D2, the diode D1 having its cathode connected to a positive potential P and the diode D2 has its anode to a negative potential N is connected. The anode of the diode D1 and the cathode of the diode D2 lead to the input of invertierernden threshold value S1, which is also connected to the positive potential P and the negative potential of N, so that when the input voltage to the threshold value S1, a predetermined positive voltage exceeds the negative potential N as an output signal applied to the threshold value S1, while when the input signal falls below the threshold value S1 to a predetermined negative value, the positive potential P is present at the output of the threshold value S1. The thus resulting output voltage is in the representation of U_A1 designated. This output voltage U_A1 is a converter U1 fed with low-pass, which from the pulse width modulated signal at the output of the threshold stage S1 this proportional analog output signal <o>U</o> formed.

p0010To understand the circuit as shown in FIG 1 is referred to the synchronously designed charts A to C of FIG. 2 In the diagram, A over time t is the course of the voltage U_PBM1 shown. It may be present in each case for a time T1 a positive potential and for a time period T2 a negative potential. The resulting period is referred to as T.

p0011In corresponding time scale is in the diagram B shows the voltage U_PBM2 shown in dashed lines. Obviously this is that the voltage-time areas due to the transformer condition are the same in positive and negative territory. In order to achieve an approximation to the waveform shown in diagram A here, the arrangement of capacitor K and diode D1 and D2 affects the voltage waveform so using that voltage values ​​of U_PBM2 are equalized in the positive and negative area, resulting in the curve shown in the illustration shown in diagram B with a solid line.

p0012Diagram C now the output of the threshold value is shown S1, wherein switching points of the threshold value are assumed S1, as these are indicated by bold dots in diagram B.

p0013The rising edge of the voltage U_PBM1 so each case leads to a falling edge of the output voltage U_A1, The falling edge of the signal U_PBM1 each leading to a rising edge of the signal U_A1, Decisive for the understanding of the present invention, it is, however, that the delay times of these two processes are not identical. The illustration in the graph C, this is removed characterized in that the left-to-right ascending hatching error area does not correspond to the falling from left to right error area illustrated. This situation results in the example taken to the fact that too large a ratio T1: T2 at the input of the converter U1 is present and consequently the signal<o>U</o> is also too large.

p0014In the illustration shown in FIG 3 shows a circuit arrangement is shown, which in principle includes features of the circuit according to FIG. 1 Here, too, may the pulse width modulated voltage U_PBM1 a transformer, the transformer TR2 are fed in this case, on one winding one of the voltage U_PBM2 corresponding voltage U_PBM3 is provided which may be fed to a threshold stage by way of the threshold value S1 in this case, the threshold value S2, but with a variation of the positive supply voltage P is possible, as will be discussed in the following. At the output of the threshold value S2 is then, as in the threshold value S1 is a pulse-width modulated output signal U_A2 on which is a converter U2 supplied by way of the converter U1, so that at the output of the converter U2 then also the then a DC signal <o>U</o> can be tapped.

p0015To the possible insertion of a circuit arrangement of the capacitor K and diodes D1 and D2 corresponding circuit of clarity has been omitted for simplicity.

p0016In the invention is now, however, the transformer TR2 one of the voltage U_PBM3 inverse voltage U_{PBM3 *} a second winding to ground can be tapped, the value level of another threshold S3 is supplied, the closely corresponding in structure to the threshold value S2 and is therefore integrated as possible with her on a chip. The output of the threshold stage S3 applied to the input of a converter U3, which basically corresponds to the converter U1, the output signal of the threshold value S3 with U_{A2 *} is designated.

p0017The inventive concept for compensate the outset error now provides that the outputs of the converter U2 and U3 are added together and S3 influence through a regulator R the positive supply voltage of the threshold stages S2 and such that the sum signal is corrected. To describe this procedure clearly referenced charts A to E of FIG. 4 The diagram A to E are shown in time synchronization with each other.

p0018In diagram A of Figure 4 is the waveform of the signal U_PBM1 shown, which corresponds to the signal shown in diagram A of Figure 2 in its course. In diagram B, the voltage U_PBM3 shown at the output of the first winding of the transformer TR2. Diagram C is the inverse output voltage of the transformer TR2, the voltage U_{PBM3 *} shown. Due to the fact that the threshold levels of the inverse branches are not inverted but identical formed in its switching behavior, it leads to switching points, as these are shown with 1, 2, 3 and 4 for the period T in the graphs B and C.

p0019A rising edge of the signal U_PBM1 always leads to a falling edge of the signal U_A2Wherein a delay time is t1, the falling edge of the signal U_PBM1 always leads to a rising edge of the signal U_A2 with a time delay of t2. For the output voltage U_{A2 *} results in the following conditions. A rising edge of the signal U_PBM1 solves delayed by exactly the time t2, a rising edge of the signal U_{A2 *} , while a falling edge of the signal U_PBM1 to a falling edge of the signal U_{A2 *} leads, wherein while the delay time t1 is flat.

p0020From the diagrams D and E is thus readily apparent that the duration of each negative signal range of the output signal U_A2, For example, f ÜR the time T1 of the signal U_PBM1To the time t2-t1 is too large. For the voltage U_{A2 *} this results in a controversial issue, namely that the positive pulses of the pulse width modulated signal U_PBM1 triggered, also positive pulses to precisely the difference t2-t1 are too narrow.

p0021In the invention, then, an averaging of the signals according to the diagrams D and E is carried out, which takes place in the embodiment by adding the output signals of the converter U2 and U3. The averaged signal is the described initially with reference to FIG 2 errors directly proportional and could in principle the value of the signal<o>U</o> compensated by an overlay, which is indicated by dashed lines in the circuit shown in FIG. 3 In this case, could be dispensed with the introduced below regulator R and the variation of the positive supply voltage for the threshold value stages S2 and S3.

p0022The described control principle has, however, extremely easily proven circuitry manageable. In the preferred embodiment, therefore, the sum signal of the output voltages of the converter U2 and U3 to the regulator R supplied with integral behavior, the S3 so varies the supply voltage of the threshold stages S2 and that the sum signal of the output voltages of the converter U2 and U3 is corrected. This, in its adjusted state signal<o>U</o> corresponds in size to the pulse-pause ratio U_PBM1,

p0023Since the embodiment, the negative impulses towards the positive momentum in the signal U_A2 would have to be wide, consequently the positive supply voltage P would be increased (or the negative supply voltage would be lowered).

p0024For the sake of a Schutzres ​​the threshold levels against over- or under-voltages, the output of the regulator R might be required, limited.