Self-routing multipath switching network for switching cells in the asynchronous transfer mode.

The present invention relates to a multipath switching network and self-routing for switching asynchronous time multiplexing cells.

A switching network, in its broadest definition structural comprises input ports to which are connected the input links, output ports of which are connected output links, elementary switch arranged between input ports and these output ports, arranged in one or more stages and interconnected by links. The input ports of the switching network are associated with the elementary switch inputs of a first stage, while the output ports are associated with the elementary switch outputs of a last stage. The outputs of the switching elements of said first stage are coupled by links, possibly through intermediate stages of switching elements, to the inputs of the switching elements of said final stage. The meshes, in general, comprise one or more independent linkages, each connecting an output of a switch to an input of a further switch, or the same.

Such a switching network is said multipath when offering over a switching path between an input port and any output port. In this case, the designation of an input port and an output port is not sufficient to determine a path from one to another. There is still a choice to be made between multipath offered by the switching network between this input and this output port.

Such a network is still said self-routing, in the broad sense of the term, such as when determining a switching path is, in the switching network, not only with information routing contains the implicit or explicit designation of an input port and that of an output port of the switching network, but also a clean routing decision to the switching network.

The self-routing option introduced in the switching network and provides an autonomous way to solve the routing problem with multipath networks when routing is only defined by the appointment of an input port and an output port.

multipath switching networks and self-routing connection are well known in the circuit switched and the switching of synchronous time division multiplex channels. The routing process or connection establishment is performed once at the beginning of a communication, and determines a switching path whose elements, initially free, then occupied by the communication, and therefore become unavailable to other communications. Established switching paths thus causing a risk of blocking by lack of roads in search of new switching path. The switching process applied in these known switching networks generally embraces the whole or a substantial part of the switching network. It is therefore complex and requires a period of relatively long time, in terms of order of elementary operations to establish the connection. By cons, this period is very short compared to the duration of the call and is not harmful, as regards the communication efficiency of the switching network.

Cells, also called packets are digital information units in particular comprising a label containing information for identifying the destination of the cell, as well as communication data.

The cells are either fixed length or variable length. In the latter case, the cell is transferred in the form of an uninterrupted sequence of a number of fixed length subcells of relatively small size, which allows to optimize the internal transfer, in memory storage or in the registers, and processing functions at the sub-cells.

In a system for transmitting asynchronous time multiplexing cells, cells of several communications transmitted on the same link, follow each other in any order, and cells relating to a same communication are transmitted at irregular intervals.

Given the characteristics of the transmission of asynchronous time-division multiplexed cells, a switching network of asynchronous time-division multiplexed cells is generally a switching network arranged for individually switching of such cells, such that a switching path is searched for each, for transporting it from a network input port to an output port at least. In this case, a switching network "self-routing cell" allows affectuer searched and a path selection for each individual cell. In addition, it is also commonly accepted that in this type of network, it is necessary to provide not only the traditional route, said point to point, an input port to an output port, but also at least routing said point to multipoint, between an input port and multiple output ports.

However, a prior connection establishment process, such as the one we just mentioned for network switching circuits or synchronous time division multiplex channels if it is in principle also applicable to the switching cells asynchronous time multiplexing, however, has a number of disadvantages, such as the complexity of managing the flows of connections established on each internal cell of the network and an excessive time for establishing data connections.

The multipath switching networks and self-routing by connection known in the circuit switched and the switching of synchronous time-division multiplex channels are therefore not an optimal solution for switching asynchronous time multiplexing cells. The technique is therefore turned toward specific switching networks in which the switching process including the path search takes place stage by stage for each individual cell, and therefore without prior establishment marking connection at the beginning of the communication.

the description is given of an example of such switching network in the article "Design of a Broadcast Packet Network" of JS Turner, published in the "Proceedings of IEEE INFOCOM'86" Fifth Annual Conference, "Computers Design and Communications Integration, Analysis, Management ", pages 668-673.

Such a network comprises input ports to output ports, floors specialized in the multiplication of cells necessary for the point to multipoint communications, floors specialized in the mixing of cells, for mixing cells from different inputs and get average flows in equal and stable mesh, as it is statistically possible, and floors specialize in selective routing to the output ports. This network is constructed using switching elements with two inputs and two outputs only. A small buffer for both cells is provided for each entry of the switching element. When a cell has to borrow an outlet is not available, because another cell is then retransmitted on that output, the input can temporarily hold non broadcast cell.

Such a network has drawbacks and limitations such as including:<ul><li>a large number of stages when the number of input and output ports is high,</li><li>limited effectiveness in retention cells to the inputs on busy outings,</li><li>some difficulty in achieving extensions, among others due to the large number of stages,</li><li>the existence of stories multiplication of cells, causing an additional cost,</li><li>a certain sensitivity to the arrival process of the cells on each input port, which is not completely controlled by the use of levels of mixing and thereby affecting the performance of the switching network, etc.</li></ul>

The present invention relates to a cell switching network asynchronous time division multiplexing self-routing cell not suffering, or at least not with that in a much smaller extent, disadvantages and limitations mentioned above.

The switching network of the present invention is characterized in that:<ul><li>each switch of at least one stage of the network has at least three outputs,</li><li>these outputs are arranged in groups called routing output groups,</li><li>an outlet group includes one or more specific outputs,</li><li>in routing information associated with a function of cell fixed or variable length received on one of its inputs, the switch is arranged to identify a set comprising one or more of said groups of outputs, a copy of the cell being transferred to each of the identified groups of outputs,</li><li>the switch is arranged to transfer said received cell, a selected one of the outputs of one group said assembly, or output, by a group of said set, each selected from the outputs of the group to which it belongs.</li></ul>

This network is composed, in one of his stories at least, elementary switches that, by thus determined output groups, between which each time an output is selected, provide not only a selective routing, but also bring a brewing cell division thereof on the various outputs of a routing group. In addition, possible routing on an output of each of several groups performs the multiplication of cells required in the case of point to multipoint routing. Thus, as will appear below, such a switch is suitable for the production of integrated switching networks in which the specialization of parts of the switching network disappears. Over the switch unit includes outputs per group, realize better brewing, because the greater the number of paths available to a cell, which also tends to reduce blocking by lack of available output, or increase the effectiveness of routing of the switching element and therefore of the entire switching network. Similarly, the switching element is then less sensitive to the arrival process of the cells, since the same input cells are carried by a plurality of different paths on each floor.

In a switching network to multiple floors, it may be provided that the switching elements of at least two stages possess these characteristics; the outputs of the arrangement in groups is not necessarily the same, so in each of these at least two stages and the switches of each of these stages are arranged to hold each of the own routing parameters derived from a given position.

Such arrangements will take into account the respective location of the switching elements in the switching network, in the arrangement of their group outings and particularly the fact that the mesh between pairs of successive stages is not necessarily the same.

According to another characteristic of the invention, said routing information is interpreted in each stage to determine the transfer mode of a received cell to the outlets of the switching element, and said interpretation is carried out in accordance with said derived paramètresd'acheminement its position.

These provisions allow to use the same type of switch in the various stages of a switching network and using a single set of routing information in a cell and still get the different cell transfer modes the various stages of the switching network, which provides great flexibility in the use of different delivery methods to transfer a cell through the switching network according to variate sequences transfer possible.

In a particularly advantageous embodiment, the switches in some stages of the network include at least means for interpreting routing information contained in a routing tag of a cell, which include a routing control code (RCC) defining the transfer sequence required for the cell, an output port address (RCA), for a point to point routing, and / or an internal reference number of distribution shaft (IRN) for a point to multipoint routing.

Contemplated switches, interpreting said routing control code based on said routing parameters derived from its position, are provided to implement accordingly a mail mode which may be, among others, a point to point routing or a point to multipoint routing.

The invention includes the case where the switching elements of all the stages are symmetrical, having the same number of inputs and outputs, and wherein the switching network is consequently also symmetrical, having the same number of input ports and output ports.

According to another characteristic of the invention, the switching elements of at least one stage may be asymmetrical and each carry a traffic entering expansion, reducing the cell traffic load on the outputs of these switches with respect to their inputs.

Such arrangements reduce the output load switches and therefore the retention of cells or loss in the switching elements, and the corresponding needs buffered in the switching elements.

Conversely, the switching elements of at least one stage may be asymmetrical and realize each concentration of the outgoing traffic by increasing the cell traffic load on the outputs of these switches with respect to their inputs.

Each of these two types of use of asymmetrical switching elements in at least one stage allows for asymmetrical switching networks, that is to say whose ports numbers entréeet output ports are different in the first case to ventilate the traffic on a greater number of output ports and in the second case to concentrate the traffic on a smaller number of output ports.

In addition, the combined use of asymmetric floors, but of different meanings within the same switching network is also possible. In particular, it is even possible to provide a symmetrical switching network having the same number of input and output ports, wherein one of the first stages at least is asymmetrical and directs expansion of traffic and one of the last story at least is asymmetrical and achieves a concentration of traffic compensates the prior expansion. Is then obtained between the two floors asymmetric reduction of traffic load internal mesh switching réseai with the advantages mentioned above.

The invention also relates to a switching network wherein the switches of some stages to carry less of cells belonging to two opposing traffic streams, and wherein in each of said bidirectional switches these switches, the inputs are divided into two sets of inputs and outputs of two sets of outputs, one traffic stream normally being routed from a first set of inputs to a first set of outlets and the other traffic stream from a second set of inputs a second set of outputs; the interpretation of the routing data in lé switch unit also takes into account all entries to which they belong to determine whether the delivery is to be "normal", that is to say to all outputs partner (same traffic stream) or "thought", that is to say to the other set of outputs (opposite traffic stream).

The invention also extends, however, if the switching elements of all stages of the switching network are unidirectional, routing cells belonging to a single traffic stream routed from each of inputs of these switching elements to their outlets.

According to one embodiment of the invention, the switching network comprises three stages at least unidirectional, each switch of one stage, except the last being connected by one or more meshes to each the following stage switch and each switch a stage, except the first, being connected by one or more meshes to each switch of the previous stage.

According to another embodiment of the invention, the switching network comprises at least one input selecting unit and at least one outlet selection unit, each formed of switching elements arranged in at least two stages and in each of which each switch of one stage, except the last is connected by one or more meshes to each switch of the following stage and each stage of a switch, except the first, is connected by one or more meshes to each switch of preceding stage, the inlet selection units being disposed in tandem with the outlet selection units, the input ports being connected to the inputs of the input selection units and the output ports to the selection units outputs Release.

In this latter embodiment, a single input selection unit can be connected directly to a single output selection unit, by brewing between the outputs of the first and second entries.

In the case of several units of selection of input and output, according to the invention, the switching network can further include selection units called selection planes connecting each of the input selection unit outputs to Release selection unit inputs.

According to another characteristic of the invention, in the switching elements of at least one stage, one of said groups of outputs of a switching element includes all outputs of the switching element, in the case of a unidirectional switch, or well all outputs of one of the two sets of outputs, pc a given transfer direction, in the case of a bidirectional switch, for general distribution of incoming traffic on all outputs of the switching element in the direction of incoming transfer ..

According to another embodiment of the invention, the switching network is configured extensible folded network, having at least two stages of which at least one is bi-directional, the input ports being connected to the inputs of said first set of inputs of the switching elements of a first stage and the output ports being connected to outputs of said second set of outlets of these same switching elements of the first stage, when it is bidirectional, the last stage being composed of unidirectional switches that carry a stream of incoming traffic to the switches of the previous stage, thereby achieving a traffic reflection.

When the first stage is not composed of bidirectional switches but two homologous sets of unidirectional switches (one for each direction of transfer), the input ports are connected to the inputs of incoming switches and output ports to the outputs of outgoing switches.

According to this latter embodiment, the folded switching network comprises at least two stages of which at least is birectionnel and each of a floor switch, except the last is connected by one or more meshes to each switch of the following stage and each stage of a switch, except the first, is connected by one or more meshes to each switch of the previous stage.

According to an alternative of this latter embodiment, the folded switching network comprises three stages and at least the first two stages consist of at least input selector and output units each formed from switching elements arranged in two-storey less and in each of which each of a floor switch, except the last is connected by one or more meshes to each switch of the following stage and each stage of a switch, except the first, is connected by one or more meshes each switch of the previous stage.

In the latter case to realize large capacity switching networks that are extensible in number of stages, said input and output selection units may be interconnected by a number of selection units called selection planes folded each comprising an arrangement of one or more stages to the required capacity.

These different types of folded switching networks have at least one bidirectional floor have the advantageous property of being extensible by number of stages, depending on the required capacity in number of network ports, without requiring cabling changes interstage . Indeed, any bidirectional stage may temporarily be the top floor equipped with an intermediate configuration through its ownership possible reflection of the traffic of the incoming transfer direction to the outgoing transfer direction.

In recent embodiments contemplated, preferably the or the first stages of the switching network perform general distribution of incoming traffic on all possible paths, that is to say on all sts, between these first stages , thereby providing a mixing of cells received on the input ports on a plurality of paths. In a unidirectional switching element of such a floor, the single routing group therefore includes all the outputs of the switch; in a bidirectional switching element of such a floor, all the outputs in the incoming transfer direction is the single routing group through which the incoming traffic is distributed. To achieve such a patch incoming traffic, according to the invention, each cell must be able to choose any of the available outputs in such distribution routing group.

Then, preferably, the switching elements of one or more of the first stages of the switching network are arranged so that, when the routing data specifies a point-to- point transfer and / or transfer of point to multipoint and taking into account said given position, there is method to the overall distribution of traffic entering or first floors.

Advantageously, the selection of one of the outputs of a group is done to balance the load cells on the various outputs of this group.

Advantageously, said selection being made so as to distribute the load cells on the various outputs of a group is based on a distribution process quasi or pseudo-randomly to a de-correlation between cell flow on the inputs and flus cells on the outputs of the switching element.

Almost or pseudo-random distribution occurs when selecting an output from the various outlets belonging to the selected routing group. This mechanism can intervene prior to registration cell identities in queues which are then assigned to individual outputs. In addition, the two mechanisms described above, load balancing and random distribution, can be advantageously combined.

multipath switching networks and self-routing according to the invention also have the following characteristics:<ul><li>The combined use of a plurality of paths for transferring the different cells of a call to the one or more output ports concerned and of the switching elements effecting a storage cell during an undetermined time, has the consequence of feeding these cells or to the output ports with a time of variable transfer may change the order of successive cells. This feature involves the introduction of order cell recovery circuits at each output port of the switching network.</li><li>Stirring the incoming traffic of the cells on a plurality of possible paths in the first stages of distribution provides the characteristic property that the flow of internal links of such switching networks is no longer conditioned by the speed of the external transmission links as are connected, or even by the flow of services provided on these external links. Indeed, the principle of distribution of a multiplicity of paths within the network serves to distribute the flow of cells entering an external link high rate on multiple input ports of the lower-speed switching network; for example, an external link to 2.4 Gbit / s can be connected to 16 input ports 150 Mbit / s. After transfer of the cells in the switching network on the set of possible paths, the cells for an outgoing external connection to the same 2.4 Gbit / s rate are routed to a group of 16 output ports 150 Mbit / s where does the restoration of order and the asynchronous cells muultiplexage on the outgoing link to 2.4 Gbit / s.</li></ul>

Similar reasoning shows that a service that would require a cell rate equal to 200 Mbit / s can be transferred in the switching network over a multiplicity of paths, each corresponding to an internal link 150 Mbit / s<ul><li>Brewing incoming traffic in the early stages of distribution also results characteristic to achieve an averaging of the burden of external links on switches internal stages of the switching network. It is then possible, for example, to equip a variable number of selection plans based on the average traffic load on all the external links of the unity of the busiest traffic selection.</li><li>Regarding point to multipoint transfers according to predetermined broadcast tree, the plurality of possible paths to transfer a cell through the comutation network multipath and self-routing requires a characteristic organization of memory contents of distribution tree of the switching elements of the different stages. According to the invention, it is possible to define the corresponding branch points so that no unnecessary copy is generated at any stage, preventing any internal overload of internal links between floors.</li></ul>

The various objects and features of the invention will be discussed in more detail in the course of the following description of an exemplary embodiment of the invention, given without limitation, with reference to the accompanying figures:<ul><li>Figure 1, the known circuit diagram of an exemplary switching element ISE used in the switching network of the present invention,</li><li>Figure 2, the format of a cell provided for the implementation of the present invention,</li><li>Figure 3, a diagram of a mode of application of the switch of Figure 1, for routing cells in opposite direction </li><li>3a the figure, the detailed diagram of sub-cells of the memory management logic SBML of Figure 1,</li><li>Figure 4, the diagram of the steering circuit RL according to the invention, applicable in the switching element of Figure l, for using it in accordance with Figure 3,</li><li>4a the figure, the detailed diagram of cells from the business logic and output selection COQML of Figure 1,</li><li>Figure 5, a symmetrical unidirectional switching network according to the present invention,</li><li>Figure 6, a unidirectional switching network symmetrical four-stage arranged in two selector units back to back, each having two floors,</li><li>Figure 7, a folded symmetrical switching network corresponding to that of Figure 6,</li><li>Figure 8, a unidirectional switched network asymmetric dual three storeys,</li><li>Figure 9, a bidirectional switching network ASYMMETRIC to three stages corresponding to the preceding,</li><li>Figure 10, a bidirectional switching network asymmetrical several selection units in two stages,</li><li>Figure 11, a unidirectional switching network symmetrical several selection units two-stage interconnected by several selection planes to three floors.</li><li>Figure 12, a folded symmetrical switching network corresponding to that of Figure 11.</li></ul>

In these figures, for simplicity, various connections are represented as mere son, although they can incorporate a plurality of such son. Furthermore, the figures do not rerésentent all control circuits, resulting realization obviously for the art, the content of the description.

The switch unit shown in Figure 1 with X inputs I1 / IX and Y outputs O1 / OY (X and Y are not simultaneously equal to 1) is arranged to commutater digital signals grouped in cells or packets of fixed or variable lengths . Such a cell, shown in Figure 2, is not constituted by such a series of successive subcells comprising a first subcell FSC, an intermediate in a final cell ISCet subcell LSC, all of equal length, example of 162 bits or 2 bits and 20 8-bit characters. Each of these subcells contains a subcell control field SCH (2 bits) and a data block DB1 - DBS, the first FSC subcell further containing a CCH cell label which, for example, contains routing information for the switch unit to determine at what (s) group (s) outputs RG1 / RGY all successive sub-cells of the same cell must be successively transferred, the transfer is effected on the same or the same outputs. In this description, the sub-cell control field SCH is assumed to have an explicit binary value 11, 00 or 01 indicating that the subcell is respectively the first FSC sub-cell, an intermediate subcell ISC or the last cell LSC sub-cell.

The CCH label itself comprises three parts, a routing control field RCC, an indication of destination as a network RCA output address and an internal reference number IRN broadcast tree.

The command field RCC, which may comprise 5 bits, contains a routing mode data designating a mode of transport point to point or broadcast mode of transportation, or any other manner provided, some of which will be explained far. If for a switch, the CCB control field denotes the point to point routing mode, analysis of network output address RCA provides the identity of the selected group of outputs. If the RCC control field denotes the dissemination of routing mode, the multicast tree reference number IRN is used to read a memory that provides the identities of the groups of outputs corresponding to the connection to be made to this tree in the switch unit .

The RCA output network address, which will include up to 14 bits, for example, is the identity of the output port of the switching network (or group of output ports) which must be sent the received cell . When selective routing is performed by more than one stage of the switching network, only a part of the destination data is needed in each of the switching elements for the routing of the cell.

The internal reference number IRN, which also include for example 14 bits, is a number used within the switching network to identify the multicast tree that an incoming cell is to be transferred to a number of output ports provided. It is interesting to note that, according to the invention, a multicast tree in a network self-routing and multipath is not a point to multipoint connection because, being independent of the input port, it is characterized only by all the destination output ports; Furthermore, in such a network with multiple paths, it corresponds to a multiplicity of paths point multipoint potential between all ports of entry and all the destination output ports of the broadcast tree considered. In fact, a given IRN multicast tree is not necessarily specific to a single communication, but can be used by all communications from any input ports need to transfer each cell to the set of output ports recipients of the multicast tree.

3 shows now, for editorial reasons of convenience, a method of use of the switching element ISE in Figure 1 in the case of the bidirectional routing, with the possibility of reflection, which will be explained later by referring figures 7, 9, 10 and 12.

The switching element ISE, in the example, has 32 inputs I1 to 132 and 32 outputs O1 to O32. Inputs I1 to I32 are divided into two sets of inputs I1 to I16 and I17 to 132. The outputs are divided into two sets of outputs O1 to O16 and O17 to O32. Internally, except in the case of reflection, the switching element is arranged to allow the normal routing from left to right, the inputs I1 to I16 to the outputs O1 to O16 and at the same time but from right to left because the external wiring mode, I17 to I32 inputs to outputs O17 to O32. In case of reflection, the switch allows routing of inputs I1 to I16 to outlets O17 to O32, I17 or I32 inputs to the outputs O1 to O16. In such a switch, the assignment of inputs to routing directions is predetermined. It may be indicated by an IO bit attached to each entry and indicates whether it belongs to a sense "incoming" (I1 to I16, for example, routing traffic normally intended for all outputs O1 to O16) or sense "outgoing" opposite (I17 to I32, using the same example, routing traffic normally intended for all outputs O17 to O32).

All 16 outputs each direction may be eg divided into 8 groups in addition to at least two outputs and routing any cell on the outputs of one of the groups simply request the identification by a word 8 bits (one bit per group) or groups to which the cell must be sent, provided that the cell is transmitted on a single output of each group so identified.

Referring to Figure 1, the inputs I1 / IX of the switching element represented there are connected to respective data inputs of a multiplexer MX circuit via the cascade connection of converter circuits respective series-parallel SPR1 / SPRX and respective latches IL1 / ILX. The output of IF data multiplexer MX is coupled to the data input, also CI, sub-cell buffer memory BM, of the RAM type, whereas the selection input XI of the multiplexer MX is controlled by a input clock circuit XC able to successively connect each of the X multiplexer inputs to the multiplexer output CI during a subcell period. Such a period of sub-cell is the time interval during which a sub-cell is received in a series-parallel converter circuit SPR1 / SPRX.

The buffer memory BM is fully shared and its data output is connected to the data input of a demultiplexer DX whose Y data outputs are coupled to respective outputs O1 / OY via parallel-serial converter circuits respective PSR1 / PSRY. The selection input YJ demultiplexer DX is controlled by a YC output clock circuit capable of connecting successively entering the demultiplexer to the Y demultiplexer outputs during a subcell period.

It should be noted that for subcells having a length of 162 bits and for a same bitrate of 50 Mbit / s at the inputs and outputs, one subcell period is equal to:    162 / 5O = 3.24 microseconds.

Specifically, when, for exeple, the switching element has X = Y = 32 inputs and 32 outputs, 32 registration operations and 32 read operations, 64 operations must be performed in the buffer memory BM during the same period subcell 3.24 microseconds. As a result, each of these operations must be carried out:    3.24 / 64 = 50.62 ns.

Furthermore, when for example X = 16 and Y = 32, 48 operations have to be performed during the same subcell period. This means that each of these operatons must be carried out:    3.24 / 48 = 67.50 ns.

WB buffer is divided into C, 512 for example, buffer locations of sub-cell, each capable of recording a sub-cell, eg 162 bits; it has an address input AC as well as a selection inputting read / write RW repectivement coupled to the outputs of the same names of SBML subcells buffer management logic.

The switching element further includes a subcell logic SL and a routing logic RL which are both coupled to the CI data output of the multiplexer MX.

The logic SL sub-cell is mainly a detector designed to detect and verify the sub-cell control field SCH of each subcell and to provide output signals assets LS, FO or NF, as the sub-cell is respectively a last subcell LSC, a first subcell FSC or not a first subcell.

The routing logic RL performs the analysis of the cell label routing information CCH of each first subcell FSC of a cell and provides active output signals RMD and RC, depending on the 'routing information. More particularly, the RMD signal provides the identity of one or more output groups selected on which the sub-cells of the cell to be transferred, whilst the signal RC indicates the number of these selected outputs of groups is -to say 1 for a point to point transfer and a value greater than 1 for a transfer point to multipoint. The type of routing information and the corresponding analysis process performed by the routing logic RL to generate the RMD and RC output signals depends on the employee routing mode for the cell. The CCH cell label may, for example, contain Y bits of routing information, each bit corresponding to a group of outputs to which the cell to be transferred.

The outputs of cell queue management logic performs both, management of queues of cells and output selection functions, registering the first address WISA input subcell in an appropriate queue BQ1 / BQZ, depending on the mode of transport and RMD data provided by RL logic and transmitting the address of the first output sub-cell FSAO the SBML logic, at the same time the identity of the selected output YS.

SBML the sub-cell buffer management logic is coupled to the previously mentioned outputs LS, NF of the logic SL, RL RC logic XI of XC input clock circuit, FSAO the business logic COQML cells, and YJ YC output clock circuit. It manages the use of the BM memory buffer locations, providing the address of free slots, making them busy and when used in the frees them when they are no more. Under the control signals applied to its inputs, it also controls, via the read selection signal / RW writing, read operations and enrollment in the buffer memory BM, while constituting linked lists chaining the buffer address subcells of a same cell. This is necessary, because the sub-cells of the same cell is stored in uncorrelated locations of the buffer memory BM, then they must be sent on the same one or more selected outputs O1 / OY and in that Similarly, uninterrupted than they were when they arrived on one of the inputs I1 / IX.

We will now briefly describe the operation of the considered elementary switch. When a subcell of a cell of variable length, such as that shown in Figure 2, appears on one of the inputs I1 / IX, for example I1, of the switching element, it is received by the circuit serial to parallel converter corresponding SPR1. SPR1 provided by the converter circuit, the parallel version of the subcell is transferred to the latch circuit corresponding IL1 by which it is provided to the multiplexer MX. XI under the control of the clock signal supplied to the same input name with the XC input clock circuit, the sub-cell is, at some point, for that entry I1, supplied to the input CI data of the buffer memory BM, and the logic SL sub-cell and routing logic RL. It is then determined whether the subcell is a first subcell FSC, LSC last sub-cell, or is not a first subcell and for what group or groups of outlets RG1 / RGY this sub-cell - and the following subcells belonging to the same cell - have to be transferred respectively. The output signals resulting LS, NF and RC are applied to the logical buffer memory management of SBML subcells RMD and the output signal to the queue management logic output cells COQML expectations.

Under the control of the clock signal XI, logic SBML provides the address of a free buffer memory location, WISA for example, the input AC address of the buffer memory BM, whereby the sub -cell present at the CI input data WB buffer is stored in the location thereof having the address WISA. This address WISA is rendered busy and is added to the linked list of addresses of all the sub-cells already received the same cell (in this case the NF signals LS, CR and RMD are used). In this list, the addresses are arranged in the same order as the subcells of the cell.

During a read operation, under the control of the clock signal Yj is supplied on the entry of the same name by the output clock circuit YC, the address of a subcell, ROSA for example, is supplied to the input of AC address of the buffer memory BM and the subcell contained in the corresponding memory location is read and transferred to the data output of the buffer memory BM. From there it is supplied via the demultiplexer DX to the outlet or one of the outputs initially indicated by the YS signal COQML management logic.

Referring now to Figure 3a, which represents the SBML subcells buffer management logic of Figure 1 in more detail.

As already mentioned, this memory management sub-LD INST cell buffer has inputs LS, NC, RC, XI, YJ, FSAO, YS, and AC outputs, L, RW and FSAI. It includes a circuit management of free memory locations FMLMC, a chaining memory sub-cells, memory cells incoming sub-pointers MIPS and memory sub-cells OSPM outgoing pointers.

The FMLMC SBML logic circuit consists of a queue memory FQ free slots is such a memory FIFO queue (first in - first out) recording the addresses of all locations free to the buffer memory BM. The circuit has a FMLMC ROSA entrance, WISA output and control terminals QC and RW.

The sub-cell linking memory SLM includes C memory locations corresponding to the C buffer locations of the sub-cell buffer WB and records for each of them:<ul><li>the chaining address the following sub-cell (NCB)</li><li>the number of sub-cell copies to be read (NC),</li><li>a last subcell of cell indicator (L).</li></ul>

The SLM memory field is associated with a retrograde DC meter, so that the NC value is decremented by one each SLM memory read operation; then the new value is stored in place of the previous one. Of course, when the new value reaches zero, all subcell copies have been read and the DC counter generates a signal QC for recording the address of the read sub-cell (ROSA), which is free, the location management circuit FMLMC free buffer.

The memory of incoming subcells pointers ISPM X slots corresponding to the X input and it operates in synchronism with the XI input clock signals defining the operation time division multiplexed X entries. For each entry, it records:<ul><li>the buffer memory address of the last received sub-cell (LCB)</li><li>the number of copies of sub-cell that will read later (LC)</li><li>a last subcell of cell indicator (B).</li></ul>

Memory outgoing subcells pointers OSPM has Y locations corresponding to the Y, which operates in synchronism with the output clock signal YJ defining the operation time division multiplexed Y outputs. For each entry, it records the location address in the following sub-cell waiting to be transmitted to the output in question (WCB).

The write control circuit provides various circuits appropriate control signals corresponding to the alternating operation of SBML circuits associated with alternating read and write operations in the buffer memory BM, therefore interleaved clock signals for the entries (XI) and to the outputs (YJ). In line with this, the result is RW active signal during each write operation in the buffer memory BM, for the entry of a sub-cell and inactive during the buffer memory BM read operation for transmission in Release a subcell.

The next principle description characterizes the operation done by these functions SBML management logic during a read or write phase for each of the three types of sub-cells of a cell: first FSC sub-cell sub- intermediate cell ISC and LSC last sub-cell.

First we will consider the writing phase in the buffer memory BM, in the case of a first subcell FSC. In such cases, the FO signal is provided and the SBML management logic receives SL and RL logic:<ul><li>NC = O, indicating a first sub-cell,</li><li>LS = O, indicating that it is not a final sub-cell,</li><li>RC = 2, assuming for example the case of a point-to- multipoint transfer on two groups of outputs.</li></ul>

The RW signal is active, a sub-cell write address WISA is provided by the FMLMC management circuit, which is free space buffer selected that stores the received sub-cell. The address WISA is also stored in the pointer memory ISPM for the entry XI to save as the last address received sub-cell in the next cycle on the same input. Furthermore, the address WISA is also provided to the logic COQML which the record as a reference identity of this new cell received, the fact that this logic receives the FO signal value 1.

Regarding the chaining memory SLM, because it is a first subcell FSC (NF = 0), the address WISA is not recorded in the NCB field, since this new sub -celule does not need to be chained with the last of the previous cell. In addition, other data fields are operated for the previous sub-cell by selecting the address provided by the LCB field of the pointer memory ISPM and saving LC and B from the ISPM pointer memory in the NC field and L of the memory SLM respectively. PC and LS control signals are respectively recorded in the LC and B fields of the ISPM memory to the input XI.

In the case of a sub-cell through the FO signal is inactive and the buffer memory management logic SBML sub-cells receives SL and RL logical signals:<ul><li>NF = 1,</li><li>LS = O,</li><li>the signal RC is not used with NF = 1.</li></ul>

As before, the signal RW is active and another address WISA is provided by the FMLMC management circuit, buffer address location that is used to:<ul><li>address the buffer memory BM and write the intermediate subcell ISC,</li><li>be registered in the LCB field of the pointer memory ISPM new address as of last sub-cell received from the cell,</li><li>be registered in the NCB field of the SLM memory addressed by the contents of the LCB field of the ISPM memory, in order to register this new address WISA is the address of the next sub-chained with the previous cell that is actually the memory location selected in the SLM memory.</li></ul>

Simultaneously, data from LC and B fields in the memory ISPM are transferred into fields NC and L of the memory SLM, before B is replaced in the ISPM memory with a new value from the LS signal.

In the case of a last subcell LSC, the TF signal is inactive and the SBML management logic receives logic SL and RL:<ul><li>NF = 1,</li><li>LS = 1,</li><li>when RC is not used since NF = 1.</li></ul>

Again the signal RW is active and another address WISA estfournie by FMLMC circuit, and the site address corresponding buffer is uslisé in the buffer memory BM, and memory ISPM and SLM exactly as in the previous case recording an intermediate subcell ISC.

Simultaneously, the LC and B values ​​of the ISPM memory are transferred to the NC fields and L of SLMN memory before B is replaced, in the ISPM memory with the new value from the LS signal, thus indicating that now the last subcell of a cell has just been received.

However, as it was pointed out in the description on the registration of a first subcell FSC, during the next cycle on the input XI, LC and B values ​​= 1 will be transferred to the NC and fields the memory of the SLM at the previous cell (the last) provided by the LCB field of the ISPM memory.

Now we will consider the WB buffer memory read phase during which the signal RW is inactive. Initially, we will consider the particular case of reading a first subcell FSC.

It must be assumed that, when issuing the first sub-cell, the WCB memory content of outgoing subcell pointer OSPM the output considered YS is initialized with the address of the first sub-cell the cell to be transmitted. Will become apparent later, during the playback of the last cell of the sub-cell.

The pointer memory OSPM provides a result the address of the outgoing sub-cell to be read that is used to:<ul><li>contact WB buffer for reading the first FSC corresponding sub-cell,</li><li>select the SLM memory read, which provided:<ul><li>an indication NCB which is transferred to the OSPM for provisional registration as a new WBC address in the next cycle on the output YJ,</li><li>an indication NC which is decremented by one and re-registered as a new indication NC, if it is not void; if zero is reached, meaning that the required number of read operations of this sub-cell (providing the required number of copies thereof) has been performed, the DC circuit generates a signal QC allows the system FMLMC save the memory location ROSA address buffer can be released and included in all free buffer emplacementsde;</li><li>The value which is zero since it is not the last cell and controls the transfer of the previously mentioned NCB value of the SLM memory WCB field of OSPM memory via the multiplexer SO.</li></ul></li></ul>

In the case of an SAI intermediate cell, the same operations take place in the memories OSPM and SLM and the FMLMC circuitry for reading a first subcell FSC.

In the case of a last subcell LSC, the OSPM memory again provides the address of the ROSA sub-cell to be transmitted, a last subcell LSC in this case, which is used for:<ul><li>contact WB buffer for reading the last sub-celule,</li><li>select the SLM memory read, which provides:<ul><li>a NC value is decremented and treated exactly as in other cases of sub-cell reading,</li><li>an L, now equal to 1, indicating that one is in the presence of a final LSC sub-cell, which in this case articulier, prohibits the transfer of NCB value of the SLM memory location WCB OSPM of memory, since there is no chaining to a next subcell not provide the NCB value of the SLM memory in the case of a last subcell LSC; instead, L = 1 is supplied to the logic COQML to indicate that the outlet in question YZ becomes available for the transmission of a next cell in the next cycle, a last subcell of a cell is being consignment.</li></ul></li></ul>

Then, after selection by the logic COQML of the appropriate cell to be transmitted on the considered output YJ, the WBC COQML logic initializes the value in the memory for OSPM regards YJ output in slot address inscribing there memory buffer FSAO the first sub-cell of the newly selected cell, before the next cycle on the output YJ. Because this initialization process is not carried out during the clock period YJ of the last subcell LSC, asynchronous access to the OSPM memory is used, by means of the output address provided YS by COQML logic.

While this embodiment of the SBML subcells buffer management logic has been described to illustrate the principles of the management of the sub-cell buffer used for the transfer of cells composed of sub-cells between any input and any output or outputs of the switching element, other embodiments of the functions of this SBML management logic, for example as regards the management circuit FMLMC of free buffer locations, are also included in the types of switching elements in accordance with the present invention.

4 shows an embodiment of RL routing circuit arranged for use in the switching element ISE of Figure 1, and also for bidirectional operation in accordance with what is shown in Figure 3.

The circuits of FIG 4 receive, a register IR, CCH cell label mentioned in Figure 1, for outputting information marking the RMD control link that provides cell management logic and selection output the information specifying the selected routing mode (aS, MC, DI, ES, PH), and routing data (RG, PO)

routing mode information are:<ul><li>a mode signal "group" RS, which is present when the cell is to be broadcast on one of the outputs of a group of outputs in case of delivery of point to point,</li><li>a mode signal "spreading" MC, which is present when the cell is to be routed to one of the outputs of each of several groups of outputs in case of multi-point routing,</li><li>a mode signal "distribution" DI, which is present when the cell should be sent on one of the outputs of a set of outputs, in the sense explained with reference to Figure 3, in the case of a switching element bidirectional, or one of all outputs of the switching element, in the case of a unidirectional switching element, realizing thereby a general distribution to a mixing of the cells received by the switching network,</li><li>a signal mode "service" ES, indicating that the received cell is intended for a particular output control,</li><li>a mode signal "directed transfer" PH, which indicates that the cell should be sent on a predetermined output, for testing purposes, for example.</li></ul>

The routing data RMD bond include:<ul><li>GL group identity signals identifying the group or groups on an output of which is to be retransmitted or the received packet to the RS and MC routing modes,</li><li>PO individual identity output signals used with PH mode of transport.</li></ul>

The circuit of Figure 4 also receive, according to the input that has reached a received cell, an incoming direction indicator IO which is for example provided by the receiving circuit providing the cell in question, on the multiplexer input of Figure 1, specifying the relevant incoming direction, the direction mentioned with reference to Figure 3.

The circuit of Figure 4 include the following:<ul><li>register IR earlier, to receive the label of each cell received CCH, which includes, as mentioned, the CCR information, RCA and IRN,</li><li>a command translation memory RCCTM, recording 32 words of 16 bits, called routing parameters, each including routing mode code MT three bits, indicator or reflection EF bit, a routing group field "incoming" RPI, 6 bits and a routing group field "outgoing" RPO, also at 6 bits,</li><li>a broadcast memory MCM, registering a plurality of mask words MSK 8 bits, one bit per group outings, each identifying the different routing groups to which a copy must be issued,</li><li>a routing mode decoder TD, decoding the routing mode code MT and providing accordingly one of the five mode signals mentioned above,</li><li>RD direction selector selecting either the routing group field "incoming" RPI or the scope of delivery "out" group RPO "RCCTM the control translation memory, depending on the EF bit of reflection and the incoming direction indicator IO,</li><li>MS output group selector with two 8-bit parallel inputs and provides the RG group identity signals, also 8 bits, each bit of which is a separate group from the 8 possible routing groups,</li><li>an SR 14 bit shift register having an output PO to five conductors; in the case where the routing mode is the "physical" fashion PH, this output identifies the output of which must be sent the received packet</li><li>GD routing group decoder,</li><li>an exclusive OR gate XOR,</li><li>and two gates, AN1 and AN2.</li></ul>

The routing logic circuits of Figure 4 operate as described below, when the header of a received cell is present on the input multiplexer (Figure 1), CCH label is included in the register IR, while IO bit indicates the incoming conveying direction. As noted above, a pace clock operation circuits, appropriately, in accordance with current practice in the field.

RCC control information, characteristic of a transfer sequence through the switching network does not directly indicate the routing mode to be applied for the relevant switching element. This routing mode depends on the type of switching network and the position of the switching element therein.

The control information, to be interpreted, is used as an address for reading, in order RCCTM translation memory, routing parameters including elements MT, EF, RPI and RPO defined above.

The routing mode code MT to apply is decoded by the TD routing mode decoder which therefore provides one RS-mode signals, MC, ES, DI or PH.

The IO incoming direction indicator is applied to one input of exclusive-OR gate XOR, while the reflection EF bit is applied to its other input. The output of the XOR port provides the control signal for the outgoing direction selector RD. It selects either the routing group field "incoming" RPI or the routing group field "Outgoing" RPO, specifying, for both sets of outputs, a specific part of the address RCA destination designed to provide the identity of a routing group to an output which is to be retransmitted the received cell. Each of these fields includes a position indicator POS and a 4-bit size indicator RGS two bits. The position indicator POS controls the shift register SR so that the RCA information will be shifted and some of it contains three bits come in three stages left in the figure, this register SR or that a part of five bits contained therein come in five stages left in the figure, the register SR. The size indicator RGS indicates how many of the three bits mentioned first shall be used to define the identity of a routing group. Thus, the left three bits bit being conveyed directly from the shift register SR GD group number decoder, the next bit is transmitted through the AND gate AN1 conditioned by RGS signals and the third bit by the AND gate AN2 conditioned by the other RGS signals. GD group number decoder provides an 8-bit word which constitutes the identity of a routing group, applied to the selector MS. In this word, a single bit is 1, for example, all the others being at O.

Simultaneously, the internal reference number of multicast tree to 14-bit IRN is applied by the IR register in the broadcast memory MCM, where he serves as an address for reading a mask word MSK 8 bits. As indicated above, this mask word identifies one or more routing groups in an 8-bit word, which one or more are at 1, and the other to 0. It is also applied to the selector MS.

If the mode signal provided by the decoder TD is the mode signal "group" RS, the MS provides its output selector RG group identity signal which is the signal from the decoder GD; if this is the mode signal "spreading" MC, the RG signal from the selector MS is the MSK signal.

Furthermore, the five stages of the left shift register SR after the offset caused by the position indicator POS, provide directly PO identity of an output at which is to be sent the received packet in the case of mode routing "physical" PH.

In the particular case of the mode "distribution" DI, any outlet group only needs to be identified, since this is one group comprising all the outputs of all considered in the direction of relevant transfer .

In the case of the mode "service" ES, the data output is directly known, since the received cell is intended a particular output controller depicted in Figure 1.

Thus we see that the information contained in the command translation memory RCCTM sets in each switching element, the interpretation that this switch must transfer the 32 possible sequences designated RCC control information for determining the operating routing to apply routing data in the label of the received cell. This involves combining the routing information of a cell, unchanged while the cell through the switches of different stages of the switching network, the routing switch parameters derived from its position in the network, for example clean on each floor and leading to a particular mode of transport in each stage and for each routing sequence.

The information in the control RCCMT translation memory are semi-permanent and can be included in the commissioning of each elementary switch. For cons, the information contained in the broadcast memory MCM must be changed during operation for the establishment of each multicast tree.

Figure 4a shows the general diagram of cell management logic and output selection COQML of Figure 1.

When the forwarding decision for a new cell received at an input of the switching element is taken by the steering circuit RL, it provides the logic COQML routing mode information, and the data of routing involved on RMD control the connection, this control being enabled by the control signal received FO SL circuit, which indicates the presence of a first subcell FSC containing information intended for the delivery of the current cell reception. Also, simultaneously, the logical memory management of SBML sub-cells provides the logic COQML WISA address of the buffer memory BM, which was recorded in the first subcell FSC.

When a YJ output of the switching element transmits the last subcell LSC of a cell and will therefore become available to transmit a following, SBML sub-cells of the memory management logic indicates a next cell application using the the signal then active, as explained earlier in the description of the SBML logic. So COQML logic selects the next cell to be transmitted on this output, providing the logical address SBML FSAO the first FSC sub-cell of the cell to transmit the output YJ, the latter indication being notified by the output address YS also provided by the logic COQML the SBML logic, to do this outside of the synchronous clock time on the YJ YJ output.

The cell management logic and COQML output selection includes the following circuits:<ul><li>Queues BQ1 / BQZ whose respective inputs are from a BI demultiplexer and the respective outputs are connected to a multiplexer BO, and realize that the temporary storage of the identities of cells awaiting output, respecting the first-discipline / first out, said identities being characterized for example by the addresses of the first sub-cell of each cell in the buffer memory,</li><li>QICL netrée a control logic receiving queuing requests waiting cells,</li><li>a logic output QOCL colmande which selects each next cell to transmit on one of the outputs of the switching element as soon as celule becomes available.</li></ul>

Besides managing the temporary holding cells to be transmitted, by sotockage their identities queues, logic COQML also ensures the selection of individual output in each selected routing group, given that state for modes point-to-point routing RS, point-to-multipoint ™, and distribution DI, LR routing system only identifies the routing groups to which a cell copy must be sent, or all output in one direction in the DI mode.

In a first embodiment, the function of individual selection outlet is conducted by the QICL input control logic prior to waiting on the identity of the cell line. In this case, each queue BQ1 / BQZ is directly associated with each of the outputs Y of the switching element.

Another form of equivalent embodiment is to perform the same output selection function by the output control logic QOCL, so after the setting of the queue for the identity of the cell line. In the latter case, each queue BQ1 / BQZ is associated with routing group comprising one or more outputs and not to an individual output of the switching element.

In either embodiment, the output selection device necessary for RS routing modes, TM and DI can be performed in known manner on the basis of a cyclic distribution of the cells to the outputs of a routing group considered, which allows a homogeneous distribution of the cell traffic load of the routing group on each of its outputs. Another proposed solution is to use a pseudo or quasi-random signal generator for selecting an output for each cell, which allows to eliminate, at least in large part, any correlation between the flow cell on the inputs and the outputs of each switching element.

In the case of ES or PH modes, an output of the switching element is respectively implied or already selected and the role of logic COQML is limited to the management function of these cells in queues by corresponding individual output.

Will now, by referring to Figures 5-12 provide several exemplary embodiments of the switching network of the invention, based on Figures 1 to 4, as regards the characteristics of the switching elements employed in the different floors of these switching networks.

Indeed, the properties of a switching network based on the properties of the switching elements that constitute it, as they are arranged, according to the invention by the semi-permanent routing parameters derived from the position of switches and configuring the switching network, comprising essentially the number of stages, the unidirectional or bidirectional characteristic of each stage, the mesh between the switching elements and the connection mode of the input and output ports.

The invention will be seen, is applicable in all the switching network configurations to be described, as well as in numerous variants which can be easily deduced.

It should also indicate that in all switching network configuration, it is generally desirable, for reasons of standardization and ease of extension, that the same type of elementary switch is used in all stages of the network. One can easily verify that the switching element of Figures 1, 3 and 4 satisfies this need through their ability to be initialized with specific routing parameters, for example by stage for each cell transfer sequence across the network of commutation.

5 shows a switching network RC1, unidirectional and symmetrical, consisting of switching elements such as that of Figure 1, arranged in three stages including the first to the TSi1 tsit switches, each having n inputs, the central stage , AS1 switches ASk, and the last of Tso1 TSOT switches each having n outputs. In this way, the switching network has N = nT input ports connected to the inputs of the switching elements of the first stage and M = nT output ports connected to the outputs of the switching elements of the last stage. The cell traffic is routed from input ports to output ports across all switches in one direction; that is why the network is said unidirectional. It is said to be symmetric, because the number of outputs is the same as that of the inputs. T switches the first floor have one or more (m) mesh to each of the k switches of the central stage, ie mxk outputs. T of the last stage switches have one or more (m) stitches from each of switches of the middle stage or mxk inputs. The switches of the central stage and have Txm Txm inputs and outputs.

Repeating the above figures (Figure 3, for example), the switching elements of the three stages can be switches to 32 inputs and 32 outputs, with Txm KXM = = 32.

Each of the switches of the central stage up to the top floor all the switches, a cell reaching the switching network on any port of entry, the TSi1 switch unit, for example, may be addressed to any of the switches of the central stage, AS1 ASk that the delivery of this cell type either point to point or point to multipoint. In such a network is therefore provide, according to the invention, the outputs of the first stage switches are arranged in one group outings and a cell received by a first stage switch that is routing point the point or point to multipoint, will be broadcast on a selected output in this unique group outings. Simply (described on Figure 4) that control translation memory (RCCTM) in the elementary switches TSi1 to tsit, provide the mode signal "distribution" DI in exchange for RCC control information indicating that the cell must be distributed to any output to the next stage, for delivery of point to point or point to multipoint.

In other words, position data included in the first stage switches (implicitly represented by the routing parameters in the control translation memory) allow an interpretation in this sense of the routing information cell.

By against, as regards the switches of the central stage, each of which has one or more (m) mesh to each switch of the last stage. The routing depends on the identity of the destination output. A group of one or more (m) mesh is available for this purpose. Each switch of the central stage will thus T groups of one or m outputs. With a data different position, these switches will perform the same routing information of the cells, so as to select the appropriate routing group, in the case of routing point-to-point, or the appropriate groups in the case of an interesting point to multipoint routing of the outputs of several different switching elements of the last stage. According to the embodiment of Figure 4, the control information RCC considered above will be translated in these switching elements of the central stage in a "group" mode signal RS, for a point to point routing, or an "MC" mode signal for a multi-point routing, while the RCA output address, or the internal reference number IRN will be used for identification of the selected output groups.

What applies to the switching elements of the central stage, with respect to routing cases considered, also applies to the last stage switches.

In the case where m = 2, for example, switches of the central stage has two stitches with each of the switches of the first and last stage. In this case, the switching elements of the central stage will T groups of two outputs between which it will be necessary to make a selection.

The number of switching elements of the central stage may, in another embodiment, be greater than that of the switches of the two end stages, other things being equal. This will reduce the traffic load of the internal links of the switching network. Starting again from the previous example (m = 2), the central stage could include 64 switching elements, and, correspondingly, the switches of the two extremes floors have 128 outputs or inputs.

Can also be considered that, for a given dimensionement network of Figure 5, the number of switching elements per stage and number of connections between them meshes, some transmission speed to input links greater than that practiced in the switching network is coupled to a plurality of input ports on which the cells of this outer link are distributed; these are then transferred individually by the plurality of possible paths to the output ports recipients. Generalizing, it can achieve a switching network whose transmission rate and switching would be less than that of the external transmission connections it serves. Of course, what you just said about the input links applies symmetrically to the output connections where cells of multiple output ports are multiplxées to the outgoing external connection.

The unidirectional symmetrical switching network of Figure 6 includes 4 floors. The designations of the switching elements of the two end stages are the same as in Figure 5. The switching elements of the two central stages are referred to respectively ASi1 Asik and ASO1 to Asok.

The switching elements of the first two floors form an input selection unit USi, while the switching elements of the last two floors form an output selection unit USO. These two selection units are coupled to one another by links joining the homologous outputs and inputs.

All that was exposed relatively to the network of Figure 5 still applies here, whereas two elementary switches counterparts of the two central floors form only. However, from the perspective of the order, the unit switches to ASi1 Asik will advantageously equipped to operate a distribution, the mode of transport either point to point or point to multipoint. The ASO1 switches Asok, in turn, from the perspective of the order, will be treated as the switching elements AS1 ASk of Figure 5.

The switching network of Figure 7 is similar to that of Figure 6, but folded, thus bidirectional, confusing the switching elements extreme floors, TSi1 to tsit and Tso1 to tSOT in first stage switches TS1 TST, while we took over the designation of the switches of the second floor of Figure 5, AS1 ASk to the switching elements of the second stage of Figure 7.

The inputs of the first stage switches are shared between input ports and output ports of the switching network (by halves for a free expansion / concentration network). The internal links are double, having one or more links to each routing direction. The switches are bidirectional and they perform reflection, either the first floor or in the second floor.

In the routing of a cell of an input of the elementary switch TS1 to one or more outputs of another TST switch, whether in the context of the routing point to point or point to multipoint, the switch TS1 accomplishes a distribution to all switches of the next stage, while the switches of the second floor that carries the cell applies the routing mode "group" or "broadcast" and it is the same in regarding first switching element TST. In the case of a transfer unit of an input of the elementary switch TS1 to one or more outputs of the same switch TS1, a transfer of reflection can be effected directly at the first stage, that is to say in TS1 bidirectional switch which transfers the cell directly to the recipient or recipients outputs, instead of the normal transfer distribution to the next stage.

All that has been exposed on the network of figure 5 therefore also applies to the network of Figure 7, with the required conversions considering the superposition of the two traffic routing directions to the switches of the two stages and the execution of a reflection in the switches of the first or second stage.

Referring to Figure 3, the switches of the first stage comprises 16 inputs and 16 outputs respectively connected to input ports and output ports. They still have 16 inputs and 16 outputs connected to 16 / m of the second stage switches, when m is the number of internal links between two switches belonging respectively to each of these two stages. If the first stage comprises 16 switches (where m = 1), 16 inputs and 16 outputs of the second stage switches are respectively connected to the 16 first stage switches by 16 bidirectional stitches each comprising a single bond in each direction of routing. Traffic from the 16 entries is then reflected to those 16 outings. The other 16 inputs and outputs of the second stage switches are not used and are available for an extension of the network by adding a third floor. If the first stage comprises up to 32 switching elements, the 32 inputs and 32 outputs of the second stage switches provide the 32 mesh two links, one in each direction of routing, which are necessary to achieve them.

The switches of the operation mode in the treatment of both routing directions has already been explained with reference to Figures 3 and 4.

Referring now to Figure 8 which shows a switching network derived from that of Figure 5, but here obtained by juxtaposition of two switching networks unidirectional separate but homologous floor by floor, each allowing the transfer in a given direction, of N1 entries from one side to the N2 exits on the other side, or N2 input side of the latter to the N1 outputs of the first side. In fact such a switching network may typically be used to form an asymmetrical set interconnecting N1 bidirectional link from one side to N2 bidirectional connection on the other side, with N1&gt; N2. The unidirectional network N1 to N2 thus achieves a concentration of traffic and one-way network N2 to N1 a traffic expansion. Each of these unidirectional networks differs from that of Figure 1 only by the fact that it is asymmetrical due to the presence of at least one stage of switching elements asymmetrical, that is to say in which the numbers of inputs and outputs are different, for example 32x16 or 16x32. Apart from this alternative configuration, routing principles described for each stage of Figure 5 network remain applicable to corresponding stages in each of these two asymmetric unidirectional networks.

9 shows an equivalent switching network of Figure 8, a bi-directional configuration. In this case, the switching network interconnects the asymmetrical N1 input and output ports on one side N2 input ports and output from the other side. Assuming N1&gt; N2, such a network is typically applied to the concentration of N1 bonds with relatively low traffic to N2 links to most traffic. cell transfer can be made between these two sets of ports N1 and N2, or unidirectional, to an input port of all N1 (or N2) to an output port of the whole N2 (or N1 ) or bi-directional between an input and output port of all N1 and an input and output port of the whole N2. Moreover, the presence of at least one bidirectional floor also allows the transfer of cells between an input port and an output port of the same set N1 (or N2), performing a reflection in a bidirectional floor. Configuration point of view, the design of this network is similar to that of Figure 8; as in the latter, at least one of the stages is asymmetrical, so that the present switching network input ports and output numbers N1 and N2 of different sides of the switching network.

The different transfer sequences are applied in the following way:<ul><li>For a non reflective cell transfer between an input port on one side of the network (set N1 or N2) and an output port on the other side of the network (set N2 or N1), the first floor distributes traffic entering all the switches from the intermediate stage. Then, it performs a selective routing to the last stage by transferring the cell to one or more output groups leading to one or more of the last stage switches. In the latter, a selective routing to transfer the cell to the output ports or destinations.</li><li>In the case of a reflected transfer between an input port and an output port of the same set N1 or N2, reflection can occur in the first stage switch, if the ports are connected to the same switch and s' it is bidirectional. Otherwise, the first stage switch distributes the cell to any of the switches of the intermediate stage, which will advantageously bidirectional to allow such transfers reflected by selective routing to or the first stage switches. In the latter a selective routing to transfer the cell to the recipient or recipients outgoing ports.</li></ul>

10 shows an extension possibledu switching network of Figure 9 by adding an additional selection stage. In addition, the first two stages of switches on the side of the set of N1 input and output ports, are formed in m selection units in two stages, bidirectional routing, each similar, close dimensioning, network of Figure 7, the switching elements being also identified by the same references as in the latter figure.

Apart from the addition of a fourth stage and the organization of the first two floors along the entire NI ports, the possible transfer types in such a bidirectional asymmetrical switching network can easily be extrapolated from that of the Figure 9:<ul><li>A transfer not reflected between cells of all N1 input port and an output port of the set N2 is performed by the first stage of distribution to any of the switches of the second stage of the selection unit then it makes a distribution to any switch of the third floor. In the latter, the switch performs a selective routing to one or more of the fourth stage switches, the latter effecting a selective routing to one or more output ports of all N2.</li><li>To transfer non-reflective cells in the opposite direction of all N2 to N1 the set, the first floor distributes each cell to one of the following stage switches. In this direction of transfer, it performs a selective routing to one or more of m selection units in two stages, while freely selecting one of the third stage switches in each recipient selection unit. A switch in the third stage, a selective routing transfers the cell to one or more switches of the fourth stage, the latter effecting a selective routing to one or more output ports of all N1.</li><li>To transfer reflected between an input port and an output port of the same set N2 or the same subset N'1 a selection unit, reflection occurs to either the first or second floor as in the network of Figure 9.</li><li>By cons, for a reflected transfer between an input port and an output port of the same set N1, but two different selection units, reflection is possible only at the third floor that interconnects m selection units. In this case, the first stage performs a distribution to the switches of the second stage; it also makes a distribution to the third floor switches; the latter then reflects the transfer and performs a selective routing to one or more recipients selection units, while leaving free choice between the switches of the second floor in each unit concerned selection. Then the second stage switch performs a selective routing to one or more switches of the first floor, the latter performing a selective routing to one or more output ports of all N'1 recipients.</li></ul>

This example switching network again illustrates the fact that, according to the invention, the outputs of groups formed in the switches of the switching network are not the same depending on the floor which they belong and that he held account in the routing mode implemented, at each stage, although the routing information of the cell remains the same in all stages.

It will then turn to Figure 11 which shows a unidirectional switching network composed of selection units which include terminal units of TSUi input PS selection planes and terminal units TSUo output. In each selection unit, there are switching elements which may be of the preceding figures, each represented by the usual sign of a switching matrix, with, on the left, the number of inputs of the switching element and to the right, the number of its outlets. These switching elements are interconnected by links.

Inside a terminal input unit, TSUi1 for example, there are two stages of switching elements, the switching elements TSi1 to TSi16 and the switching elements ASi1 to ASI4. I1 are generally one or more meshes between an output of a switching element of the first stage and an input of a switching element of the second floor. The four outputs of first stage switch, TSi1 for example, are then each connected to one or more inputs of each of four switching elements of the second stage. In the case of a single mesh, the 16 inputs of a switching element of the second stage, ASi1 for example, are each connected to an output of each of the switching elements 16 of the first stage. 16 times 4 inputs of the switching elements of the first stage are connected to 64 input ports to pi1 pi64. The other input terminal units may be similar, the numerical values ​​given closely. In this example, the output terminal units are assumed to be arranged in the same manner and symmetrically. Thus, the terminal unit output TSUo1, for example, provides access, by the two stages of switching elements the switching elements comprising ASO1 to ASO4 and Tso1 to TSo16, to output ports PO1 to po64.

The figure also shows terminal units, input and output TSUi128 TSUo128 and to indicate a total number of terminal units of the switching network.

Selection plans such as PS1 selection plan, include three selection stages formed unit switches to PSI1 PSi32, PSC1 to PSc16, PSO1 to PSo32. The arrangement of the internal links between one stage and the next follows the principle of the selection of the terminal units, assuming in this example a mesh count between switches equal to one; will not be described in detail.

It is expected 16 selection planes PS1 to PS16. The 16 outputs of a second stage switch with a terminal selection unit input, TSUi1 for example, are individually connected, by 16 mesh, to an input of each of the 16 selection planes. The 4 outputs of the same rank of the four elementary switches of a terminal unit input, TSUi1 for example, are connected to successive inputs of a switching element PSI1 example of a selection plan, the PS1 occurence. So the 512 entries of a selection plane PS1 for example, are connected, four by four, the four elementary switches on the second floor of each terminal units 128 input.

The arrangement of the mesh among the outputs of the switching elements of the third stage of the selection planes, PSO1 to PSo32 to the selection plane PS1 for example, and the inputs of switching elements of the first stage of the terminal output units is symmetrical with the one we just described.

When the entire switching network is symmetrical about the central stage of the selection planes, that is to say when the number of entries and switch outputs and the numbers of stitches per counterparts verticuale central symmetry are identical, it is possible to realize a folded equivalent switching network with bidirectional switches at least for a part of the stages, as shown in Figure 12 and described loin.Chaque central switching element, such as PSC 1, is connected, by three switching stages, on each side, to all input and all output ports. Conversely, between any input port and any output port, there are in this example more than 4000 (4k) separate paths through one of the four switches ASi of the incoming selection unit, one PS 16 selection planes, one of the 16 central switches PSc in a plane, and one of the four switches ASo the outgoing selection unit. Given the total of each input port accessibility to all PSc central switches of all plans, the transfer in this first part of the network realizes a widespread distribution of all incoming traffic on 16x16 all core switches PSc so thoroughly mix all the incoming traffic cells.

Then PSc of the central stage to the output ports, routing is necessarily selective, to attain the destination output ports. If it is to achieve several distinct output ports, a multi-point routing, this selective routing must include several branches to one or plsieurs floors.

Referring now to the foregoing descriptions, relating in particular to Figures 1 and 3, we will define how the various modes of delivery are applied to the switching elements of the network of Figure 11.

First we will consider a point to point routing, for example between the pi1 input port and port po1 output. In the label of the cell, a given RCC control field of routing mode specifies the delivery point to point. The RCA output address contains 7 bits designating the terminal unit TSUo1 and 6 bits po1 designating the output port in the terminal unit.

In the switching elements of the first stage of the switching network, such as TSi1, routing parameters are such that the cell is sent on one among the set of all outputs of the switching element. We saw the conditions of the selection previously. For example, the cell is thus sent to the ASi1 switching element.

In the switching elements of the second stage of the switching network, such as ASi1, routing parameters have the same effect as in the first stage and the cell is thus sent on one among the set of all outputs of the switch basic, for example that which leads to the plane PS1 and therefore, therein, to the switching element PSI1.

It still is the same in the switching elements of the third stage of the switching network and the cell manages eg PSC1 switch unit.

From the central stage, routing becomes selective, at least in part.

Routing settings of the switches of the central stage of the switching network are such that the commutaeur PSC1 selects a group of four terminal units in which the terminal unit is the destination, on the basis of 5 bits, from the 7 bits designating the terminal selection unit, which designate the routing group, in this example a single output, leading to one of the 32 switching elements of the fourth stage of the switching network in the PS1 plan accesses the destination terminal unit. And is selected mesh PSO1 leading to the switch unit.

The mode of operation is similar to the one we have just seen, in the switching elements of the fifth stage of the switching network. The routing settings are different; they cause the selection of two remaining bits of the identity of the destination terminal unit, which identifies a routing group comprising four exits leading to the four elementary switches to ASO1 ASO4, according to the example. One of these four outputs is selected in the manner mentioned above. It leads the cell, e.g., until the ASO1 switch.

In the switching elements of the sixth stage of the switching network, routing parameters select among the 6 bits of the address designating the RCA output port, 4 bits identifying the switch unit on the top floor serving that output port. The cell is thus conducted to the switching element Tso1 in accordance with the chosen example.

Finally, similarly, in the switching element of the last stage of the switching network, the routing parameters will transfer the worm cell the output port PO1.

At this point to point transfer sequence, the routing parameters of the switching elements of the different stages have therefore first carried out the non-selectively to any cell switching element of the central stage, and then the lead selectively, exploiting successive portions of the RCA output address, to the specified destination.

It is easy to verify that, to the extent that all the switching elements of the central stage in a selection plan, see the 32 switching elements of the fifth floor of the selection plan in the same way, routing is the same in each of them. Similarly, to the extent that all the selection planes see the terminal units of output in the same way, it can be concluded that all the switching elements of the central stage perform the routing in the same way. A similar reasoning leads to the same conclusion with respect to the switching elements of the other stages from the fifth to last. The conclusion is that, in such an example of folded switching network, the routing parameters depend only on the identity of the floor wherein the switch unit is included, not of its position in the floor.

By cons, they could also depend on the position of the switching element in the stage, in some variants of this type of switching network, for example such that all terminal units or all of the selection planes is not composed of identical configurations of selection units, as is the case, for example, during switching network extension operations requiring a gradual shift from one configuration to another.

Furthermore, it should be noted that successive cells of the same origin and the same destination can, mainly through the brewing routing practiced in the early stages of the switching network, take many different paths, which makes the mixing of streams of regular and irregular traffic, favorable to flow more homogeneous various cell rates subjected to the switching network and therefore the relative performance of the cell transfer.

The delivery of multi-point, in such a network is carried out on the same basis, except in some or all floors selective routing, there is a multiplication of the cell with retransmission groups different outputs in the stage switches where the multicast tree indicates that several output branches are required to the next stage.

This example illustrates how the point to multipoint transfers according to predetermined broadcast trees can be used according to the invention in multipath networks and self-routing, while maintaining this type of transfer can choose a path for any one to many ports of the plurality of possible paths through the switching network, with a characteristic organization of the content of broadcast trees memories of elementary switches on different floors. According to the invention, it is possible to define the corresponding branch points so that no unnecessary copy is generated at any stage, allowing avoid internal overloading of internal links between floors. This characteristic is achieved by the following principles:<ul><li>no copy in the stages of distribution;</li><li>the same contents (points of branching) distribution tree memory in all switches of a stage which belong to the same set of multipath equivalents to route the cells to the next stage of switch groups;</li><li>in these "equivalents" switches that perform a selective routing of various distinct routing groups, a connection to a plurality of predetermined routing groups (in the multicast tree of memory) is performed by transferring a copy of the incoming cell only routing groups marked connections required in these switches among the set of possible routing groups. Thus, no unnecessary copy is generated on each floor.</li></ul>

12 illustrates the folded version of the network of Figure 11, obtained by using at least some stages of the bidirectional switches, except for the central stage PSc remains unidirectional. By the analogy of the notations used, it is clear that the peer switches can now be combined into bidirectional stages, namely:<ul><li>previous stages 1 and 7 (TSi and TSO) become the first two-way stage (TS)</li><li>the previous stages 2 and 6 (ASi and ASo) become the second bidirectional stage (AS)</li><li>the previous stages 3 and 5 (PSI1 and PSO1) become the third bidirectional floor (PSa).</li></ul>

For cons, the central stage PSc remains unidirectional and fourth floor is called mirror stage (required reflection).

All the characteristics and properties of the unidirectional network of Figure 11 can be readily transposed to that of the folded release: <ul><li>The same number of possible paths exist, not including additional trips made possible by intermediate reflections described below.</li><li>The two major steps, during the transfer of a cell, general distribution and selective routing, are also carried out referring now to a first transfer part in the incoming direction to the floor of reflection and a second portion transfer in the outgoing direction from the latter to the first floor, routing operations on each floor easily be transposed by symmetry and being based on the same principles as those described for the network in Figure 11.</li></ul>

However, the folded variant of Figure 12 has the following additional characteristics derived intrinsic faculties of reflection possible in a bidirectional switch as described above:<ul><li>In the first step of a transfer point to point, wherein the cell is freely distributed in the incoming direction towards one of the switches of the next stage, each stage bidirectional, potentially TS, AS and PSa, premature reflection is possible whenever the destination output port is accessible by the relevant switch, and of course if it is bidirectional. Such premature reflection is possible:<ul><li>TS on the first floor if the destination port belongs to the group of ports connected to the switch TSx considered,</li><li>AS the second floor if the destination port belongs to the terminal unit in which is considered the switch ASx,</li><li>the third floor PSa if the destination port belongs to the group of four terminal units to which the switch is connected TSax considered.</li></ul></li><li>Such possibilities prematurely induce reflection of the following properties:<ul><li>a relative decrease in the burden of internal links insofar as part of the cell traffic does not pass through all the stages of the switching network,</li><li>increasing the number of possible paths, namely the reflected paths prematurely</li><li>the possibility of equipping the sub-switching network of the figure number of stages and proceeding to successive floors extensions without modifying wiring between stages, insofar as each bidirectional floor 1, 2 or 3 can be temporarily the top floor fitted and then perform the required reflections of a mirror floor.</li></ul></li></ul>

It is obvious that the above descriptions have been given by way of example and that numerous variations can be devised without departing from the scope of the invention. Digital information in particular can change with every application.