Multi-data rate selectable equalizer.

This invention relates to equalizers for use with data signal transmission and, more particularly to a multi-data rate selectable equalizer which will equalize a transmission media over which one of a plurality of data signals having different data rates are selectively transmitted.

The IEEE 802.5 Token Ring Local Area Network uses a balanced twisted pair wire for data transmission. In this system data is transmitted using an encoding technique known as differential Manchester encoding. As the signal travels down the twisted pair, it undergoes phase and amplitude distortion which varies with the length of the transmission line and the data rate. This distortion gives rise to intersymbol interference and may be corrected by using an equalizer circuit located at the receiving end. Most of the prior equalizers are not used for equalizing signals at different data rates. Solutions to the equalization of multi-data rate transmission systems have been given. But all these solutions have disadvantages which are not desirable such as signal distorsion and excessive feed through of unwanted signals.

Therefore, the object of the present invention is an equalizer circuit which can selectively equalize signals at one or more than one data rate.

The equalizer circuit includes a plurality of equalizers each adapted for connection to the transmission medium and arranged to equalize the transmission medium for signals at a different one of the more than one different data rates. Each of the equalizers includes a controllable means having a first state in which the equalizer is operative and a second state in which the equalizer is inoperative. Means are provided for selectively controlling a single means associated with one of the equalizers to a first state and the remaining means to the second state whereby the transmission media is equalized only by the equalizer associated with the means controlled to the first state and all of the other equalizers remain in the inoperative state.

A description of the invention will now be made with reference to the accompanying drawings wherein:

Figure 1 is a circuit diagram of a prior art equalizer suitable for equalizing a transmission media operating at a single data rate.

Figures 2 and 3 are circuit diagrams of early attempts which proved to be unsatisfactory at the data rates used in the contemplated application; and,

Figure 4 shows a circuit diagram of a multiple equalizer constructed according to the invention.

Figure 1 illustrates a prior art equalization circuit suitable where a single data rate is employed. The equalizer has a pair of input terminals 11 and a pair of output terminals 12. A differential amplifier/filter including a pair of transistors 14 and 15 provides an output at the pair of terminals 12 which is a function of the differential input applied at the pair of input terminals 11. A pair of constant current sources 16 and 17 regulate the total current through transistors 14 and 15. The frequency response and group delay characteristics for small signals can be tailored by selection of a suitable impedance Z. (Voltage transfer from input to output = 2*RL/Z) As the input signal gets larger, corresponding to shorter lengths of transmission line, the transfer function from input to output becomes non-linear and reduces the amount of frequency and group delay correction. When the input signal at the pair of input terminals 11 is sufficiently large, the collector current through transistor 14 is cut off. Current flowing through transistor 15 will flow through impedance 18 and current source 16 as well as current source 17. Conversely, when the collector current through transistor 15 is cut off, current flowing through transistor 14 will flow through impedance 18 and current source 17 as well as through current source 16. This circuit is inserted in the data path at the receiver.

If the transmission media, that is the twisted pair used to carry signals between stations, is to carry signals having different data rates at different times, the equalizer illustrated in Figure 1 cannot cope with different data rates such as 4 or 16 megabits. A pair of equalizers each suitable for equalizing the line for the different data rates will be required. Figures 2 and 3 show early attempts at solving the problem by providing two equalization circuits. In Figure 2 the signal from the input is applied to a first equalizer 1 and a second equalizer 2 and an electronic analog switch is used to select one or the other equalizer. In the equalizer of Figure 3, two impedances Z₁ and Z₂ are selected depending upon the data rate of the signal applied to the transmission media. Z₁ is selected, for example, to compensate the transmission media for a 4 megabit data rate while Z₂ will be selected to compensate the transmission media for a signal at a 16 megabit rate.

The circuits illustrated in Figure 2 and Figure 3 are potential solutions to the equalization of multi-data rate transmission systems. However, for reasons which will be explained below, neither of these circuits is desirable.

The obvious disadvantage of the circuit illustrated in Figure 2 is the duplication of components and the additional space required for providing multiple equalizers.

A second disadvantage is the possibility of feedthrough of unwanted signals from the deselected equalizer. The extent of the feedthrough would depend entirely on the type of switch used. If a relay is used, the open contacts must have very little capacitance across them. Capacitance as small as 1 pico-farad could allow excessive feedthrough of unwanted signals. This low value of capacitance is not difficult to achieve with relay contacts. However, relay contacts have other disadvantages such as requiring power for operating the coil and requiring a large amount of area on circuit boards, etc. Analog switches used as an alternative have unique problems of their own. While they solve the space problem, they have electrical characteristics which are undesirable. They have a relatively large series resistance (50-100 ohms) for closed switches and large capacitances (substantially greater than 1 pico-farad) for open switches. These characteristics add undesirable signal distortion and allow excessive feedthrough of unwanted signals. In addition, there is excessive capacitive coupling between different switches fabricated on a single chip.

The circuit illustrated in Figure 4 utilizes a plurality of equalizers 40 and 41 which are similar in some respects to the single equalizer illustrated in Figure 1. Equalizer 40 includes a pair of transistors Q₁ and Q₂ having their collectors connected to Vcc by resistors R₅ and R₆ respectively. The emitters of Q₁ and Q₂ are connected to ground through controlled constant current sources Q₃ and Q₄. The bases of Q₁ and Q₂ are connected to the input terminals (Vin) and the collectors are connected to the output terminals (V out). A pair of resistors R₁ and R₂ provide bias voltage to the base of Q₁ while resistors R₃ and R₄ provide bias voltage to the base of Q₂. An impedance Z₁, selected to equalize the transmission media at a given data rate, is connected between the emitters of Q₁ and Q₂.

In the prior art circuit, transistors Q₃ and Q₄ are permanently biased on which is not the case for the equalizer illustrated in Figure 4. In this novel circuit, a transistor Q₅ has its collector connected to its base and to Vcc via R₇. Current flows from Vcc through R₇ and the base emitter of Q₅. Q₃ and Q₄ are connected to Q₅ and together form mirrored current sources for Q₁ and Q₂. By applying an appropriate control voltage (B₁) to the bases of Q₃, Q₄ and Q₅, the current sources Q₃ and Q₄ can be gated off. When these current sources are not gated to the off or inoperative state, the transistors Q₁ and Q₂ along with impedance Z₁ act as a differential amplifier/filter and provide an output at Vout that is dependent on the input at Vin. When the current sources are selected to the off or inoperative state, no current flows and no voltage is present at Vout as a result of the action of equalizer 40. Capacitor C₁ prevents any switching noise from modulating the current sources and degrading the output signal.

Equalizer 41 is identical to equalizer 40 and shares Vcc, Vin, Vout and R₁₋₆. It is connected in parallel with equalizer 40 to Vin, Vout and Vcc and the shared biasing resistors. A significant difference is the provision of a separate current source control provided by Q₁₀ and R₈ which allows the individual current sources to be individually controlled. Of course the impedance Z₂ of equalizer 41 is selected to equalize the transmission media at a different data rate.

Switches SW₁ and SW₂ under control of selection signals S₁ and S₂ apply bias voltage B₁ (typically 0 volts) to the bases of transistors Q₃₋₅ and Q₈₋₁₀. In the illustrated embodiment, current sources Q₃ and Q₄ will be on or operative when sources Q₈ and Q₉ are off or inoperative and visa versa.

When the Q₃ and Q₄ current mirrors are on and the Q₈ and Q₉ current mirrors are off, the signal path through Q₆ and Q₇ is blocked since the base collector junctions of Q₆ and Q₇ are reversed biased which makes the base collector capacitance a fraction of a pico-farad. Such a small capacitance allows only a negligible feed-through. With the path through Q₆ and Q₇ blocked, the equalizer characteristics are determined by Z₁ only. When the control signals are reversed, mirrored current sources Q₃ and Q₄ are off and mirrored current sources Q₈ and Q₉ are on. This will block the signal path through Q₁ and Q₂ and the path through Q₆ and Q₇ will allow Z₂ only to determine the equalizer characteristics.

If more than two data rates are to be accommodated, then additional equalizers must be connected in parallel with equalizers 40 and 41 and the switching circuit expanded whereby the current sources of the desired equalization Z_i is turned on or rendered operative while the remaining current sources (Z₁...Z_i-1, Z_i+1...Z_n) are turned off or rendered inoperative.