Integrated digital signal processor/general purpose CPU with shared internal memory.

0001The present invention relates generally to data processing systems and, in particular, to a processing platform that provides integrated general purpose and digital signal processing (DSP) capabilities for recovering and processing digital data utilizing an internal shared memory resource.

0002The basic function of any communications system is to transmit information over a communication channel from an information source to a destination as fast and as accurately as possible.

0003There are two general types of information sources. Analog sources, such as a telephone microphone, generate a continuous signal. Digital sources, such as a digital data processing system, generate a signal that consists of a sequence of pulses.

0004Communications channels that are designed to transmit analog signals (e.g., the telephone network) have characteristics which make it difficult for them to transmit digital signals. To permit the transmission of digital pulse streams over an analog channel, it is necessary to utilize the digital data pulses to modulate a carrier waveform that is compatible with the analog transmission channel.

0005The equipment that performs the required modulation is generally referred to as a "MODEM". The term "MODEM" is an acronym for MOdulator-DEModulator, since one piece of equipment typically includes the capability not only to modulate transmitted signals, but also to demodulate received signals to recover the digital data from the modulated analog carrier waveform.

0006While passing through the transmission channel, the modulated carrier waveform suffers from distortion introduced both by the system itself and by noise contamination. Thus, one of the tasks of the modem's demodulation function is to filter the signal received from the transmission channel to improve the signal-to-noise ratio. The demodulator also retrieves timing information from the received signal to provide sampling points for recovering the digital data. The demodulator may also condition the data in other ways to make it suitable for additional processing.

0007In a conventional modem, the signal filtering, sampling and conditioning tasks are performed by three functional units: analog-to-digital conversion circuitry ("analog front end") that converts the received modulated carrier waveform to a digitized replica, a digital signal processor (DSP) that recovers the digital data from the digitized replica, and a control function for controlling both the analog front end and the digital signal processor. The digital signal processor recovers the data by implementing a signal conditioning and data recovery algorithm that is specific to the type of data being received.

0008For example, the digital signal processor function in a facsimile (fax) machine modem implements a special purpose algorithm that can only be used for recovering digital fax data. In the case of a fax system, the data to be recovered is a digital bit map that corresponds to the transmitted hard copy image and which has been compressed to facilitate efficient transmission. The algorithm implemented by the digital signal processor function of the receiving fax machine's modem is a dedicated "fax" algorithm that has been designed specifically for accurately recovering the compressed bit map. It cannot recover digital data in a format other than a compressed bit map, e.g. voice mail data or data modem applications. A different digital signal processor implementing a different dedicated "voice mail" or "data modem" algorithm is needed for each of these other applications.

0009As shown in Fig. 1, a conventional fax machine architecture may be partitioned into two major functional blocks: (1) a special purpose fax modem block of the type described above for recovering a compressed bit map from a modulated carrier waveform and (2) a general purpose processor block for performing those tasks required to convert the compressed bit map to a corresponding hard copy image.

0010A well known example of a special purpose fax modem block is the Rockwell R96DFX MONOFAX® modem chip, the so-called "Rockwell Module". In the Rockwell Module, the incoming modulated carrier waveform received from an analog channel, i.e., a telephone line, is processed by an analog front end which generates a digitized replica of the analog signal; that is, the analog front end generates a digital reading of the input voltage level. A dedicated fax digital signal processor then performs the adaptive filtering, signal sampling, synchronization and carrier phase/frequency tracking required to reconstruct the compressed facsimile bit map from the digitized replica provided by the analog front end. The recovered bit map is then provided to the general purpose processor block which performs the additional processing functions required for printing the transmitted image. That is, the general purpose processor block controls and performs the data decompression, decoding, imaging and printing functions necessary to generate a hard copy reconstruction of the recovered bit map.

0011To transmit an image, the fax machine shown in Fig. 1 performs the above-described steps in reverse order. The general purpose processor block controls and performs the conversion of the hard copy image to a corresponding compressed bit map. The compressed bit map is then provided to the special purpose fax modem block which utilizes the bit map to modulate a carrier waveform which is transmitted over the analog channel to a destination fax machine.

0012A modem architecture similar to that of the Rockwell Module is also provided by the Yamaha YM7109 FAX modem LSI chip.

0013The fax machine architecture exemplified by the Rockwell Module and the Yamaha modem chip, that is, a special purpose fax modem block in combination with a separate general purpose processor block, suffers from a number of disadvantages. First, the system requires two separate processor functions: the special purpose DSP function of the modem block for recovering the compressed bit map and the general purpose processing and control functions of the general purpose processor block for performing the remaining tasks required to convert the compressed bit map to hard copy. Since there are periods of time when no facsimile transmissions are being received, the system's full processing capability is greatly underutilized. Furthermore, the DSP functions of the modem block are dedicated to a particular application, in this case, facsimile reception/transmission. That is, as stated above, the DSP algorithm utilized to recover the incoming data is fixed; aside from the ability to modify the coefficients of the "fax" algorithm, there is no flexibility in the modem algorithm to allow it to perform tasks other than facsimile data recovery. This results in a high-cost, application-specific system architecture with redundant processing capabilities.

0014A variation in the Rockwell and Yamaha modem architectures is exemplified by the OKI KV96-X6D modem chip set. While the architecture of the OKI modem chip set maintains the separate modem and general purpose processor functions of the Rockwell and Yamaha modems described above, its analog front end and DSP functions are also separated. Since the DSP function is programmable, some flexibility in the type of signal that may be processed is permitted. However, once programmed, the DSP function of the OKI modem still relies on a fixed DSP algorithm. Thus, the OKI architecture has the same basic limitations and inefficiencies as the Rockwell and Yamaha devices.

0015The Texas Instruments TMS320C25 Digital Signal Processor provides a "general purpose" DSP capability in that it can accommodate a number of DSP algorithmic sequences. However, it relies on dedicated memory for storage of its DSP operations and data. Thus, it must incorporate its own segregated control capability aside from that provided by the general purpose processor with which it is associated.

0016NEC IC Microsystems Ltd. provides a modem DSP chip that includes a DSP core that is integrated with a general purpose processor block. However, the DSP core of the NEC device is dedicated to a particular algorithm and relies on its own control functions and an internal memory separate from that of the general purpose processor function for storage and retrieval of its operands. Furthermore, the general purpose processor function is fully embedded, making it unavailable for tasks other than those related to the dedicated DSP function.

0017It would, therefore, be desirable to have available a dual processor platform that can execute a variety of DSP algorithms while maintaining full general purpose processor capability, and the invention as defined in the independant claims addresses this object. In a preferred embodiment,

0018the present invention provides a data processing system that utilizes integrated general purpose processor (GPP) and digital signal processor (DSP) functions that are connected for common access to an internal shared memory array. The shared memory array stores the operands for a set of basic DSP operations that can be executed by the DSP function. The sequence of DSP operations to be executed by the DSP function is selectively configurable by the GPP function; that is, the general purpose processor can define a variety of DSP algorithms that can be executed by the DSP function for processing different digital input signal formats. In addition to storing the operands required by the DSP function for execution of a DSP algorithm, the internal shared memory array also stores selected instructions and data required by the GPP function for execution of general purpose tasks. The operands, insructions and data may be selectively loaded to the internal shared memory array from system memory. After execution of a DSP algorithm, the corresponding information set may be down-loaded from the internal memory array to system memory and a new information set retrieved for execution of a subsequent DSP algorithm or a new general purpose processor task.

0019Thus, in accordance with the principles of the present invention, the general purpose processor selects a DSP algorithm for conditioning and recovering digital data from the incoming signal. That is, the GPP selects from the set of basic DSP operations to define a specific sequence of DSP operations appropriate for processing the incoming signal. The GPP then retrieves operands required for execution of the selected DSP algorithm and/or instructions and data critical to the GPP for controlling the DSP function or for performing GPP tasks and loads them into the internal shared memory array. Next, the GPP invokes the first DSP operation in the selected sequence and the DSP function performs the DSP operation utilizing operands retrieved by the DSP function from both the shared memory array and system memory. Upon completion of the DSP operation by the DSP function, the GPP function either reads the result of the DSP operation, invokes the next DSP operation in the selected sequence or performs a GPP task. This process continues until the selected sequence of DSP operations has been executed by the DSP function. The GPP may then download from the internal shared memory array the operands, instructions and data utilized in executing the selected DSP algorithm and either identify and execute a subsequent DSP algorithm fashioned from the set of basic DSP operations or retrieve instructions and data required for a separate GPP task.

0020While the input signal to the data processing system may be received directly from a digital source, a preferred embodiment of the invention includes an analog front end that converts a modulated input signal received on an analog channel to a corresponding digital signal for processing by the data processing system.

0021Thus, a data processing system in accordance with the present invention provides a unique system partitioning by integrating a small DSP module and a general purpose processor. This unique partitioning provides a single processor solution for both DSP and general purpose computations that can utilize the same programming model and the same system development tools for both functions. The DSP module provides the capability necessary to handle a variety of DSP requirements. The internal shared memory allows the DSP algorithms to be tuned or changed or new algorithms to be added to meet changing, expanding system requirements; general purpose computation intensive tasks can also be executed directly from the internal shared memory.

0022A better understanding of the features and advantages of the present invention may be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. <ul id="ul0001" list-style="none"><li>Figure 1 is a block diagram illustrating the basic functional partitioning of a conventional facsimile system.</li><li>Figure 2 is a block diagram illustrating the basic functional partitioning of a data processing system in accordance with the present invention.</li><li>Figure 3 is a block diagram illustrating the primary functional units of a data processing system in accordance with the present invention.</li><li>Figure 4 is a block diagram illustrating a DSP module utilizable in a data processing system in accordance with the present invention.</li><li>Figure 5 illustrates the general purpose processor address mapping of a data processing system in accordance with the present invention.</li><li>Figure 6 is a table illustrating the memory organization of a complex vector for use in a DSP module in accordance with the present invention.</li><li>Figure 7 provides an instruction set summary for a DSP module in accordance with the present invention.</li><li>Figure 8 is a table illustrating the handling of cyclic buffers for a DSP module in accordance with the present invention.</li><li>Figure 9A is a block diagram illustrating an internal bus configuration of a data processing system in accordance with the present invention with the DSP module executing a VCMAG command.</li><li>Figure 9B is a block diagram illustrating an internal bus configuration of a data processing system in accordance with the present invention with the DSP module executing a VCMAD, VCMUL or VCMAC command.</li><li>Figure 9C is a block diagram illustrating an internal bus configuration of a data processing system in accordance with the present invention with the general purpose processor executing a read or write to registers of the DSP module or to the internal memory array.</li></ul>

DETAILED DESCRIPTION OF THE INVENTION

0023Fig. 2 shows a data processing system 10 which is uniquely partitioned in accordance with the concepts of the present invention. The data processing system 10 is described below in the context of the requirements of a facsimile system. However, it will be understood by those skilled in the art that the principles of the invention are applicable to any system which receives an incoming data signal that requires digital signal processing.

0024The data processing system 10 shown in Fig. 2 includes two primary functional elements: an analog front end 12 and an integrated processing platform 14. The integrated processing platform 14 includes both a digital signal processor (DSP) module 16 and a general purpose processor (GPP) 18.

0025The analog front end 12 converts a modulated input signal received from an analog transmission channel, e.g. a telephone line, to a digitized replica of the modulated input signal. The analog front end 12 can be implemented utilizing conventional, off-the-shelf integrated circuit products available for this purpose.

0026As stated above, the integrated processor platform 14 includes a DSP module 16 that recovers digital data from the digital signal generated by the analog front end 12. The DSP module 16 includes a processing mechanism, described in greater detail below, that conditions the digital signal utilizing an algorithm comprising a selected sequence of DSP operations.

0027The general purpose processor 18 controls the DSP module 16 and processes the digital data generated by the DSP module 16 to a desired end result. The general purpose processor 18 may be any conventional state-of-the-art microprocessor.

0028As further shown in Fig. 2, while in many applications, the analog front end 12 will be utilized to convert a modulated input signal received on an analog channel to a corresponding digital signal, there are a growing number of applications (e.g., ISDN and T1) in which a digital input signal will be received by the integrated processor platform 14 directly from a digital source.

0029Referring to Fig. 3, both the DSP module 16 and the general purpose processor 18 are connected to an internal bus 20, allowing both the DSP module 16 and the general purpose processor 18 to communicate with a system memory (not shown) via a conventional bus interface unit 24 for transfer of control/status information and addresses/data therebetween. It will be understood by those skilled in the art that the internal bus 20 comprises both an internal address bus for handling address references by the DSP module 16 and the general purpose processor 18 and an internal data bus for handling instruction and data transfers.

0030To save bus bandwidth, the DSP module 16 stores operands used in executing DSP algorithms in an internal RAM memory array 22 which, as will be described in greater detail below, is also accessible to general purpose processor 18. That is, in accordance with the concepts of the present invention, the internal memory array 22 serves as a shared resource for both the DSP module 16 and the general purpose processor 18. In the illustrated embodiment, the internal memory is shown as accessible by the DSP module 16 and the general purpose processor 18 via the internal bus 20. It will be understood by those skilled in the art that other bus structures would also provide the desired shared accessibility to the internal memory array 22; for example, the internal memory array 22 could be implemented as a dual port memory.

0031As described in greater detail below, the DSP module 16 may fetch operands in parallel from the internal memory array 22 and system memory.

0032The DSP module 16 executes vector operations on complex variables that are optimized for DSP applications. The general purpose processor 18 treats the DSP module 16 as a memory mapped I/O device that occupies a reserved memory space, interfacing with the DSP module 16 via a set of memory mapped registers.

0033As shown in Fig. 4, high performance is achieved in the DSP module 16 by using the internal shared memory array 22 as well as a multiplier/accumulator 26. The DSP module also includes its own internal address generator 28 for system memory and internal operand accesses, thus reducing the load on the general purpose processor 18. Both the multiplier/accumulator 26 and the address generator 28 are conventional implementations.

0034In the operation of the data processing system 10, the general purpose processor 18 selects from a basic set of DSP operations to define a specific sequence of operations as the DSP algorithm to be executed by the DSP module 16 for recovering data from the incoming digital signal. The general purpose processor then retrieves operands required for execution of the selected DSP algorithm and/or instructions and data critical to the general purpose processor for controlling the DSP module 16 or for performing general purpose tasks and loads them into the internal RAM array 22. The general purpose processor then invokes the first DSP operation in the selected sequence by issuing the corresponding command to the control register of the DSP module 16. The DSP module then places the general purpose processor 18 in a continuous wait state while it performs the first DSP operation utilizing operands retrieved by the address generator 28 from the RAM array 22 and system memory. Upon completion of the DSP operation, the DSP module cancels the continuous wait state and the general purpose processor 18 then either reads the status of the DSP module 16 or the result of the DSP operation or carries on with the execution of its normal program flow, which may be either invoking the next DSP operation in the selected sequence by issuing the appropriate command to the DSP module control register or performance of a general purpose task. This process continues until the selected sequence of DSP operations has been completed. The general purpose processsor may then download the contents of the shared internal RAM array 22 and retrieve a new set of operands, instructions and data for further DSP operations or general purpose processing tasks.

0035As further shown in Fig. 4, the DSP module 16 performs complex arithmetic calculations on two vector operands provided to the multiplier/accumulator 26 at Port Y and Port D. One vector is retrieved from the internal memory array 22. The other vector is either organized as a circular buffer in the system memory (described in greater detail below) or retrieved from the internal memory array 22.

0036The DSP module 16 executes vector operations in a two stage pipeline. This allows for a significant performance enhancement as the fetch and execution of operands for consecutive vector elements are performed simultaneously rather than in a strictly sequential manner. The DSP module 16 can fetch up to two data elements at a time, using its address generator 28 for system memory access and the internal array 22 for the second operand. While fetching operands for one vector element, the DSP module 16 performs the multiply and add operations on the previous vector element.

0037The DSP module 16 contains seven registers in addition to the RAM array 22. These registers, as well as the internal memory array 22, are accessed by the general purpose processor 18 as memory-mapped I/O devices. As shown in Fig. 5, their associated addresses reside in the upper part of a 32-bit address range of general purpose processor 18. External memory locations are specified by the lower 24 address bits and mapped to the lower 16 megabyte of this address range.

0038Any reference by general purpose processor 18 to the registers of the DSP module 16 or to the internal memory array 22 is done using a bus protocol for internal control register access to enable external observability. This protocol is more fully described in copending and commonly-assigned U.S. Patent Application Serial No. <u style="single">          </u>, filed January 4, 1990, by Zeev Bikowsky and Dan Biran, titled METHOD AND APPARATUS FOR OBSERVING MEMORY-MAPPED REGISTERS; the just-referenced Bikowsky/Biran application is hereby incorporated by reference to provide additional background information regarding the present invention.

0039Each storage location in the internal memory array 22 is 32 bits wide and holds one complex number.

0040As stated above, the internal memory array 22 is not limited to storage of filtering coefficients for a specific DSP algorithm. It can also be used as a fast, zero-wait state, integrated memory for storing instructions and data utilized by the general purpose processor 18 as well as for storing selected operands for use by the DSP module 16 for processing a variety of data signal formats.

0041The memory array 22 can be used for instruction fetches with only one restriction: instructions must be loaded into the array 22 using word aligned accesses. This can be achieved by moving the aligned double-word from system memory to memory array 22. Data can also be stored in the memory array 22 with one restriction: storing data in the array 22 can be done only if all the data is written using aligned word or double-word accesses.

0042Referring back to Fig. 4, the multiplier input register Y is a 32-bit register that holds one complex operand. The multiplier input register Y is mapped into two consecutive words called Y0 and Y1.

0043The accumulator register A is a 32-bit register that holds one complex result. The A register is mapped into consecutive words, also called A0 and A1. Internally, A0 and A1 are 32-bit registers. However, only bits 15-30 (i.e., 16 bits) are visible. The rest of the bits are used for a higher dynamic range and intermediate calculations.

0044A 24-bit pointer to the beginning of the data vector in the external system memory is provided by data pointer register DPTR. In order to implement circular buffers, only the less significant bits of the DPTR pointer are incremented. When the end of a buffer is reached, the least significant bits of the DPTR pointer are reloaded with zeroes. The number of bits that are set to zero, which defines the size of the circular buffer, is controlled by a Control Register CTL, which is described below. The least significant word of the DPTR pointer is called DPTR0 and the most significant byte is called DPTR1.

0045The CPTR register holds the address and length of the coefficient vector.<img file="EP0442041A2_D0001.tif" /><dl id="dl0001"><dt>SO - S6</dt><dd> Start Address of coefficient's vector (number of C reg.)</dd><dt>L0 - L6</dt><dd> Length of coefficient' vector (in double words)</dd></dl>

0046The Control Register CTL controls the various modes of operation of the data processing system 10.<img file="EP0442041A2_D0002.tif" /><dl id="dl0002"><dt>OPC1-0</dt><dd> Operation code.</dd><dt>00</dt><dd> VCMAD Vector Complex Multiply Add</dd><dt>01</dt><dd> VCMUL Vector Complex Multiply</dd><dt>10</dt><dd> VCMAC Vector Complex Multiply Accumulate</dd><dt>11</dt><dd> VCMAG Vector Complex Magnitude</dd><dt>DS0-DS1</dt><dd> Data Buffer Size.</dd><dt>00</dt><dd> 8 double-words</dd><dt>01</dt><dd> 16 double-words</dd><dt>10</dt><dd> 32 double-words</dd><dt>11</dt><dd> 64 double-words</dd></dl><dl id="dl0003"><dt>CLR</dt><dd> Clear Accumulator (A0 and A1) before beginning the operation.</dd><dt>COJ</dt><dd> Conjugate when set to 1, the value of the operand in Port D of the multiplier will be conjugated prior to multiplication.</dd></dl>

0047The Status Register ST holds the status of the last vector operation.<img file="EP0442041A2_D0003.tif" /><dl id="dl0004"><dt>OP0</dt><dd> Overflow occurred on calculation of A0.</dd><dt>OP1</dt><dd> Overflow occurred on calculation of A1.</dd></dl>

0048The ST register is cleared to 0 in the following cases: <ul id="ul0002" list-style="dash"><li>the user writes directly to either A0 or A1.</li><li>the user writes to the CTL register upon reset.</li></ul>

0049The operation of the DSP module 16 will now be described in greater detail; the following terms will be used in the operational description: <dl id="dl0005"><dt>C[i]</dt><dd> an entry in internal memory array 22, entry [i] can be selected by address generator 28 or directly accessed by CPU 18;</dd><dt>D[i]</dt><dd> Data from system memory fetched using address generator 28;</dd><dt>Y</dt><dd> Complex Multiplier input register 30 in Fig. 4;</dd><dt>D[i]*</dt><dd> The conjugate of D[i];</dd><dt>A</dt><dd> Complex Accumulator register.</dd></dl>

0050The DSP module 16 executes the following six basic commands: <dl id="dl0006"><dt>VCMAC</dt><dd> Vector Complex Multiply Accumulate</dd><dt>VCMAG</dt><dd> Vector Complex Magnitude</dd><dt>VCMAD</dt><dd> Vector Complex Multiply Add</dd><dt>VCMUL</dt><dd> Vector Complex Multiply</dd><dt>LOAD</dt><dd> Write into C, Y, A or CTL</dd><dt>STORE</dt><dd> Read from C, Y, A, ST or CTL</dd></dl>

0051The VCMAC, VCMAD and VCMUL commands use the following parameters: <dl id="dl0007"><dt>D</dt><dd> Vector Start Address in system memory</dd><dt>C</dt><dd> Vector Start Address in internal RAM Vector Length Control bits</dd></dl>

0052The VCMAG command uses only the last three operands.

0053Complex numbers are organized in the internal memory array 22 as double words. Each double word contains two 16-bit 2's complement fractional integers. The less significant word contains the Real part of the number. The most significant word contains the Imaginary part of the number.

0054The complex vectors utilized by the DSP module 16 consist of arrays of complex numbers stored in consecutive addresses. Complex vectors must be aligned to double word boundary. Fig. 6 illustrates the memory organization of a vector D.

0055Referring back to Fig. 4, the arithmetic logic unit 26 of the DSP module 16 contains a 16x16 multiplier 26a and a 32-bit adder/accumulator 26b. Bits 15-30 (16 bits) of the result are rounded and can be read by accessing the A register. If an overflow is detected during an operation, the Status Register (ST) overflow bit and either the OP0 bit or the OP1 bit is set to "1."

0056When data is loaded into the adder/accumulator 26b, the 16 bits of data are loaded into bits 15-30, the lower bits are set to "0," while bit 31 gets the same value as bit 30 (sign extended). An overflow is detected whenever the value of bit 30 is different from the value of bit 31.

0057Each basic DSP operation or instruction to be performed by the DSP module 16 is controlled by two OP-code bits (OPC0 and OPC1) and two specifiers (COJ and CLR). COJ specifies whether the operand on port D of the multiplier 26a must be conjugated prior to multiplication. The CLR bit is used to extend the instruction set. On VCMAC and VCMAG, CLR specifies whether the accumulator 26b must be cleared at the beginning of the vector operation. On VCMAD, CLR specifies that the operation will ignore the value of C[i]. In VCMUL, CLR indicates that the value of D[i] is to be taken instead of 1+D[i].

0058Fig. 7 provides a summary of the set of basic DSP operations executed by the DSP module 16 as a function of the OPC1, OPC0, COJ, and CLR bits in the CTL register. In Fig. 7, "SIGMA" represents the summation sign<maths id="math0001" num=""><img file="EP0442041A2_D0004.tif" /></maths>

0059All the operands are complex numbers. Thus, A = SIGMA C[i]xD[i] breaks down to: <maths id="math0002" num=""><img file="EP0442041A2_D0005.tif" /></maths><maths id="math0003" num=""><img file="EP0442041A2_D0006.tif" /></maths>

0060The accumulator 26b, the multiplier input register Y, the external data pointer DPTR and the coefficient pointer CPTR registers are used as temporary registers during vector operations. Values stored in these register prior to activation of the DSP module 16 are destroyed. If the content of the accumulator register A after an operation of the DSP module 16 is used as an initial value for the next operation, it must be remembered that the least significant bits of (0/14) may contain a value of other than zero.

0061As stated above, the DSP module 16 accesses arrays of data in external memory using the DPTR pointer as an address. The DS0 and DS1 bits of the CTL register control the size of the array. The DSP module 16 allows a convenient way of handling data arrays as a FIFO. Only the appropriate number of the least significant bits of the DPTR are incremented on each access. The upper bits remain constant. Fig. 8 shows which bits are incremented. The rest remain constant.

0062Fig. 9A illustrates the operation of the data processing system 10 with the DSP module 16 executing the VCMAG command while the general purpose processor 18 executes a general purpose task.

0063As shown in Fig. 9A, bidirectional switches S that are responsive to control signals provided by the general purpose processor 18 are located on the internal bus 20 so as to permit configuration of a variety of communications paths among the DSP module 16, the general purpose processor 18 and the bus interface unit 24 (which, as stated above, provides access to external memory).

0064When the DSP module 16 is executing the VCMAG command, the DSP module 16 is isolated from the internal bus 20 so that the address generator 28 can retrieve operands for the VCMAG operation from the internal memory array 22 for both port Y and port D of the multiplier/accumulator 26. Isolation of the DSP module 16 in this manner allows the general purpose processor 18 to reference the external memory via the bus interface unit 24 to allow transfer of data and instructions between the general purpose processor 18 and external memory for simultaneous execution of a general purpose task.

0065Fig. 9B illustrates the bus configuration during execution of the VCMAD, VCMUL or VCMAC commands by the DSP module 16. In this case, the address generator 28 references an operand stored in the memory array 22 which is then provided to the Y port of the multiplier/accumulator 26. The address generator 28 also references a location in external memory which provides the second operand to the D port of the multiplier/accumulator 26. The general purpose processor 18 is isolated from both the internal memory array 22 and external memory.

0066Fig. 9C illustrates read and write operations by the general purpose processor 18 either to the Y register or the accumulator register A or to the internal memory array 22 of the DSP module. As shown in Fig. 9C, in this case, the general purpose processor 18 references the selected storage element as memory mapped I/O via the internal address bus and either reads or writes to the selected storage element via the internal data bus.

0067Addition information regarding the present invention is provided in National Semiconductor Corporation's Advanced Data Sheet, NS32FX16, High Performance Fax Processor, which is provided as Appendix A at the end of this Detailed Description of the Invention.

0068It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention, that the structure and methods within the scope of these claims and their equivalence be covered thereby.