Phase lock circuit and resulting frequency multiplier.

The invention relates to a phase-locked loop and to a frequency multiplier resultant.

The phase locked conventional circuit is commonly known by the acronym PLL (Phase Locked Loop). A PLL comprises: a phase comparator receiving the input and against a feedback signal; a filter receiving the output signal of the phase comparator; and a voltage controlled oscillator, commonly called VCO (Voltage Controlled Oscillator), which receives the filter output signal, outputs the PLL output signal and controls a against feedback loop for generating the against feedback signal applied to the phase comparator. The filter has a relatively low cutoff frequency relative to the frequency of the oscillator. The oscillator is generally a generator of free oscillations at a frequency analogically controlled to vary in a predetermined frequency band. Forming with this a PLL frequency multiplier by N by inserting a frequency divider by N in the feedback loop against.

The use of a PLL has several major drawbacks. The first disadvantage resides in the relatively long duration to obtain a stable phase lock on the desired operating frequency of the PLL. This drawback occurs when the switching of the PLL, or during a change of the desired operating frequency of the PLL. The duration of establishing a stable operation of the PLL is due to the presence of the feedback loop against and depends on the electrical characteristics of the PLL. The most important characteristic is the value of the cutoff frequency with respect to the desired operating frequency of the PLL. The duration setting is even longer than the cutoff frequency is low. However, the effectiveness of the phase lock is even better than the filter cutoff frequency is low. Therefore, we must concede a relatively long period to establish the correct operation of a PLL. This period is usually several milliseconds and corresponds to the passage of many data the PLL can not be treated.

A second disadvantage of the use of a PLL is its sensitivity to electric noise induced on the control analog signal of the VCO, which produce a temporary instability (jitter) of the output frequency of the PLL.

As a third drawback, the frequency band of operation of a PLL is relatively narrow for two reasons. On the one hand, the two input signals of the phase comparator does not have the same phase and the same frequency. The realization of a comparator broadband frequency and phase is very difficult and cumbersome in an integrated circuit. On the other hand, we have seen that the analog control of the oscillator is very sensitive to electrical noise. Therefore, the speaker noise in a wide frequency band too induce large variations in frequency in the output signal of the PLL operation and jeopardize stability.

The analog phase control oscillator of a PLL is also the cause of a fourth disadvantage. This disadvantage is particularly highlighted in the following example. Currently, the activation of a transmission link in an integrated product a relatively high heat dissipation circuit, of the order of 0.5 watts, for example. Therefore, if we want to incorporate a large number (eg 32) of links, it is only possible to activate a small number (4 or 8). One method is to put to sleep the other connections and wake them selectively to activate them. Since the alarm must be done in a very short time, it is necessary to digitally store all own settings to each link. The analog phase control of a PLL therefore forbidden rapid recovery bonds. This disadvantage is cumulative with the first-mentioned drawback.

The invention overcomes these drawbacks by presenting a phase-locked loop and a frequency multiplier having a brief period of establishment of proper operation, immune to electrical noise, applicable to a wide operating frequency band and provided with a numerical control.

The invention has a phase-locked loop comprising a phase comparator receiving an input signal and a signal against feedback, characterized in that the cons feedback signal is produced by a variable phase delay circuit of the input signal, whose delay is controlled by the output signal of the phase comparator.

This results in a frequency multiplier according to the invention, comprising a phase comparator receiving an input signal and a signal against feedback, characterized in that the cons feedback signal is produced by a delay circuit producing successive delays phase of the input signal controlled by the output signal of the phase comparator, and in that the multiplier output signal is delivered by a logical adder of the delayed signals.

The features and advantages of the invention are clear from the following description given by way of example and with reference to the accompanying drawings.

In the drawings:<ul><li>Figure 1 schematically illustrates a phase locked loop according to the invention;</li><li>2 shows various forms of signal-wave taken from the phase-locked loop shown in Figure 1 to illustrate its operation;</li><li>3 schematically illustrates a frequency multiplier according to the invention, resulting from the implementation of the phase-locked loop shown in Figure 1;</li><li>4 shows various forms of signal-wave taken from the frequency multiplier shown in Figure 3 in order to illustrate its operation;</li><li>5 schematically illustrates an embodiment of a frequency multiplier variant according to the invention; and</li><li>6 shows signal waveforms taken from the frequency multiplier shown in Figure 5 to illustrate the operation.</li></ul>

1 illustrates a preferred embodiment of a phase-locked loop 10 according to the invention. The circuit 10 comprises: an input terminal 10a; a phase comparator 11 having a first input terminal 11a connected to the input terminal 10a of the circuit 10, a second input terminal 11b and two output terminals 11c, 11d; a down counter 12 having two input terminals 12a, 12b connected respectively to the output terminals 11c, 11d of the phase comparator 11 and an output terminal 12c; a phase delay circuit 13 consists of eight delay elements 130-137 connected in series between both terminals 11a and 11b input from the phase comparator 11 and each having a control terminal connected to the output terminal 12c of the down counter 12; and an outlet 10b formed by the respective output terminals of delay elements 130-137.

The phase comparator 11 consists of two master-slave flip-flops 14 and 15 sensitive to rising edges. The flip-flop 14 has its data input connected to the input terminal 11a, its clock input connected to the input terminal 11b, and its output connected to the output terminal 11d. The bar 15 has, similarly, its data input connected to the input terminal 11b, a clock input connected to the input terminal 11a and its output connected to the output terminal 11c.

The input terminal 10a of the circuit 10 receives a frequency CL input signal data corresponding to a period T and usually constituting a clock signal. 2 shows an example of waveform of the input signal CL with respect to the time axis<u>t</u>. In Figure 2, it is assumed that the input signal CL is applied at time t = 0 of the input terminal 10a. 2 illustrates waveforms of the output signals CL0, CL1, CL2, CL3, ..., CL6 and CL7 of the respective delay elements 130, 131, 132, 133, ..., 136 and 137 of the circuit phase delay 13. CL0-CL7 signals are presented to the output terminal 10b of the circuit 10. the terminal 11b against feedback of the phase comparator 11 receives an FB against feedback signal consisting of the output signal CL7 of the delay circuit 13. the comparator 11 thus compares the phase of CL7 output signal with that of the input signal CL. Both terminals 11c and 11d output of the phase comparator 11 furnish an increment signal INC and a decrement signal December In response, the up-down counter 12 provides the control signal CTL applied to the delay elements 130-137. Each delay element comprises, conventionally, a predetermined number of unit delay cells. The control signal CTL represents a digital value, which is applied to each delay element for varying the delay time. The possible variation range of the delay time of a delay element during a period T of the input signal CL corresponds to a predetermined fraction 1 / P of the maximum extent of the variation time of a delay element. In other words, it takes a given integer number P of periods T to pass from one to the other extreme values ​​of the maximum extent of variation of the delay of an element.

In operation, the input signal CL is delayed successively by the eight delay elements 130-137. The eight successive delays produced by the elements 130-137 are equal and in principle divide the period T of the input signal CL. If it is exactly in practice, CL and FB signals (CL7) entering the phase comparator 11 and applied to the master-slave flip-flops 14 and 15 have the same phase and the same frequency. DEC and INC signals from the flip-flops 14 and 15 thus have the same logical value. The up-down counter 12 is not activated and leaves unchanged the control signal CTL. All CL0-CL7 output signals are properly phase shifted relative to each other and relative to the input signal CL by the same value T / 8. In practice, it determines a tolerance<u>m</u> phase shift between the input signal CL and against feedback signal FB = CL7. A phase shift in the margin<u>m</u> leave the INC and DEC unchanged and signals is not likened to a phase shift to correct. Margin<u>m</u> can be determined by the settling time of flip-flops 14 and 15 and / or the relative delays between data input signals and the clock input of each flip-flop, for example. The width of the margin<u>m</u> determines the precision of the phase comparison performed by the comparator 11. It is typically of the order of 50ps for a period T = 5 ns of the input signal CL.

If the cons feedback FB signal is in phase advance on the input signal CL, the decrement signal DEC logical 0 and the increment signal is 1. The up-down counter 12 is incremented so that the control signal CTL increases accordingly and equally the durations of the delays produced by the elements 130-137. On the contrary, if the reaction against FB-signal is behind the input signal CL, the increment signal INC is 0 and the decrement signal DEC to 1. The up-down counter 12 is decremented so that the control signal CTL will shorten the durations of the delays produced by the elements 130-137. Therefore, a phase shift beyond the tolerance<u>m</u> is corrected at all delay elements 130-137 to restore the desired phase shifts.

The digital phase control implemented in the phase-locked loop 10 according to the invention offers a significant advantage. If the CL input signal is interrupted, by the principle FB-reaction against signal is also interrupted. The flip-flops 14 and 15 of the phase comparator 11 no longer receive signal on their clock input and thus each retain the last state of the transmission. Similarly, the up-down counter 12 retains its last state and, therefore, the status of the delay elements 131-138. In other words, the circuit 10 according to the invention retains the last state of the transmission. It follows that the reappearance of the first edge of the input signal CL immediately produce the CL0-CL7 correct output signals if the frequency of the input signal CL has not changed. Otherwise, delays are set by the up-down counter 12 in the second cycle of the input signal CL, to produce the desired CL0-CL7 output signals. In conclusion, the time of establishment of the correct operation of a phase locked loop according to the invention may be zero, or at worst equal to the aforementioned number P of periods T of the input signal to pass between the two extreme values the extent of variation in the duration of each delay element. Therefore, the starting of the circuit according to the invention or the awakening of a transmission line in a very brief.

A second major advantage is the wide operating frequency band of the phase-locked loop according to the invention. The width of the strip depends primarily on the range of variable delays of each delay element 130-137, as will be apparent later with reference to the frequency multiplier according to the invention.

As another great benefit, the input signal CL and the signal-reaction against FB which are compared by the phase comparator 11 have in principle the same frequency. The structure of the comparator 11 can be very simple, like the one shown. Furthermore, the comparator can accommodate a wide band of operating frequencies. In summary, the invention solves all the above problems using a conventional PLL. Another advantage offered by a circuit 10 according to the invention lies in its adaptation to various forms of the input signal. In the example, the duty of the input signal can be arbitrary.

Numerous variants may be made to the circuit 10 described and illustrated. In particular, it is clear that the delay circuit 13 may be any number N of delay elements. At the limit, the delay circuit 13 may be made of one variable delay element. In this case, the circuit 10 may for example serve as a period T of a phase shifter input signal CL may vary in a very wide frequency band. In addition, the delay elements 130-137 may have a structure other than that described above. delay elements for example are known corresponding to the transit time of a logic gate. The crossing time is controlled by the current intensity which passes through the door, or by the value of the load applied to the door. In this case, the reversible counter 12 should be replaced by a suitable control device for the operation of such delay elements. The general principle of the invention is therefore that the delay circuit 13 is controlled by the output signal of the phase comparator 11. The advantage of the up-down counter 12 and delay elements 130-137 described lies in particular in their simplicity structure and functioning, reliability and adaptation to the phase comparator described. We have seen the benefits of this comparator. Of course, other structures are possible and can be better adapted to those of the control device 12 of the delay circuit 13.

3 illustrates a frequency multiplier 20 according to the invention implementing the phase-locked loop 10 shown in Figure 1. The multiplier 20 comprises simply the circuit 10, 10a whose input terminal is the terminal input 20a of multiplier 20 and the output 10b is connected to the input of a logic adder 16. the output of the adder 16 constitutes the output terminal 20b of the frequency multiplier 20. figures 3 and 4 illustrate a alternative use of the invention of the phase-locked loop 10. in this embodiment, the phase comparator 11 incorporates two master-slave flip-flops 14 ', 15' triggering on the falling edges of the input signal CL. The flip-flops 14 'and 15' are arranged in the same manner as the flip-flops 14 and 15 fires on the rising edges of the input signal CL. With this variant, the phase comparison is done every half-periods T / 2 of the input signal CL. Therefore, CL0-CL7 output signals are successively shifted with respect to each edge of the square of the input signal CL by a duration T / 16 produced by each delay element 130-137.

The adder 16 is made ​​conventionally of a mounting shaft of seven XOR gates 160-166 with two inputs. The four gates 160-163 respectively receive the output signals CL0 and CL4, CL5 and CL1, CL2 and CL6, CL3 and CL7. The gates 160-163 respectively deliver the 2CL0-2CL3 output signals shown in Figure 4. The 2CL0-2CL3 signals are square, having a frequency twice that of the input signal CL. The doors 164 and 165 respectively receive the output signals of the gates 160, 162 and 161, 163 and deliver the 4CL0 and 4CL1 signals shown in Figure 4. The 4CL0 and 4CL1 signals are square, having a quadruple the frequency of the signal 'CL input. Their application to the last gate 166 provides the 8CL0 output signal on the output terminal 20b of the multiplier 20. As shown in Figure 4, the signal 8CL0 is square and has a frequency eight times e to that of the input signal CL.

In practice, the realization of logic integrated circuits adder 16 must confer equal delay between the outputs of delay elements 130-137 and the output 20b of the adder. This constraint ensures the quality of multiple frequency. On the other hand, employment of the adder 16 as shown requires phase shifts of T / 16 between the signals CL and CL0-CL7. In the multiplier 20 receiving an input square signal, these offsets are simply produced by eight delay elements set to each half-period T / 2 after phase comparison in the comparator 11.

The frequency multiplier 20 enjoys all the advantages of phase-locked loop 10 and those of a logic adder. They include in particular the simplicity, reliability and adaptation to a wide band of frequencies. For example, with a period T CL input signal varying between 5 ns and 10 ns and with a delay circuit 13 of ten delay elements each capable of producing a delay varying from 250 to 500 ps, ​​it is possible to obtain to the output of a frequency multiplier according to the invention a frequency within a band of 1 to 2GHz.

In addition to the embodiments referenced in phase-locked loop 10 are added all the well known variants of the logical adder 16. It is also clear that the multiplication factor depends on the number N of delay elements in the delay circuit 13, the operation of the phase-locked loop 10 and the structure of the logical adder 16. for example, one could remove the two flip-flops 14 'and 15' in the phase comparator 11 and proceed to the phase comparison in each period T after two passages in elements 130-137. If the input signal CL is not square, it could for example have sixteen delay elements in the circuit 10 of Figure 1, or add an interface between the logic circuit 10 and the adder 16 in the frequency multiplier 20.

5 schematically illustrates a frequency multiplier of the embodiment 20. All components have the same structure as that described above with reference to Figure 3. In other words, the locked phase ciruit 10 provides the adder logic 16 all output signals of the eight delay elements 130-137. The only difference of the embodiment with that shown in Figure 3 is the addition of a selection device such as a multiplexer 17 and in adaptation to connections of multiplexer between the delay elements 130-137. The multiplexer 17 provides the signal against feedback FB to the input of feedback against the phase comparator 11. The inputs of multiplexer 17 are shown schematically by switches connecting delay elements with each other and associated with the line providing the signal against feedback FB. The advantage of multiplexer 17 is to vary the multiplier the multiplication factor of frequency 20. In the example shown and illustrated in Figures 5 and 6, the multiplexer 17 holds the connection of the first six delay elements 130-135 for sample the signal against feedback FB to the output of the element 135 (FB = CL5). The delay elements 136 and 137 are separated by the multiplexer 17, but their respective outputs are connected to the adder 16 and provide it with a predetermined fixed logic value. 6 illustrates the waveforms of signals taken under these conditions the frequency multiplier 20. CL0-CL7 signals are successively delayed by the duration T / 16 with respect to the input signal CL. The gates 160-163 provide intermediate signals XCL0-XCL3 the gates 164 and 165. Compared to the frequency of the input signal CL, the output signals of 3CL0 and 3CL1 doors 164 and 165 is three, and that of the signal 6CL0 the terminal 20c is six times larger. Of course, the skilled person has other embodiment of a device for selecting variants for obtaining a desired multiplication factor of a frequency multiplier according to the invention.