Digital video mixer control signal.

Background of the Invention

0001The present invention relates to the mixing of two signals, and more particularly to an improved digital video mixer that adds a correction term to provide full mixing range while satisfying all mixing constraints.

0002A mix between two signals, A and B, with the mix proportion controlled by a variable K is mathematically defined as:<maths id="math0001" num=""><img file="EP0430701A2_D0001.tif" /></maths>where K is a variable having a range between 0.0 and 1.0 inclusive. Furthermore the mix result should meet the following constraints :<maths id="math0002" num=""><img file="EP0430701A2_D0002.tif" /></maths><maths id="math0003" num=""><img file="EP0430701A2_D0003.tif" /></maths><maths id="math0004" num=""><img file="EP0430701A2_D0004.tif" /></maths>

0003In one prior art method for the K variable 0.0 is defined as 0 and 1.0 is defined as 2^(n-1). Therefore when K = 0, (1.0 - K) = 2"(n -1) and when K = 2"(n - 1), (1.0 - K) = 0. K values in the range 2^(n - 1) + 1 to 2^n -1 are not valid. For eight-bit signals (n = 8) 0.0 is 0.0000000 binary and 1.0 is 1.0000000 binary. K values in the range 1.0000001 to 1.1111111 binary are not valid. Thus approximately one-half of the available range of K is not valid. This implementation, as shown in Fig. 1, satisfies all of the constraints, but the loss of resolution due to the unused values of K results in coarser mix steps.

0004Another prior art method is shown in Fig. 2 where for the K input 0.0 is defined as 0 and 1.0 is defined as 2^n -1. When 1.0 is defined as 2^n -1, (1.0 - K) is equivalent to \K. Therefore when K = 0, (1.0 - K) = 2^n - 1 and when K = 2^n - 1, (1.0 - K) = 0. For eight-bit signals (n = 8) 0.0 is.00000000 binary and 1.0 is.11111111 binary. This implementation uses all of the available K range, but the results do not satisfy all of the constraints. For example when A = 11111111. binary, K =.11111111 binary and \K = .00000000 binary, A ^*K + B ^*\K should equal A. The B ^* \K term equals zero, but the A ^* K term equals 11111111. ^* .11111111 = 11111110.00000001 which, when truncated to eight bits, becomes 11111110. rather than 11111111.

0005Thus what is desired is an improved digital mixer for mixing two signals according to a variable K that uses the full range of K while meeting all desirable mixer constraints.

Summary of the Invention

0006Accordingly the present invention provides an improved digital video mixer that adds a correction term to assure that the full variable K range is used and all desirable mixer constraints are met. Specifically the correction term corrects the mix result to satisfy the desirable constraints. The corrected mix is defined as :<maths id="math0005" num=""><img file="EP0430701A2_D0005.tif" /></maths>The D term represents some form of rounding function according to the desired result.

0007The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.

Brief Description of the Drawing

0008<ul id="ul0001" list-style="none"><li>Fig. 1 is a block diagram of a first prior art mixer.</li><li>Fig. 2 is a block diagram of a second prior art mixer.</li><li>Fig. 3 is a block diagram of an improved digital mixer according to the present invention.</li><li>Fig. 4 is a block diagram of a prior art single multiplier mixer.</li><li>Fig. 5 is a block diagram of an improved single multiplier digital mixer according to the present invention.</li></ul>

Description of the Preferred Embodiment

0009Referring now to Fig. 3 a conventional mixer, such as that shown in Fig. 2, has a first multiplier 12 to which a first signal A and a mixer control variable K are input. A second multiplier 14 has a second signal B and the complement of the mixer control variable \K as inputs. The outputs of multipliers 12, 14 are summed by a first adder 16 to produce a first mix output according to the prior art. The first mix output, however, is input to a second adder 18 and to a sign extension right shifter 20. The output of the sign extension right shifter 20 is (A ^* K + B ^* \K)/2^n where the parenthetical term is the first mix output input to the shifter and the divisor term represents right shifting by n bits so that for 011111111.00000000 binary (MSB is sign) sign extended right shift of eight places and truncated to seventeen bits (sign plus sixteen bits) becomes 000000000.11111111 binary. This output also is input to the second adder 18. The output of the second adder 18 is input to a third adder 22 together with a correction signal D. The output of the third adder 22 is a final mix output signal that uses the full range of K while satisfying all the desired mixer constraints and satisfies the equation :<maths id="math0006" num=""><img file="EP0430701A2_D0006.tif" /></maths>

0010The correction signal D is dependent upon the desired result. For dithered rounding to an N-bit result D is a random, or pseudorandom, number distributed from<maths id="math0007" num=""><img file="EP0430701A2_D0007.tif" /></maths>For a truncated result<maths id="math0008" num=""><img file="EP0430701A2_D0008.tif" /></maths>And for a result rounded up if the fractional portion is greater than or equal to one-half<maths id="math0009" num=""><img file="EP0430701A2_D0009.tif" /></maths>The only requirement for D is that it produce the desired result.

0011Another prior art mixer that uses a single multiplier is shown in Fig. 4 and implements the equation<maths id="math0010" num=""><img file="EP0430701A2_D0010.tif" /></maths>This prior art single multiplier mixer may be modified to incorporate the present invention as indicated in Fig. 5. A subtracter 24 has as inputs the two signals A and B. The output of the subtracter24 together with the mixer control variable K is input to a multiplier 26. The output of the multiplier 26 is input to a first adder 28 and to a sign extension right shifter 30, the output of which also is input to the first adder. The second signal B is concatenated with the correction signal D by concatenation circuit 32 to form signal E, where B occupies the integer portion and D occupies the fractional portion. Concatenation (a connected series) is a special case of addition where nonzero terms do not overlap so that AB : CD (concatenation) is equivalent to AB00 + OOCD = ABCD. The output of the concatenation circuit 32, E, and the output of the first adder 28 are input to a second adder 34, the output of which is the desired mix output.

0012Thus the present invention provides an improved digital mixer that uses the full range of a mixer control variable while satisfying desired mixer constraints by adding a correction term to the mixer equation to correct to the desired constraints.