Video recorder for recording a video signal comprising picture information and auxiliary digital information in time-multiplex.

The invention relates to a VCR for recording a video signal containing image information and additional digital information in time division multiplex.

Such video recorders are described in European Patent Application 87111866.7 from 17.08.87 and 89112523.9 from 07.08.89.

In the video recorder known from the European patent application 87111866.7 a time division multiplexed transmitted within each line with the image information data packet by means of a time gate is separated from the video signal, formed in addition to each data packet a time-delayed version, subjected to all the data packets of a multi-level coding and the associated one line of the video signal , multiply the information to a frequency modulation mutually time-shifted recorded on different oblique tracks of a magnetic tape.

Also in the video recorder described in non-prepublished patent application 89112523.9 a new version is made to each data packet. This additional version of a data packet is recorded in contrast to the aforementioned application in time division multiplex with the data packet and the image information of a previous line. Also, this recording takes place after previous frequency modulation of the data packets.

In the aforementioned video recorders can the loss of a data packet - for example due to dropouts - recorded on a different slant track additional version this data packet are used in the sense of Dropoutkompensation.

However, the disadvantage is the need for the aforementioned video recorders, having to produce and record an additional data packet.

Furthermore, it is known from the journal "EBU Review Technical", no. 227, February 1988, section 4.4, known in the vertical blanking intervals of a satellite television signal called DATV ( "<u>d</u>igitally <u>a</u>ssisted <u>t</u>ele<u>v</u>to transmit ision ") signals These signals included in the transmitter generated information about the motion content and the coding mode of the transmitted television pictures which -., depending on the motion content -. be coded differently in the transmitter in the receiver, the transmitted DATV signals to restore the original image used will.

Further, in the magazine "Radio Show", No. 18, 1989, pages 44 to 48 of the insert-part radio show / specialty, described a HD-MAC video recorder. The cited reference can be seen that at the beginning of each line and digital data in the vertical blanking interval for decoding the HD-MAC signal required DATV data are transmitted in an HD-MAC signal. In particular is to be noted that the error rate of the reproduced digital signal certain limit values ​​must not exceed if one wants to obtain a good picture quality. It is therefore proposed to provide additional error protection measures in the recording of digital data. How this is done in detail, but is not described in the cited reference.

Starting from the aforementioned prior art, the invention has the object to further develop a VCR with the stated in the preamble of claim 1 features, as is known from European Patent Application 87111866.7 such that a reliable recording and playback is assured of digital additional information, without the production and recording of an additional version of the digital additional information is necessary.

This object is achieved with a VCR that specified in the preamble of claim 1 by the kind indicated in the characterizing part of claim 1. Advantageous embodiments of the invention result from the dependent claims.

The advantages of the invention are, in particular, that can be adjusted by the digital recording of the digital additional information about driving error protection expenditure of the bit error rate of the video recorder and / or the importance of the digital additional information. Since the delay, the subject within the error protection procedure, the digital additional information is compensated by delaying the image information reaching for recording digital additional information are again in the correct temporal relationship to the image information. With multiple overdubs of the recorded signals therefore occurs not increasing temporal offset between the image and the digital additional information. For a better understanding is to be noted that the caused by the fault protection procedure increasing the data quantity is matched by a exercise ahead of error protection procedure clock rates increase in the time frame of the video signal. Further advantages of the invention will be apparent from the explanation of embodiments with reference to FIGS.

Show it<ul><li>- Fig. 1 the structure of a frame of an HD-MAC signal,</li><li>- Fig. 2 a block diagram for explaining the recording side signal processing,</li><li>- Fig. 3 a detailed block diagram of Fehlerschutzcoders 16 of Figure 2,</li><li>- Fig. 4 and 5 Diagrams for explaining the operation of the interface circuit 15 and the Fehlerschutzcoders 16 of FIG. 2 and</li><li>- Fig. 6 is a block diagram for explaining the reproducing-side signal processing.</li></ul>

1 shows the structure of a frame of an HD-MAC signal. The frame shown consists of 625 lines and has a duration of 40 ms. The first part of each of the lines 1-624, a digital data burst or a digital data packet for example, each 198 bits is transferred to duobinary coding, which contains inter alia a sound information. In the second part of each of the lines 1 to 20 and 313-333 are also called in duobinary coding. DATV ( "<u>d</u>igitally <u>a</u>ssisted <u>t</u>ele<u>v</u>transmitted ision ") data containing information generated in the transmitter on the motion content, and the encoding mode of the transmitted television pictures which are coded differently depending on the motion content in the transmitter. In the second part of each of lines 21 to 312 and 334-624, an analog video signal transmitted, which each consist of a time multiplexed chrominance and luminance information. the line 625 of the frame shown contains in duobinary coding data for synchronization and for the identification of the HD-MAC frame signal, for example a frame synchronization block, the date and time, an indication for the satellite channel and the construction of the packet signal. This transmitted in line 625 information includes an error correction code or are secured by multiple transmission.

In the lower part of Figure 1 the division of the duration of the lines 21 to 312 and 334 to 624 is shown on the transmitted signal components within these lines. It will be appreciated that within each of said rows, a digital data burst of 10.2 microseconds duration, a clamping gap of 1 microseconds duration of 18 microseconds duration chrominance and luminance information is of 34.8 microseconds.

2 shows a block diagram for explaining the recording side signal processing. The input E of the arrangement shown is supplied to a HD-MAC video signal whose fundamental structure Wirde described in FIG. 1 This signal is a first time gate 1 is supplied, which has the task to separate the 21-312 and 334-624 transmitted in the second part of the line analog video signal and the data transmitted in the line 625 signals from the HD-MAC signal. Furthermore, the HD-MAC input signal is fed to a second time gate 2, which has the task, in the first part of rows 1 to 624 and in the second part of the rows 1 to 20 and 313-333 digital data transmitted from the HD-MAC separate signal. Further, the HD-MAC input signal is supplied to a clock generator 3, which is derived from the HD-MAC input signal a clock signal CK, switch control pulses S1 and S2 and switching signals U1 ..... U4.

The signal available at the output of the time gate 1 is converted in an analog / digital converter 4 into a digital signal and then fed to a delay stage 5th The delay stage 5 has the task to compensate for that delay, in response to the error protection procedure that is explained in greater detail subject to digital data.

The successive lines of the output signal of the delay stage 5 are alternately Save 7 and 8 where it is separated time-expanded, as it is basically known from the aforementioned European patent applications 87111866.7 and 89112523.9. The output of memory 7 is reset converted in a digital / analog converter 9 into an analog signal subjected to a 10 Preemphaseschaltung a Vorverzurrung and supplied to a frequency modulator eleventh The frequency modulated signal is supplied to the contact b of a switch 20th The output signal of the memory 8 is converted back into a digital / analog converter 12 into an analog signal subjected to a pre-distortion Preemphaseschaltung 13 and supplied to a frequency modulator fourteenth The frequency modulated signal is supplied to the contact b of a switch 24th

The available in duo-binary coding on the output of the second time gate 2 digital data is converted to a converter 6 into a binary signal. The binary signal is supplied to an interface circuit 15th On the output of this interface circuit, the digital data in blocks with increased data rate provided, so that within the foreseen to transfer a block of time gaps are included in the - are used check words, sync words and address words - as will be described below.

To this end, the interface circuit 15 to a not shown memory in which is written the binary signal having a first clock rate in the row direction and read out at a second clock rate which is greater than the first clock rate, in the column direction. By reading in the column direction the binary signal to the subsequent Fehlerschutzcoder 16 is so provided that the outer coder 161 - is below described - can make the check word Q, without the need for a further caching.

Such a data block for the first part of each of lines 1 to 624 transmitted digital data is shown in FIG. 4 It includes, for example, 52 lines. The first part of each of these 52 lines transmitted digital data is compressed in time such by the clock rate conversion as described above, that at the beginning of each data block space Pl 1 for two synchronous words and possibly two address words and at the end of each data block and in the last 4 of the 52 lines of data block space for check words is created.

Such a data block for the second part of each of lines 1 to 20 and 313 to 333 transmitted DATV data is shown in FIG. 5 It includes, for example, 20 lines. The second part of each of these 20 lines transferred DATV data are compressed in time such by the Taltratenwandlung above that at the beginning of each DATV data block space Pl 2 for two synchronous words and possibly two address words and the at the end of each data block and in the last 6 20 lines of the DATV-block space for check words is created.

The structure and operation of the Fehlerschutzcoders 16, in which the data blocks generated in the interface circuit 15 are provided with check words to form a Reed-Solomon product code is shown in FIG. 3 The Fehlerschutzcoder 16 shown includes an outer coder 161, a memory 162, an inner coder 163, a switch 164, a delay circuit 165, and another switch 166. In the outer coder 161, each column of the column direction from the memory to the interface circuit 15 read data block with a first check word Q provided that consists in the presence of a DATV data block, for example, of 6 bytes and in the presence of a data block from the first part of the lines 1 to 4 624 bytes. The signal thus obtained is written in the column direction into the memory 162 and read out again from this in the row direction. Each line of the read-out signal is provided in the inner coder 163 with a second check word P, which for example consists of 4 bytes. The output of the inner coder 163 is a switch 164 is supplied, which is when the output of the inner coder 163 is a block of data from the first part of rows 1 to 624 of the HD-MAC signal, b is in the switching position, so that the output of the inner coder 163 via the switch 164 and the switch 166, which is also located in the switching position, the output of 16 is fed Fehlerschutzcoders. Wherever the output of the inner coder 163, however a DATV data block, so is this, via the switch 164, located in the switching position a, the delay circuit 165 and the switch 166, which is also located in the switching position a to passed the output of Fehlerschutzcoders 16th The delay time of delay circuit 165 is the difference between those delays, which the data blocks as shown in FIG 4 and FIG. 5 are within the error protection coding. Thus, the data blocks are at the output of the switch 166 again at the correct time available. Since - as it Wirde described above - the check words P and Q depending on whether the currently to be processed data block is a data block from the first part of the lines 1 to 624 or a DATV data block must be formed by a different number of data bytes, are the outer coder 161 and inner coder 163 switching signals U1 and U2 supplied, which specifies the number of data bytes for a check word is generated. These switching signals are - as is indicated in Figure 2 - the clock generator 3 generates. The changeover to the switches 164 and 166 necessary switching signals are generated in the clock generator. 3

By selecting different block sizes and Prüfwortlängen for the transferred in the first part of the line data package and the DATV data the DATV data a stronger error protection is given as the transferred in the first part of the line data packet. This reflects the fact that in an eventual loss of DATV data in record-playback channel the necessary on a screen for displaying the reproduced signal regeneration of the HD-MAC signal due to the lack of information on the movement of content and the coding mode no longer would be possible, as already impossible any lost bytes regeneration. In contrast to this lost information can be concealed by interpolation in the transmitted during the first part of the line data packet.

The output of the Fehlerschutzcoders 16 is an address signal insertion circuit 17 is supplied, in which in the beginning of each line of each data block created gap two address words are keyed.

To the output of the address signal insertion circuit 17, a multiplexer 18 is connected, are divided into two channels by means of which the recording data signals and address signals as follows:

The odd bytes are, disposed in the first recording channel 8 / 10th of the channel encoder 19 is supplied, as is known, for example from DE-PS 2,830,924th In the output of the 8/10-Kanalcodieres 19, a synchronous word is strobed into a Synchronworteintastufe 20 in which at the beginning of each line of each data block created gap further. The output of the Synchronworteintaststufe 20 is supplied to the contact a of the switch 21st

The switch 21 which is controlled by the generated in the clock generator 3 switching signal S1 in the time intervals in which there are digital data, into the switching position a, and is controlled in time intervals, are present in which frequency-modulated signals, into the switching position b, thus provides at its output a time-division multiplex signal which consists of a code error protection is provided and digital data of frequency-modulated signals. This time multiplexed signal is amplified in an amplifier 22 and recorded by a magnetic head unit 23rd

The even numbered bytes are a channel arranged in the second recording 8/10-channel encoder 24 is supplied. In the output of the 8/10-channel encoder 24, a synchronous word is strobed into a Synchronworteintaststufe 25 in which at the beginning of each line of each data block created gap further. The output of the Synchronworteintastestufe 25 is supplied to the contact a of the switch 26th

The switch 26 which is controlled by the generated in the clock generator 3 switching signal S2 in the time intervals in which there are digital data, into the switching position a, and is controlled in time intervals, are present in which frequency-modulated signals, into the switching position b, thus provides at its output a time-division multiplex signal which consists of a code error protection is provided and digital data of frequency-modulated signals. This time multiplexed signal is amplified in an amplifier 27 and recorded by a magnetic head unit 28th

6 shows a block diagram for explaining the reproducing-side signal processing. The reproduced from a place in the first playback channel 30 magnetic head unit 31 signals are subjected to a circuit 32 of amplitude and phase correction. The output of the circuit 32 is supplied to a first signal in which the reproduced digital data is processed and fed to a second signal path, in which the reproduced frequency-modulated signal is processed.

In the first pathway, the reproduced digital data will first be taken to be assigned to a decision logic 33, in the reproduced signal clearly "HIGH" and "LOW" level. a clock signal is regenerated and a channel decoder 35 is supplied, which continues to be the output of the decision logic 33 is supplied by a frequency and phase locked loop 34 from the reproduced digital signal from the output of the decision logic 33rd In the channel decoder 35 for recording a mutually conducted 8/10 channel coding inverse operation is performed. Further, the recording-provided inserted in the signal synchronizing word is detected and 37 supplied via a line L 3 of a circuit for Zeitfehlerkorrekktur to compensate for the resulting in the recording / reproducing channel time errors and to compensate for propagation time differences between the two recording / playback channels in the channel decoder 35th For this purpose, the circuit 37 also receives via a line L 2, the output signal of the channel decoder 35 and a reference clock signal supplied, which is generated in a crystal oscillator 45 whose output signal is fed via a frequency divider 46th The output of the time error corrector 37 is supplied to a circuit node A.

The arranged between the channel decoder 35 and the time error corrector 37 address detection circuit 36 ​​is advantageous in normal Viedergabebetrieb when major disruptions occur, and for example, when Schlaufbetrieb, in which the magnetic tape is transported with increased speed and in which the reproduction head crosses several tracks.

In these cases, it can be ensured by means of the detected address information, the reproduced data from the tape information can be stored to the correct locations of the memory of the time error corrector 37th

In the second pathway, the reproduced frequency-modulated signals are applied to a frequency demodulator 39 and frequency-demodulated there. The frequency-demodulated signal is converted in an analog / digital converter 40 into a digital signal. This is a memory 42 for time compression. The necessary for writing the digital signal into the memory 42 write clock signals are gewonne in a clock signal generator 41, which is connected to the output of the analog / digital converter 40 or the output of the demodulator 39 either, and generates from the signals supplied Taksignale CK and horizontal sync pulses H , Further, the memory 42 the reference clock signal supplied, from which the read clock signal is generated for the memory 42nd DasAusgangssignal the memory 42 is a circuit node B supplied.

At circuit nodes A processed in the second reproducing channel 50 digital data are created further via a signal line L 5 so that the error protection decoder coupled to the circuit node A 38, a signal is supplied which corresponds to the signal obtained at the output of the recording-side Fehlerschutzcoders sixteenth Furthermore, the error protection decoder reference clock signal is supplied to 38th The error protection decoder 38 is similar in structure to the Fehlerschutzcoder shown in Figure 3 16 and is used to using the recording side generated check words to check the reproduced digital data on resulting in the recording / reproducing operation error and this - if possible - to correct.

If one uses the recording side generated in the inner coder 163 check words P exclusively for error detection and generated in the outer coder 161 check words Q solely for error correction, as is achieved by means of the selected Prüfwortlängen that in the case of transferred in the first part of the row 1-624 data packets 4 of 52 bytes are available for error correction, while in the case of DATV data 6 are available from 20 bytes to the error corrector.

The output of the error protection decoder 38 is an interface circuit 48 is supplied, whose job it is to make the recording-side gap generation and clock rates increase again undone. The Aysgangssignal the interface circuit 48 is converted into a binary / Duobinärwandler 48 back into a duobinary signal and applied to the contact a of a switch 47th

To the circuit node B processed in the second reproducing channel 50 frequency-modulated signals recorded are created further via a signal line L6 so that the connected to the circuit node B delay circuit 43 is supplied with a signal which corresponds to the signal obtained at the output of the recording-side delay circuit fifth The delay circuit 43 has the task to delay their signals supplied such that that delay, the subject within the error protection procedure, the digital data is compensated and thus are video signal and digital data at the correct time available. The output signal of the delay circuit 43 is converted back into a digital / analog converter 44 into an analog signal. This is supplied to the contact b of the switch 47th

The switch 47 is alternately transparent to the on contact a fitting digital signals and the contact b incoming signals so that the output of the switch 47, a time-division multiplex signal is obtained, as shown in FIG. 1