Asynchronization device for a digital signal.

The invention relates to a synchronizer for a digital signal according to the preamble of claim 1.

In digital systems with high bit rate must be used because of the maturity of digital devices special synchronization concepts. From the article "High speed (140 Mbit / s) switching techniques for broadband communications" (Zurich, Switzerland, 11-13 March 1986); Boettle, D .; Small, M .; Professional, A., ed .; Hartmann, R., ed .; . Stand Elektrik Lorenz AG, Stuttgart, Germany; IEEE, Zurich, Switzerland, PP. 97-100, (Conference Paper) describes a synchronization device, wherein the digital signal is routed via delay elements. A panel of three flip-flops phase detector operating with mutually shifted clock signals is supplied from the output of the delay line, the data signal. If the step envelopes within a formed by the delayed clock signals synchronizing window, so the delay time of the digital signal is changed accordingly. The disadvantage here is that the synchronization can be limited for plesiochronous signals and not used for asynchronous signals since an adjustment to the phase of the digital signal by the delay line length is limited. In addition, a control logic come the criteria of the phase detector with different clocks.

The object of the invention is to specify a suitable for plesiochronous and asynchronous data signals with high bit rate synchronization.

This object is achieved by the features specified in patent claim 1.

Advantageous embodiments of the invention are specified in the subclaims.

Advantageously, in the synchronizer according to the invention that, even when caused by frequency differences between the received digital signal and the internal system clock changes the phase no data loss occurs is.

A further advantage is that no delayed clock signals are used and thus the complexity of the control logic is less. This is also achieved in that when switching between foreground and background sync the data bits output are mutually always delayed by one bit length.

By parallelizing or plug the output data can be further processed.

Also advantageous is averaging or filtering the output from the phase detection criteria.

The invention is illustrated by a block diagram, and of exemplary embodiments.

Show it:<ul><li>Figure 1 shows a block diagram of the synchronization,</li><li>Figure 2 is a circuit diagram of the phase detection and the control logic,</li><li>Figure 3 is a timing diagram for phase detection,</li><li>Figure 4 is a diagram for explaining the control logic,</li><li>Figure 5 shows an embodiment of the delay device,</li><li>6 shows a second embodiment of the delay device,</li><li>7 shows a data selection circuit with delay elements,</li><li>8 shows a data selection circuit with a serial-parallel converter and</li><li>Figure 9 a corresponding time chart.</li></ul>

1 shows the principle of the synchronization is shown. A delay device 2 is fed via its input 2₁ the received digital signal DE. The signal outputs 2₂ and 2₃ are each connected to a phase detection 6 and 7 respectively. The data outputs 6₂ and 7₂ phase detections are performed on an output device 8, at the output of the output data DA 8₃ be issued. The output at the outputs 6₃ or 7₃ phase position criteria are routed to a control logic 9, by which the delay means 2 is controlled.

Each phase detection 6, 7 provides via the control logic 9 ensure that the digital signal is in each case delayed so that the data bits are sampled as ideally as possible in the center. Both phase detections work here independently. This is mainly necessary because of the tolerances of the delay device. The synchronizer includes gewißermaßen a foreground synchronization, consisting of a delay line of the delay means 2, the phase detection 6 and parts of the control logic, and a background synchronization, consisting of a second independently controllable delay line of the delay means 2, the phase detection 7 and parts of the control logic. 9 Both synchronizers operate independently, however, before a switch from foreground to background synchronization always so that the delay device delivers them by one bit length differently delayed digital signals.

Before discussing the operation of the synchronizer more precisely, only the phase detections and the essential parts of the control logic will be explained in more detail.

In Figure 2 both phase detection and the essential elements of the control logic are shown. The fore-phase detection 6 essentially consists of three D-flip-flops 65, 66 and 67, whose clock inputs CE is supplied via a connection point 10, the system clock signal CT (chip clock). From the first output 22 of the delay means 2, the delayed digital signal - now referred to as foreground data DV - the data input D of the first D-flip-flop 65 directly and the data inputs 66 and 67 a via a delay element 63 and via still further D-flip-flops further delay element 64 are each supplied with a delay time "t". The multiple phase-shifted digital signal DV, DV2, DV3 delivers at the outputs of the D flip-flops, the phase position criteria, V1 to V3, which are fed to an evaluation logic 93 whose outputs 63 (Figure 1) connected to control inputs U, D of a first forward backward counter 92 are. The outputs 92₁ of the VR-counter controlled by a decoder 94 and whose outputs 94₂ a delay line of the delay device. 2

The background-phase evaluation is constructed. The D-flip-flops are designated by 75 to 77, the delay elements 73 and 74 and the phase position criteria H1 to H3. These are performed in accordance with a second evaluation logic 96 whose outputs are connected to the respective control inputs of a second up-down counter 95th Its outputs 95₁ control via a second decoder 97, whose outputs are designated 97₂, for example, a second delay line of the delay device 2. Both decoder outputs 94₂ and 97₂ are the starting 9₃ the control logic.

In this embodiment, only the positive edges of foreground data and background data for the sake of a simplified representation rated and also the forward-backward counter is only affected by these.

In Figure 3, once delayed foreground data DV2 are presented at the output of the delay element 63 in the second row of the timing chart. The edge jitter was drawn dashed. Jitter foreground data are scanned by the system clock signal CT at the center. The instantaneous foreground data DV and the twice delayed foreground data DV3 be scanned properly. If all criteria phasing V1 to V3 match is therefore assumed that a proper synchronization. However, if the frequency of the received data signal is, for example, lower than the frequency of the system clock signal, then move the focus data to the internal system clock signal. The corresponding data signals are marked with an *. This is at the twice delayed foreground data DV3 * nor the previous data bit B0 scanned while has already been adopted in the D-flip-flops 65 and 66, the following data bit B1. The output at the output of the D-flipflop 66 6₂ data bit is sampled while still correctly; However, the probing is no longer in the middle of a bit. In this case must be synchronized, that is the delay in the delay device to be lower.

In contrast, when the phase of V1 and V2 criteria no longer coincide, must be increased in accordance with the delay.

By mutually phase shifted foreground data (based on the output as a regenerated digital signal sampled foreground data DV2) is spanned a synchronizing window, so to speak. If there are shifts in the edge of the foreground data DV2 - in this example - more than 25%, so the edge falls within the synchronizing window and causes a change in the delay time.

The corresponding control signals are supplied by the evaluation logic 93rd Is V1 equal to V2, a control signal VU is (up) given that on the control input U of the up-down counter 92 (VR-counter) is guided and led him 'to count the value 1 upwards and thus to increase the delay time; V2 is equal to V3, a signal VD is (down) if that is passed to the input D of the VR-counter 92, causing it to devalue by counting down the delay time. In the exemplary embodiment is a 4-bit counter whose outputs 92₁ controls the delay means via the decoder 94th

The positive edge of the evaluated signal bits ensures here via the delay element 91 for the timing of the VR-counter.

In the same way sync with the background phase detection 7. This is done there is one special. The delay means is formed so that the delay time also taking into account tolerances of the blocks comprises at least the duration of a signal bit. The foreground synchronization works gewißermaßen as master synchronizing. Only when the counter position of the VR-counter 92 is one of the extreme values ​​0 or n approaches, ie, the delay is the minimum or the maximum value approaches, for example, from the count AV1 or AVn-1 on the background synchronization switched (Figure 4 ) and their background data DH instead of the foreground data DV outputted. The delay means is in this case controlled so that the delay time between foreground and background data a difference of one bit. This control may be effected for example by a picture taken from the dependent count of the first counter 92 VR-loading the second VR-counter 95 by a load address LAH and a load pulse 1H. When a count 1 of the first VR-counter 92, the second VR-counter 95 is set to the count n-1 and vice versa. Or the second VR-counter is at a count AV = 1 to a count of at least AH = AV + 1 = 2 better AH = AV + n / 2 set and must then count up until the background data scanned correctly. the count of the first counter 92 VR contrast Located 11 (Figure 2) in the second region of the reading of the second VR-counter 95 is correspondingly reduced until it earlier background data DH scans correctly to a bit duration. In another "run" the foreground synchronization then the background synchronization runs in the same sense. Here, numerous circuit variants are possible.

As apparent from the above description, the fore-phase detection works prioritized only when a secure Datenbitmitte was found by the fore-phase detection, the phase detection of the background synchronization begins to adjust. After a switch to the background synchronization of the first VR-counter 92 is set according to the counter address of the second VR-counter 95, this is the count - called background address HA - as load address foreground LAV on the corresponding load inputs and a load pulse LV from first VR-counter 92 taken. The background phase detection needs again only to be active when the Zählerrstand - Foreground address AV referred - the first VRZählers one of extremes approaches. Since it is data signals of high frequency stability generally, switching between foreground and background synchronization occurs relatively infrequently. Therefore, it is possible to supplied by the evaluation logic control signals or to filter means. The easiest way to do this is to increase the VR counter. In the upward and downward data jitter criteria VU and VD are averaged and will be a greater difference resulting in a Synchronisierschnitt. A digital filter leads to even better results. Then more than three flip-flops can be used in the recognition phase, form the synchronizing window with different valency, in order to achieve a more accurate sampling of the digital signal in the Bitmitten. The criterion VM, which indicates that the sampling was carried out correctly, can also be used to control the extended VR-counter or the digital filter.

It is to be understood that the width of the synchronization window, and the time constant for adjusting the delay means are adapted to the system conditions. Likewise, of course at a resynchronization of the mean value of the counter can be set, etc.

An embodiment of the delay device is shown in FIG. 5 The digital signal is supplied to a series circuit of inverters IN0 INn. From the output of each inverter a further inverter IN00-INn0 leads to the common-connected inputs of two transmission gate TG, whose outputs are switched to two different bus line BL1, and BL2 and compared with the outputs 22 and 23 of the delay device by amplifiers V1 and V2 are decoupled. The inverters used as delay elements.

The running time is set by each the appropriate transmission gate is turned on in each case one bus line, while others will be blocked. Although this delay is made with a small circuit required, but it must all transmission gates are driven.

In Figure 6, the delay means is implemented by two delay lines. Upper one input inverter INe the digital signal is initially decoupled. The output of the input inverter inverters IN11-IN21 and IN1n-IN2n are on. In series with each of them is a transmission gate. In addition, delay elements L11-L1n are provided, each connected in another transmission gate in series. The inverter IN11-IN1n are each connected via their assigned a transmission gate to the input of this delay elements L11-L1n. In the same manner, the inverter IN21-IN2n are turned on at a second series connection of delay elements L21-L2n. The delay elements L11 and L21 are in this case the outputs 22 and 23 the next, and the delay elements L1n and L2n farthest. Although this circuitry requires more components, but have fewer loads are driven. Depending on the technology, the inverters can optionally be IN11 and IN21, IN12 and IN22, etc. replaced by a single inverter. The delay elements L11, L21 and the inverter IN11 and IN21 can be optionally dispensed with entirely. Because of component tolerances is the

The regenerated by sampling digital signals are identical to the phase angle criterion V2 or the phasing criterion H2 in the background phase detection. Of these digital signals is one each selected by the data selection circuit 8 for distribution or further processing. The choice of course, must be such that the bits of the output signal DA are in the correct order. To this end, numerous circuit variants are possible, two of which will be explained in more detail.

A suitable for synchronous data signals data selection circuit is shown in FIG. 7 It essentially contains two delay elements 84 and 85, where the regenerated data signals V2 and H2 are supplied. One of the sake of convenience, it is assumed that the delay time T1 of the first delay element 84 is one bit time. If there is to be switched to the background phase detection, instead of the digital signal V2 the digital signal H2 is switched through to the output. Two cases are possible. The digital signal H2 is delayed from the digital signal V2 to a bit duration. Then, the delay time is set to zero T2 of the second delay element 85 and the takeover can be done without loss of data from the Hintergrundsynchronisiereinrichtung. contrast Hasten the digital signal to the digital signal H2 V2 to a bit time before, the delay time of the second delay element is set to 2 bits, thereby switching between two digital signals without data loss is possible. As delay elements to shift register are with selectable length. This arrangement is possible for synchronous and to a certain extent also for plesiochronous data signals. The maximum permissible phase deviation between the digital signal and the internal system clock signal is determined by the delay means and the number of delay elements.

A working with serial-parallel conversion data selection circuit is shown in FIG. 8 It contains two shift registers, each consisting of two flip-flops KS11, KS12 and KS21, KS22. Each of the shift register is fed to a regenerated digital signal V2 and H2. To the clock inputs of the system clock signal CT is at. In addition, two output flip-flops are KP1 and KP2 provided, the data inputs are connectable via a multi-pole change-over switch 87 to the outputs of one or the other shift register. At their clock inputs is located on a parallel clock signal TP, which usually has half the frequency of the system clock signal CT.

By the shift register, the serial digital signals Y2, H2 are converted into parallel signals with a 2-bit word width. The takeover of the parallel signal bits is performed with the parallel clock TP in the output trigger circuits KP1 and KP2. If the frequency of the received digital signal to the system clock signal is too low, the Unschalten between the shift registers a pulse of the parallel clock signal TP is hidden. In the timing chart shown in Figure 9 the corresponding parallel-to-clock signal is designated TP1. contrast, if the received digital signal has a higher frequency than the system clock signal, so a pulse into the parallel clock signal must be inserted when switching between the shift registers. In Figure 9, the parallel clock signal for this case is denoted by TP2. By plug or by means of a controllable oscillator (VCO), the output signal DA can be converted into a digital signal kontinuirliches again.