Memory access control circuit.

p0001The invention relates to a circuit arrangement for controlling access to a memory by at least two processors with a clock-driven control circuit, the request signals from the processors and therefrom generates control signals for accessing the memory, and interrupts the execution of an access for one processor when prior to completion of this access a request signal of the privileged processor occurs.

p0002Such a circuit arrangement is known from DE-OS 35 02 721. In it, although an address register is provided for each processor, however, the data terminal of the memory is connected without intermediate storage via bus switch controlled with the corresponding data terminals of the processors. However, many processors need to deliver and in particular for transferring data from a substantial period, as several clock cycles of a clock signal, and during this time the memory must remain addressed so that data remain valid until the processing or acquisition. Furthermore, it must, if the access of a processor of lower priority is interrupted by the privileged processor, repeat this processor lower priority its request constantly, until the access to the memory is free. This not only requires additional time, but also additional programming measures. The maximum speed of consecutive hits is not determined by the speed of the memory, but by the appropriate speed the accessing processors.

p0003The object of the invention is therefore to provide a circuit arrangement of the type mentioned, by means of which the maximum speed of the memory can be largely utilized independently of the cycle time of the connected processors, for access.

p0004This object is achieved in that data registers for each processor for the incoming and outgoing data are provided which are each connected between the data port of the memory and the data port of the subject processor, and that the control circuit upon occurrence of a request signal for writing data in the memory directly writes the data supplied by the processor into the associated data register and to read data from the memory a predetermined time after the request signal writes the output at the data output of the memory data in the corresponding data register, provided there has been no request signal of the privileged processor during this period is, and when a request signal of the privileged processor during the execution of the access to another processor occurrence these privileged access executes first and then automatically continues the not fully carried out access.

p0005By the use of the data registers for each processor there is a significant decoupling between the memory and the connected processors, so that the speed of consecutive accesses to the memory is no longer dependent on the speed of the individual processors. The data read from the memory data may in fact be held in the data register for the processor in question are available until they are processed by the processor, while in the meantime been able to take place further accesses to memory. Also, when writing in the memory, an uncoupling is possible in so far that a processor regardless of whether the access to the memory is currently possible, the data to be inscribed directly into the data memory, and then may continue in its other processing during the actual writing of the data later takes place in the memory. In this way, not only the operation of the memory is accelerated by accessing a slow processor, but also the operation of the processors in an access conflict.

p0006There are already memory (dual port memory) for access from two positions, two processors known, use the data register. For example, in Japanese Patent Application 63-183678 (English summary) and the IEEE ISSCC conference reports February 1985, pages 44 and 45 memory arrays are described in which the to be written into the memory data is cached in registers. Further in US-PS 4,796,232 a memory controller is provided, wherein a data register is only intended for a processor for data read from the memory. Data register for both to be written and read data are not known therefrom, and accessing the storage processors and other elements are all equal among themselves, and each commenced access will only be fully completed before an access from any other source is started.

p0007When accessing the memory is a multi-bit data word is read or written in parallel respectively. Frequently now is the number of bits of a memory word among differently to the number of bits of a data word for a processor, in particular, for example, the memory word comprises eight bits, while the processor is operating with 16-bit data words. In this case, the data word of a processor at two different, expediently successive addresses of the memory is stored. In order to permit in this case a simple as possible access of the processor to the memory, it is appropriate according to an embodiment of the invention that for the transmission of words with p-fold word width of the memory to or from at least one processor, the control circuit successively p additional sub-address signals for the memory is generated and addressed with the current supplied from the processor address signals successively p memory words in the memory that are provided for this processor p data registers each with a word width of the memory, the record when reading from the memory successively p words from memory and after receiving the last word proposed for all words in parallel to the data port for this processor and record for writing into memory parallel different parts of the processor to the memory data to be written word and successively proposed to the memory. In this way, the memory for the processor such as with a correspondingly larger length data word appears, while for the memory only take place several consecutive accesses without the memory must otherwise be designed for a larger word length. In this way, in addition, a decoupling of the data word width manages to speed moderate decoupling between memory and processors. To adjust the individual parts of the wider data word of the processor to the data word width of the memory, it is favorable according to a further embodiment of the invention is that the p data registers are connected each for a processor in series and form a shift register. A shift register is a used in other contexts means for parallel-serial conversion.

p0008Digital systems are commonly controlled and synchronized by a clock signal. A system with multiple processors and a shared memory may use a common clock generator, but it is also possible to assign each processor includes a clock generator. Particularly in the latter case it is advantageous according to one embodiment of the invention that the control circuit essentially consists of two identical parts which receive the same request signals from the processors in parallel and of which the controlled one part with rising clock edges and the other part with falling clock edges and is the part that first occurs whose associated clock pulse edge for a request signal of a processor that generates the control signals for the memory and the registers. Thus, each request is processed by the next rising or falling clock edge, so that the delay in processing a request is a half cycle time maximum.

p0009It can sometimes happen that the privileged processor accesses the memory to read a memory word to be rewritten by an immediately preceding access begun by a non-privileged processor. This write access of the non-privileged processor will now become broken before the writing is done, and the privileged processor would then read the previous data word. To prevent this and to ensure that the privileged processor always receives the really current data, a further embodiment of the invention is characterized in that the control circuit includes an address comparator, the unfinished in a request signal of the privileged processor for reading during a write access, the read address compares by a non-privileged processor with the write address and equality enrolled from non-privileged processor in the associated data register transfers data directly into the data register of the privileged processor. So is therefore achieved that the privileged processor receives the new data word, although this is not yet written into the memory.

p0010Embodiments of the invention will be explained hereinafter with reference to the drawing. Show it<ul><li>Fig. 1 is a block diagram of a circuit arrangement according to the invention and their connection to the memory,</li><li>Fig. 2 shows the structure of a data register for adjustment of different word widths,</li><li>Fig. 3 shows the structure of the control circuit consists of two substantially identical parts,</li><li>FIGS. 4 and 5 two time diagrams,</li><li>Fig. 6 an address comparator in the control circuit.</li></ul>

p0011In Fig. 1, a memory 10 is coupled via a circuit arrangement 2 comprising data, address and control lines of two processors that are not shown for simplicity. For a processor performs an address bus 24, a control line 25 and a data bus 26, while on the other hand, applicable here as privileged processor address bus 28, a control line 29 and a data bus 30 leads. In a corresponding manner in principle can further processors to be connected to the control circuit second Over the address buses 24 and 28, address signals are supplied from the processors of the circuit arrangement 2, while via the data buses 26 and 30, data words can be transferred in both directions. The control buses 25 and 29 contain both lines that lead to the processors, as well as control lines leading away from them to the circuitry. 2

p0012For the control lines include a request line for a signal indicating at the same time that the lying on the corresponding address bus signals are valid and the address signals are with this request signal therefore written into an address register 14 and 18 respectively. In addition, the control signal leads to a control circuit 12, there to generate the appropriate control signals or sequence of control signals on the control bus 13 for memory 10th The control circuit 12 controls the same time the priority, ie the possible preemption of the corresponding processor. Further, the control circuit 12 generates further control signals, which will be explained later.

p0013The outputs of the address registers 14 and 18 lead through the buses 15 and 19 to a multiplexer 22 which is controlled via line 37 from the control circuit 12 one of these buses 15 and 19 through switches on the address line 23 for the memory 10th Instead, the address register 14 and 18 might have that are directly connected to each other and to the address bus 23 of the memory 10 and which are switched by the control circuit 12 when required low resistance via so-called tri-state outputs.

p0014a data register for the data buses 26 and 30 of the connected processors each provided 17 or 20, wherein each private data register for a complete processor data word can be provided for both transmission directions, or the inputs and outputs of a single data register for processor the data direction are -Datenwort correspondingly switched. The data direction is determined by an appropriate signal in the control bus 25 and 29, respectively, by the so-called write control signal indicating whether an access to the memory 10 is to be effected for a write operation or a read operation. In case of a write operation, the associated data via the data bus 26 or 30 from the processor concerned are fed together or prior to the write control signal and are written directly into the corresponding data register with this control signal. Further, such a write control signal reaches the control circuit 12 which then supplies a corresponding control signal via the control bus 13 to the memory 10 and further via a selection signal over the connection 31 and 33 selects the corresponding data register output and containing therein data on the data bus 11 to the data terminal of the memory 10 feeds.

p0015In the case of an access for a read operation, a defined period of time after selecting and applying an address over the address bus 23 to the memory 10, a read out and emitted via the data bus data word in one of the data registers 17 and 20 by a corresponding control signal on the connection 31 and 33 enrolled, and this data word is then on the data bus 26 or 30 to the processor in question is available, while the other or possibly another processor already starting a new access to the memory 10th

p0016In the example described, it is now assumed that the device connected to the buses 28, 29 and 30 processor 16-bit data words processed while the memory 10 at each memory address contains only one 8-bit data word. In this case, on each request will be driven from this processor in immediate succession two addresses of the memory 10 and written thereby the read-out data words in the data register 20 in sequence and outputted in parallel through the data bus 30th For controlling the succession of the two data words in memory 10, the address bus 19 is expanded to the address of this processor to a line 35 which comes from the control circuit 12th This line 35 leads initially to a binary value, and when the read out data word stored at the corresponding address in the memory 10 and stored in data register 20, the signal on line 35 is set to the other binary value is switched (if this line address bit lowest represents valence, characterized the adjacent address in the memory 10 is activated), and which is now read out data word is also written into the data register 20 by an appropriate signal on the connection 31 from the control circuit 12th

p0017A possible construction of the data register 20 for this adaptation of the data word width of the memory to the larger data word width of the associated processor is shown in Fig. 2. In it, the data bus 11 to the input of a register 40 with the width of a memory data word, the 8 bits wide in this case, and the output 41 of the register 40 via a connected bus switch 46 to the lines for the data bits most significant of data bus 30, and also performs the output 41 of the register 40 to the input of a further register 42 having 8-bit width, the output 43 are connected via a further bus driver 46 connected with the other lines of the data bus. The bus switches 44 and 46 are initially open.

p0018When the first data word from the memory is supplied via the data bus 11, it is written through a signal on a line 31b of the control circuit 12 in Fig. 1 in the register 40. Simultaneously, the former contents of the register 40 is written into the register 42, which, however, continue to be of no importance here. The second supplied via the data bus 11 data word is also written by an appropriate signal on line 31b in the register 40, which now contains the second data word, while the first data word is transferred to the register 42 at the same time. Subsequently, the bus switches 44 and 46 are closed, so that the two 8-bit data words can be supplied as a 16-bit data word to the processor.

p0019In a corresponding manner, two 8-bit registers 50 and 52 are provided for writing a 16-bit data word in the memory from which the register 50 receives the corresponding 8-bit part of the processor data word via a multiplexer 54th The writing into the registers 50 and 52 is carried out by a write control signal on the line 29 within the control bus 29th

p0020First, then, the 8-bit data word contained in the register 50 is supplied to the memory 10 via the data bus 11 and enrolled at the address that is determined by a binary value on the line 35th Thereafter, the binary value is changed on the line 35 and written via the line 31a, the data word contained in the register 52 via the multiplexer 54 to the register 50, which is then supplied to the memory 10 via the data bus 11 and written therein. Instead, the two registers may be 50 and 52 also connected in parallel to the input 30, the multiplexer 54 course optional one of the outputs of the registers 50 or 52 to the data bus 11th

p0021The control circuit 12 includes among others a known priority control circuit which is the requirement of the devices connected to the control bus 29 processor priority over a request from the connected to the control bus 25 processor, as well as some selectors that selects control lines of the control bus 29 or 25 in a corresponding manner, and via the bus 13 to the memory 10 feeds. Further, the control circuit 12 includes a sequencer that generates, for example, the control signals for writing data read from the memory 10 into the associated data register a predetermined period of time after selecting and forwarding the concerned address. This time delay, as well as the rest of the procedure for generating the control signals is controlled by the clock signals of a clock generator that is not shown in more detail in Fig. 1 for clarity. This clock generator can also be the two processors or control at least one of them, but it could also both processors have their own clock generators, the frequencies of the clock signals generated thereby can be very different. However, the generation of the control signals can not start until the next Taktf lanke after a request signal. This waiting time can occur until nearly a clock cycle time, depending on when the request signal occurs within this clock cycle.

p0022In order to shorten this waiting time, the construction of a control circuit 12 is shown schematically in Fig. 3. Therein the control circuit 12 includes two substantially identical parts 64 and 66, which are simplified here shown as blocks, since there is the internal structure of the on the control buses 25 and 29, the input control lines and the necessary data for the memory used in each case control signals. The circuits in two parts 64 and 66 are 60 controlled by a clock generator by clock signals that are supplied to the part 64 through the line 61 directly and the part 66 via the inverter 62 and the line 63 is inverted. Characterized responding to a request signal on the control bus 25 and 29, the portion in which the first active clock edge occurs after the request signal. The output signals generated at the outputs 65 and 67 of the parts 64 and 66 are combined, what is symbolically indicated here by the OR circuit 68, and the respective active signal or the active signal edge for controlling the memory of the outcome or the delivered control bus 13 for the memory.

p0023The course of a access by both the processors connected to the circuit arrangement shown in Fig. 1 will be explained with reference to the exemplary timing diagram in Fig. 4. The first line is the clock signal of the clock generator 60, which is indicated in Fig. 3, shown, in which the individual clock pulses are numbered from 1 to 12, wherein it is assumed that processors are connected, in which between two consecutive requirements for access are at least 12 clock pulses, even if the processors have independent clock generators.

p0024The individual time diagrams in Fig. 4 are otherwise designated by the numbers which the lines or buses to the circuits of FIGS. 1 to 3 refer, to which the signals of the time chart occur.

p0025Prior to the first pulse occurs on a request signal on the control bus 29 of the privileged processor. The triggered thereby processing and selection of the address signal may require a clock cycle, so that abuts the right address on the address bus 23 of the memory 10 at the beginning of the second clock pulse. After 1 1/2 clock cycles then read from the memory 10 data word that is written at the beginning of the fourth clock pulse in the register 40 and thus appear on the connection 41 appear on the data bus 11th With the start of the fifth clock pulse, the following address is determined by the signal change on the line 35 in Fig. 1 via the address bus 23 to the memory 10, and 1 1/2 clock cycles later appear on the data bus 11, the next memory word at the beginning of the seventh clock pulse is written in the register 40 and thus appear on the connection 43, while the previous content is transferred to the register 42. Thus, the bus switch can be 44 and 46 released in FIG. 2, so that now the complete data word is available to the processor on the bus 30.

p0026In the meantime, however, is already a requirement of the other processor has arrived on the control bus 25, which is kept by the current access the privileged processor in a waiting state. The associated address is taken into the address register 14, and when the previous access has been completed, ie, the second memory word is transferred to the register and thus the waiting status is terminated, is supplied with the start of the eighth clock pulse, the new address of the memory 10, whereby again the new data word will appear after 1 1/2 clock cycles on the data bus 11 and is written at the beginning of the tenth clock pulse in the data register 17, and thus appear on the data bus 26 for this processor. Meanwhile, the acquisition of the still pending on the data bus 30 data word needs to be not yet complete. Similarly, the data word is on the data bus 26 even while the next access of privileged processor can be done already.

p0027In the timing chart in Fig. 5, the occurrence of a request from the privileged processor is assumed during the access has begun for the non-privileged processor already by the corresponding signal on the control bus 25th This may here lie just before the trailing edge of the first clock pulse, so that the address applied on the address bus 23 to the memory 10 with the trailing edge of the second clock pulse, so in Fig. The portion 66 of the control circuit 12 3 is effective.

p0028Now the beginning of the third clock pulse, a request of the privileged processor appears on the control bus 29th The corresponding address appears at the beginning of the fourth clock pulse on the address bus 23. At about the same data word read will appear also in the aborted access to the data bus 11, but this is by the address change occurring about the same time no longer reliable or stable so that it does not more can be done to the data register 17th The address change with the beginning of the fourth clock pulse, however, the first portion of the data for the privileged processor that is included in the register 40 with the beginning of the sixth clock pulse and appear on the compound 41 appears at the end of the fifth clock pulse. shown in a corresponding manner as in Fig. 4, the second part of the data word will now be addressed and transferred to the register 40, while the first part is overwritten in the register 42. This is the beginning of the ninth clock pulse.

p0029Thus, the access of the privileged processor is substantially complete, and the earliest time subsequently, namely at the beginning of the tenth clock pulse is now again the address of the non-privileged processor whose access was not yet finished, placed on the address bus 23 to the memory 10 , and the read word is written with the beginning of the twelfth clock pulse into the data register 17 and will appear on the data bus 26. However, now that is a longer time between the start of the request on the control bus 29 and the output of the associated data word has the associated processor optionally be placed in a wait state until access the privileged processor is terminated by an appropriate signal from the control circuit 12th This is particularly important when the clock frequencies of the processors are very different and, in particular, the clock frequency of the non-privileged processor is much higher.

p0030The procedures run in a similar manner from the writing of a data word, so that these operations are not shown separately. Each access for writing starts but expediently first with a read operation at the address to be written, which is then switched to a write operation. However, when writing a data word representing a possible waiting state of the non-privileged processor when this write operation is interrupted by an access of privileged processor, since the data to sind.Die then already enrolled in the data register of the non-privileged processor continuation of the writing operation is carried out after completion of the interrupting access by the privileged processor as well as automatically upon reading by control circuit 12th

p0031It should be noted that the numbers of clock cycles are chosen in the described processes, for example, and can be selected depending on the exact structure of the control circuit and the memory is also different.

p0032If a write operation of a non-privileged processor is interrupted by a read access of privileged processor while the same address to be read, in which the non-privileged processor wanted to enroll, is to ensure that the privileged processor actually new to be written, not contained in the memory receives word. This is done with a complement of the control circuit 12, which is shown in Fig. 6. In this case only the parts of Fig. 1 are again shown and provided with the same reference numerals, which are in this context.

p0033In the control circuit 12, an address comparator 70 is provided which receives the two existing on the buses 15 and 19 addresses. In addition, the comparator 70 receives also the signal on the line 35, which is a part of the address of the privileged processor. Now, when the address comparator 70 has an equality of the address on bus 15 with the address on the bus 19, including the line 35 notes and at the same time is reported via the control line 25 by the non-privileged processor, a write access and via the control line 29 from the privileged processor read access , the data register 17 is controlled via the connection 33, to give the to be written by the non-privileged processor data onto the data bus 11, and via the connection 31, the data register 20 of the privileged processor is driven to the now present on data bus 11 the data word to take. In this case, the driving of the memory is suppressed to read course. In this manner, the data register 20 receives the updated data word of the addressed address, although this is not yet written into the memory and outputs this via the data bus 30 to the privileged processor further.