Charge pump circuit.

0001The present invention generally relates to charge pump circuits, for example, for use in a phase locked loop (PLL) system.

0002Fig. 1 illustrates a conventional PLL utilizing a digital phase comparison circuit 4. A reference oscillation signal is produced by a reference oscillation signal generating circuit 1 and is provided to a frequency-dividing circuit 2, in which it is frequency-divided to provide a frequency-divided signal R at an output terminal of the circuit 2. The frequency-­divided signal R has a reference frequency, for example, of 25 kHz. The output terminal of the frequency-dividing circuit 2 is coupled with an input terminal R′ of the digital phase comparison circuit 4 to provide the frequency-divided signal R thereto as a first phase comparison signal.

0003A voltage controlled oscillator (VCO) 7 produces an oscillation signal which it supplies to the input of a variable frequency-dividing circuit 3 simultaneously with the provision of the reference oscillation signal to the frequency-dividing circuit 2. The variable frequency-dividing circuit 3 divides the frequency of the oscillation signal from the VCO 7 by a divisor N to provide a frequency-divided signal V which it supplies to a second input terminal V′ of the digital phase comparison circuit 4 as a second phase comparison signal.

0004With reference to Fig. 2, the digital phase comparison circuit 4 includes nine NAND gates connected as shown therein. With reference also to Fig. 3, the digital phase comparison circuit 4 is operative to provide a first phase difference signal U at a first output terminal U′ thereof and a second phase comparison signal D at a second output terminal D′ thereof in response to a phase difference between the first and second phase comparison signals R and V received at the input terminals R′ and V′, respectively. More specifically, when the first phase comparison signal V is delayed in phase with respect to the second phase comparison signal R, as shown in the left side of Fig. 3, the first phase difference signal U changes from a logic "1" state (a high voltage level) to a logic "0" state (a low voltage level) upon a transition of the phase comparison signal R from a logic "1" state to a logic "0" state. The first phase difference signal U thereafter remains in the logic "0" state until the phase comparison signal V subsequently falls from a logic "1" state to a logic "0" state, whereupon the first phase difference signal U rises to a logic "1" state. The second phase difference signal D remains in a logic "1" state so long as the phase of the first phase comparison signal R leads that of the second phase comparison signal V.

0005However, at such times that the phase of the second phase comparison signal V leads that of the first phase comparison signal R, as shown in the right hand side of Fig. 3, the first phase difference signal U remains in a logic "1" state, while the second phase difference signal D changes from a logic "1" state to a logic "0" state when the second phase comparison signal V falls from a logic "1" state to a logic "0" state and thereafter remains in a logic "0" state until the first comparison signal R also falls from a logic "1" state to a logic "0" state, whereupon the second phase difference signal D is raised to a logic "1" state.

0006With reference again to Fig. 1, the first and second phase difference signals U and D are supplied to respective inputs of a charge pump circuit 5. With reference also to Fig. 4, it will be seen that the charge pump circuit 5 includes a p-­channel field effect transistor (FET) Qa whose gate is connected to output U′ of the digital phase comparison circuit 4 to receive the first phase difference signal U therefrom and whose drain-­source circuit is coupled between a source of positive power voltage + V_DD and an output terminal 20 of the charge pump circuit 5. The charge pump circuit 5 also includes an n-channel FET Qb whose gate electrode is coupled through an inverter Qc with output D of the digital phase comparison circuit 4 to receive the second phase difference signal D therefrom. The source-drain path of the FET Qb is coupled between the output terminal 20 of the charge pump circuit 5 and a circuit ground.

0007A loop filter 6 includes an operational amplifier Qd having an inverting input terminal coupled through an input resistor Ra with the output terminal 20 of the charge pump circuit 5. An output terminal of the operational amplifier Qd is coupled with a control voltage terminal of the VCO 7. A first feedback capacitor Ca is coupled between the output terminal of the operational amplifier Qd and its inverting input terminal. A second feedback capacitor Cb has a first terminal connected with the output terminal of the operational amplifier Qd and a second terminal connected with a first terminal of a feedback resistor Rb having a second terminal connected with the inverting input terminal of the operational amplifier Qd. In this manner, the loop filter 6 takes the form of a mirror integrating circuit.

0008At such times that the phase of the first phase comparison signal R leads the phase of the second phase comparison V, the voltage applied to the gate of the FET Qa is periodically brought low by the first phase difference signal U to turn ON the FET Qa. Since the second phase difference signal D remains at a logic "1" state (high voltage) the gate of the FET Qb remains essentially at ground potential, so that the FET Qb is OFF. Accordingly, while the phase of the first phase comparison signal R leads that of the second phase comparison signal V, the loop filter 6 is charged by the power source voltage + V_DD whenever the first phase difference signal U goes low in a logic "0" state. Conversely, at such times that the phase of the second phase comparison signal V leads that of the first phase comparison signal R, the FET Qa is maintained in an OFF state by the high voltage level of the first phase difference signal U in the logic "1" state, while the FET Qb is turned ON periodically by the high voltage level at the output of the inverter Qc produced at such times that the second phase difference signal D is in a logic "0" state so that the loop filter 6 is then discharged through the FET Qb. However, when both of the first and second phase difference signals U and D are in a logic "1" state, FETs Qa and Qb are both turned OFF so that the loop filter 6 is neither charged nor discharged. Accordingly, the loop filter 6 produces a dc voltage level at the output terminal thereof corresponding with the phase difference between the first and second phase difference signals U and D.

0009As noted above, the dc voltage level produced at the output of the loop filter 6 is applied to the control voltage terminal of the VCO 7 so that, in a stationary state, the VCO 7 produces an oscillation signal whose frequency is N times the frequency of the phase comparison signal R. The frequency dividing circuit 2, the variable frequency-dividing circuit 3, the digital phase comparison circuit 4 and the charge pump circuit 5 may be fabricated as a single chip integrated circuit 15 (see "Practical Use Guide to PLL", pages 125-127, dated August 30, 1974, by Seibundoshinkosha and Japanese Laid-Open Patent No. 51-139758 published December 2, 1976).

0010With reference again to Fig. 2, the phase comparison circuit 4 ideally provides the first and second phase difference signals U and D in a logic "1" state whenever the phase comparison signals R and V are in phase. However, due to the inherent propagation delays of the circuit elements comprising the phase comparison circuit 4, upon the simultaneous high to low logic state transitions of the in-phase first and second phase comparison signals R and V (as shown by the solid line waveforms in Fig. 5A) both the first and second phase difference signals U and D are then brought to a logic "0" state for a brief but significant period of time. When the second phase comparison signal V becomes delayed in phase with respect to the first phase comparison signal R by a very small amount as shown by the dashed line in Fig. 5A, the first and second phase difference signals U and D are suddenly placed in logic states similar to those illustrated in the left-hand side of Fig. 3, although a brief interval may exist during which both signals are simultaneously in a logic "0" state. Alternatively, where the second phase comparison signal V becomes advanced in phase by a very small amount with respect to the first phase comparison signal R the first and second phase difference signals U and D are suddenly placed in states similar to those illustrated in the right-hand side of Fig. 3. The resulting relationship between the phase difference ΔΘ, (that is, the phase difference of the second phase comparison signal V with respect to the first phase comparison signal R) and the charging and discharging periods controlled by the first and second phase difference signals U and D, is illustrated by the line A in Fig. 6. In Fig. 6, the axis of ordinates represents the relative charging and discharging periods of the loop filter 6, while the axis of abscissas represents the relative phase delay or advance of the second phase comparison signal V with respect to the first phase comparison signal R. It will be seen from Fig. 6 that an indefinite charging period exists where the signals R and V are either in phase or only slightly out of phase so that the operation of the PLL is unstable under such conditions.

0011In order to overcome the foregoing problem, it has been proposed that a dead zone interval be introduced for phase differences ΔΘ which do not exceed a predetermined magnitude, so that, when the first and second phase comparison signals R and V are in phase, the first and second phase difference signals U and D are reliably maintained in a logic "1" state. Accordingly, the combination of the operational delay times of the NAND gates and other circuit elements forming the phase comparison circuit 4 are changed so that the relationship of the charging and discharging periods to the phase difference ΔΘ is instead expressed by the broken line B of Fig. 6. That is, even when the second phase comparison signal V is phase delayed with respect to the first phase comparison signal R by a relatively small amount (for example, as shown by the solid line waveform illustrated in Fig. 5B) or when the second phase comparison signal V is advanced in phase with respect to the first phase comparison signal R (for example, as shown by the dashed line waveform in Fig. 5B), the first and second phase difference signals U and D are maintained in a logic "1" state. Accordingly, unless the phase difference ΔΘ exceeds a minimum predetermined magnitude defining the extremes of the dead zone interval, the charge pump circuit 5 will neither charge nor discharge the loop filter 6.

0012Where the phase comparison circuit 4 and the charge pump circuit 5 are constructed as above so that an indefinite charging period exists (as represented by the discontinuous line A in Fig. 6) or where a dead zone interval is provided (as shown by the broken line B of Fig. 6), the phase locked loop exhibits a different natural frequency ωn and damping coefficient ξ when operating in a phase locked condition than while operating in an unlocked condition. Accordingly, the natural frequency and damping coefficient of the phase-locked loop cannot be optimized and, consequently, the purity of the oscillation frequency of the VCO 7 deteriorates. The foregoing results in the deterioration of the carrier-to-noise ratio where, for example, the output of the VCO 7 is utilized to provide a local oscillation signal for a radio receiver. Moreover, where the conventional phase locked loop as described above, is utilized for FM modulation, the modulated output signal exhibits distortion as a consequence of deterioration in the purity of the oscillation frequency.

0013A further disadvantage inherent in the conventional phase locked loop described above is an unavoidable dependency between the loop gain and the cut-off frequency of the loop filter 6. That is, although the loop gain can be adjusted by selecting the ratio between the resistance values of the resistors Ra and Rb, this likewise changes the cut-off frequency of the loop filter 6. The design of the conventional phase locked loop, therefore, is inherently inflexible. In addition, the conventional phase locked loop requires the use of the operational amplifier Qd for constructing the loop filter 6, resulting in a poor space factor and increased cost.

0014Accordingly, it is an object of this invention to provide an improved charge pump circuit and an improved phase locked loop system which avoid the above mentioned disadvantages and problems associated with the prior art.

0015More specifically, it is an object of the present invention to provide a charge pump circuit for a phase locked loop which is capable of more reliably charging and discharging a loop filter thereof in proportion to a phase difference which is arbitrarily small.

0016Another object of the present invention is to provide a charge pump circuit capable of reducing the lock-up time of a phase locked loop system to thereby provide stable operation.

0017Still another object of the present invention is to provide a phase locked loop system employing a charge pump circuit for charging a loop filter wherein the cut-off frequency of the loop filter is independent of the loop gain of the phase locked loop system, and vice versa.

0018Yet another object of the present invention is to provide a phase locked loop system which has an advantageous space factor and which can be made inexpensively.

0019In accordance with an aspect of the present invention, a charge pump circuit for charging capacitive means in response to a phase difference between first and second input signals comprises constant current source means for providing a first constant current; constant current sinking means for absorbing a second constant current; means for substantially equalizing the magnitudes of the first constant current provided by the constant current source means and the second constant current absorbed by the constant current sinking means; and switching means for providing the first constant current and the second constant current flowing in opposed directions to said capacitive means through an output terminal of the charge pump circuit in response to the phase difference between the first and second input signals for selectively charging and discharging the capacitive means to produce a voltage level thereof corresponding to the phase difference.

0020In accordance with another aspect of this invention, a phase locked loop system comprises means for receiving a reference signal; voltage controlled oscillator means for providing a phase adjustable output signal controllable by a control voltage applied at a control terminal thereof; means for producing a phase difference signal representative of a phase difference between the reference signal and the phase adjustable output signal of the voltage controlled oscillator means; means for producing the control voltage including constant current source means for providing a first constant current, constant current sinking means for absorbing a second constant current, means for substantially equalizing the magnitudes of the first current provided by the constant current source means and the second constant current absorbed by the constant current sinking means, capacitive means for producing the control voltage, and switching means for providing the first constant current and the second constant current flowing in opposed directions to the capacitive means in response to the phase difference signal for selectively charging and discharging the capacitive means to produce the control voltage corresponding to the phase difference signal; and means for applying the control voltage produced by the capacitive means to the control terminal of the voltage control oscillator means.

0021These, and other objects, features and advantages of the invention, will be apparent in the following detailed description of certain illustrative embodiments thereof which is to be read in conjunction with the accompanying drawings forming a part hereof, and wherein corresponding parts and components are identified by the same reference numerals in the several views of drawings. <ul id="ul0001" list-style="none"><li>Fig. 1 is a block diagram of an exemplary prior art phase locked loop circuit utilizing a digital phase comparison circuit;</li><li>Fig. 2 is a schematic diagram of a digital phase comparison circuit incorporated in the phase locked loop circuit of Fig. 1;</li><li>Fig. 3 is a waveform diagram of frequency-divided, phase comparison signals input to the phase comparison circuit of Fig. 2 and phase difference signals output thereby to which reference is made in explaining the operation thereof;</li><li>Fig. 4 is a partially schematic and partially block diagram illustrating a charge pump circuit and a loop filter incorporated in the phase locked loop circuit of Fig. 1;</li><li>Figs. 5A and 5B are waveform diagrams of frequency-­divided, phase comparison signals input, respectively, to the phase comparison circuit of Fig. 2 and to a modified form thereof, and output phase difference signals therefrom, to which further reference is made in explaining the operation thereof;</li><li>Fig. 6 is a graph of certain operational characteristics of prior art phase locked loop circuits, including the phase locked loop circuit of Fig. 1, and of the phase locked loop system of the present invention;</li><li>Fig. 7 is a partially block and partially schematic circuit diagram illustrating a first embodiment of a charge pump circuit and phase locked loop system in accordance with the present invention; and</li><li>Fig. 8 is a partially schematic and partially block diagram illustrating a second embodiment of a charge pump circuit and phase locked loop system in accordance with the present invention.</li></ul>

0022With reference to Fig. 7, a phase locked loop system in accordance with a first embodiment of the present invention is illustrated therein. Elements of the Fig. 7 embodiment corresponding to elements shown in Fig. 1 bear the same reference numerals.

0023In a charge pump circuit 21 of the Fig. 7 embodiment, the source-drain paths of p-channel FETs Q₃ and Q₄ are connected in series between a positive voltage power source terminal T₃ and an output terminal T₂ of the charge pump circuit 21. Charge pump circuit 21 also includes n-channel FETs Q₅ and Q₆ whose drain-­source paths are connected in series between the output terminal T₂ and circuit ground. The FET Q₃ is a current source transistor which supplies a charging current i₃ of constant magnitude in a first direction toward the output terminal T₂ for charging a loop filter 22 described in greater detail hereinbelow. The FET Q₆ is a current sink transistor which draws a discharging current i₆ of constant magnitude in a second direction from the output terminal T₂ to circuit ground for discharging the loop filter 22. The FET Q₄ acts as a first switching transistor for controlling the application of the charging current i₃ supplied by the current source transistor Q₃, while the FET₅ Q₅ serves as a second switching transistor for controlling the flow of the discharging current i₆ from the output terminal T₂ to ground through the current sink transistor Q₆.

0024A current mirror circuit 11 includes a p-channel FET Q₁ at an input side thereof, the FET Q₁ having a source electrode connected with terminal T₃ and drain and gate electrodes both connected to a control terminal T₁ of the charge pump circuit 21. The FET Q₃ is arranged at an output side of the current mirror circuit 11 such that its gate electrode is coupled with that of the FET Q₁. A further p-channel FET Q₂ is also connected at the output side of the current mirror circuit 11 such that its gate electrode is coupled with that of the FET Q₁ and its source electrode is connected with that of FET Q₁ to the terminal T₃.

0025A second current mirror circuit 12 includes an n-­channel FET Q₇ whose source electrode is connected to circuit ground and whose drain and gate electrodes are connected with the drain electrode of the FET Q₂. The current sink transistor Q₆ forms the output side of the current mirror circuit 12 such that its gate electrode is connected with that of the FET Q₇.

0026The output terminal U′ of the digital phase comparison circuit 4 is connected to the gate electrode of the first switching transistor Q₄ and the output terminal D′ of the digital phase comparison circuit 4 is coupled through an inverter Q₈ to the gate electrode of the second switching transistor Q₅. The digital phase comparison circuit 4 and the charge pump circuit 21 together with the frequency-dividing circuits 2 and 3, are fabricated as an integrated circuit 23, as indicated in Fig. 7.

0027A resistor R₂ is connected between the control terminal T₁ and circuit ground. A resistor R₁ has a first terminal connected to the control terminal T₁ and a second terminal connected with the collector of an non transistor Q₉ whose emitter is connected to circuit ground.

0028The loop filter 22 includes a capacitor C₁ connected between the output terminal T₂ and circuit ground. The loop filter 22 further includes a resistor R₃ having a first terminal connected with the output terminal T₂ of the charge pump circuit 21, and a capacitor C₂ having a first terminal connected with a second terminal of the resistor R₃ and a second terminal connected with the circuit ground. The loop filter 22 produces a voltage E₆ at the terminal T₂ which the loop filter 22 supplies to the control terminal of the VCO 7.

0029The digital phase comparison circuit 4 receives the first and second phase comparison signals R and V as inputs and produces the first and second phase difference signals U and D as outputs, as discussed above in connection with Figs. 3 and 5A. Accordingly, the relationship of the first and second phase difference signals U and D produced by the phase comparison circuit 4 to the phase difference between the first and second phase comparison signals R and V provided as inputs thereto is expressed essentially by the discontinuous line A of Fig. 6.

0030In operation, the current i₁ flowing in the FET Q₁ has a constant magnitude depending on a signal level applied to the base of the transistor Q₉, as discussed more fully herein­below. Since the FETs Q₁ and Q₃ form respective input and output portions of the current mirror circuit 11, the magnitude of the current i₃ flowing in the source-drain path of the FET Q₃ will be equal to that of the current i₁ of the FET Q₁. Since the FETs Q₁ and Q₂ likewise form respective input and output portions of the current mirror circuit 11, the current flowing in the source-­drain path of the FET Q₂ is also equal in magnitude to that of the current i₁ and, therefore, to that of the current i₃. Since the FETs Q₇ and Q₆ constitute input and output portions, respectively, of the current mirror circuit 12, the current i₆ flowing in the source-drain path of the FET Q₆ is equal to the current flowing in the source-drain path of the FET Q₇. Since the current flowing in the source-drain path of the FET Q₇ is equal to that flowing in the source-drain path of the FET Q₂ and, therefore, is also equal to that of i₃, it is apparent that the magnitudes of the currents i₃ and i₆, when permitted to flow through the switching transistors Q₄ and Q₅, respectively, will have the same magnitude. Accordingly, the charge pump circuit 21 forces the magnitudes of the currents i₃ and i₆ to equal that of the reference current i₁ whenever the respective switching transistors Q₄ and Q₅ are turned ON.

0031In operation, where the phase comparison signal V is phase delayed with respect to the phase comparison signal R such that the phase difference signal U is in a logic "0" state and the phase difference signal D is in a logic "1" state, the switching transistor Q₄ is turned ON and the switching transistor Q₅ is turned OFF. Accordingly, the constant current i₃ is then provided to the loop filter 22 to charge the capacitors C₁ and C₂ to increase the level of the output voltage E₆ of the loop filter 22. Consequently, the phase (that is, the oscillation frequency) of the oscillation signal produced by the VCO 7 is advanced. Since the capacitors C₁ and C₂ are charged by a current i₃ having a constant magnitude, the voltage level E₆ is linearly increased thereby.

0032When the second phase comparison signal V is phase advanced with respect to the first phase comparison signal R so that the first phase difference signal U is in a logic "1" state while the second phase difference signal D is in a logic "0" state, the first switching transistor Q₄ is then turned OFF while the second switching transistor Q₅ is turned ON such that the capacitors C₁ and C₂ are thereby discharged by the constant current i₆. Consequently, this simultaneously decreases the level of the output voltage E₆ of the loop filter 22 in a linear fashion, such that the phase of the oscillation signal produced by the VCO 7 is delayed.

0033Furthermore, at such times that the first and second phase comparison signals R and V are in phase such that the first and second phase difference signals U and D are in a logic "1" state, the first and second switching transistors Q₄ and Q₅ are both turned OFF, so that neither the current i₃ nor the current i₆ is permitted to flow to the output terminal T₂. Consequently, the capacitors C₁ and C₂ are neither charged or discharged and the output voltage level E₆ is maintained at a constant value such that the phase of the oscillation signal produced by the VCO 7 is likewise unchanged.

0034As noted above, where the phase comparison signals R and V are in phase, during a short period of time commencing from the trailing edges of the phase comparison signals R and V, both of the first and second phase difference signals U and D switch to a logic "0" state before returning to a logic "1" state at the end of the short time period. Since, however, the magnitudes of the charging and discharging currents i₃ and i₆, respectively, are equal, they add to zero when both of the first and second switching transistors Q₄ and Q₅ are turned ON by the logic "0" levels of the first and second phase difference signals U and D. Accordingly, the capacitors C₁ and C₂ of the loop filter 22 are neither charged nor discharged at such time and the level of the output voltage E₆ is maintained at a constant value so that the phase of the oscillation signal produced by the VCO 7 is unchanged.

0035With reference again to Fig. 6, the continuous line C indicates the relationship of the phase difference ΔΘ between the phase comparison signals V and R input to the phase comparison circuit 4 and the charging and discharging periods produced in response thereto by the charge pump circuit 21. It will be seen therefrom that a linear relationship exists between the phase difference ΔΘ and the resulting charging and discharging periods. Since the charge pump circuit 21 supplies charging and discharging currents i₃ and i₆, respectively, which have a constant magnitude, it will be appreciated that the Fig. 7 embodiment provides a linear relationship between the phase difference ΔΘ and the control voltage E₆ even at arbitrarily small phase differences. Accordingly, the phase of the oscillation signal produced by the VCO 7 varies linearly with the phase difference ΔΘ between the first and second phase comparison signals R and V.

0036When the transistor Q₉ is turned OFF, the reference current i₁ flows through the resistor R₂ only, such that the reference current i₁ is maintained at a relatively low value by the relatively high impedance presented by the resistor R₂ alone. When however, the transistor Q₉ is turned ON, the current i₁ is able to flow through the parallel combination of resistors R₁ and R₂, such that the magnitude of the current i₁ flowing through the FET Q₁ is increased. Since the currents i₃ and i₆ are equal in magnitude to the reference current i₁, it will be seen that a means is provided for adjusting the magnitudes of the constant currents i₃ and i₆ by controlling the ON-OFF states of the transistor Q₉. Since the output voltage E₆ of the loop filter 22 varies linearly with the magnitudes of the currents i₃ and i₆, it will be seen that, by adjusting the magnitudes of the constant currents i₃ and i₆ by selecting the ON-OFF states of the transistor Q₉, the loop gain of the phase locked loop is thereby adjusted. It will also be appreciated that the lock-up time of the phase locked loop can be selectably reduced by increasing the loop gain in the foregoing manner. Since the cut-off frequency of the loop filter 22 is determined only by the capacitors C₁ and C₂ and the resistor R₃, whose values are unaffected by the magnitudes of the charging and the discharging currents i₃ and i₆, the cut-off frequency of the loop filter 22 is unaffected by adjusting the loop gain in the foregoing manner. It will also be apparent that the loop gain can be made independent of the cut-­off frequency.

0037With reference now to Fig. 8, a second embodiment of a phase locked loop system in accordance with the present invention is illustrated therein. Elements of the Fig. 8 embodiment corresponding to elements shown in the foregoing figures bear the same reference numerals.

0038In the Fig. 8 embodiment, the first and second current source transistors Q₃ and Q₆ are coupled directly to the output terminal T₂, while the source-drain path of the current source transistor Q₃ is coupled to the positive voltage power source terminal T₃ through a resistor R₆, while the source-drain path of the current sink transistor Q₆ is coupled to circuit ground through a resistor R₈. The source of the FET Q₁ is coupled to the positive voltage power supply terminal T₃ through a resistor R₄, while the source of the FET Q₂ is coupled to the positive voltage power source T₃ through a resistor R₅. The source of the FET Q₇ is coupled to circuit ground through a resistor R₇. A p-­channel bypass switching FET Q₁₀ has its source-drain path coupled in series with the resistor R₆ between the terminal T₃ and circuit ground and has its gate electrode coupled with the output terminal U′ of the phase comparison circuit 4 through an inverter Q₁₂. Accordingly, the bypass switching transistor Q₁₀ is operative to control the flow of the constant current i₃ supplied by the current source transistor Q₃ by bypassing the current i₃ whenever the first phase difference signal U is high.

0039An n-channel bypass switching FET Q₁₁ has its source-­drain path connected in series through the resistor R₈ between the terminal T₃ and circuit ground and its gate electrode connected with the output terminal D′ of the phase comparison circuit 4. Accordingly, the FET Q₁₁ acts as a second bypass switching transistor for controlling the flow of the constant current i₆ supplied by the current sink transistor Q₆ such that whenever the second phase difference signal supplied at the output terminal D′ of the phase comparison circuit 4 is in a logic "1" state, the second bypass switching transistor Q₁₁ is turned ON to bypass the current i₆ which otherwise would flow through the current sink transistor Q₆. In all other respects, the operation of the Fig. 8 embodiment is identical to that of the Fig. 7 embodiment.

0040It will be readily appreciated by those skilled in the art that the embodiments of Figs. 7 and 8 may be similarly constructed with the use of bipolar transistors in place of the field effect transistors (FETs) specifically disclosed herein.

0041Although specific embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.