Microprocessor having cash bypass signal terminal

A microprocessor employed in an information processing system including a cash memory unit, comprising an instruction decoder unit decoding an instruction to be executed and generating decoded instruction information and a data access request for an instruction operand, a bus control unit performing a data access bus cycle, in response to said data access request from said instruction decoder unit, and an instruction execution unit executing an instruction in response to said decode instruction information from said instruction decoder unit and receiving and supplying data from and to said bus control unit, said instruction decoder unit including means for generating a cash bypass request when data, for which said data access request is to be generated, is a predetermined kind, and said bus control unit including means responsive to said cash bypass request for generating a cash bypass command signal in synchronism with said data access bus cycle, said cash bypass command signal being supplied to said cash memory unit to cause said cash memory unit to inhibit a data cashing operation on data responsive to said data access bus cycle.