Read-only memory test method, and device for carrying out the method.

p0001The invention relates to a method for testing the contents of a read-only memory in an integrated circuit which also includes a controlled by the contents of the ROM processor with a computing unit and a storage register, the processor being connected to external connections of the integrated circuit and being switchable to a test mode in which the contents of the ROM is compared within the integrated circuit with externally supplied test data and generates an error message if none match, and an arrangement for carrying out the method.

p0002Such a method and a corresponding arrangement are known from US-PS 4,777,586. The program contained in ROM is often self-prepared by the customer with a significant amount of work, possibly with the assistance of the manufacturer of the microcontroller, and this program thus represents a significant value. In order to prevent a third party to such a microcontroller is purchasing and the content the ROM reads in order to build itself microcontroller or program, this third would save the effort for the development of the program to confirm the contents of the ROM must be possible without this content is immediately noticeable from the outside.

p0003This is done according to the mentioned US-PS 4,777,586 in that the content of the ROM is read out with the aid of a clock signal separately generated and fed to a separate comparator, which receives with the inversion of this clock signal externally supplied test data. An occurrence of the error is stored and delivered after a predetermined number of test steps via a separate output to the outside. For counting the number of test steps, a separate counter is required. The comparator is provided with registers for temporarily storing the data read from the ROM data and the test data. Overall, therefore, a number of additional elements to carry out the examination of the contents of the ROM are needed that require additional area on the integrated circuit.

p0004Object of the invention is therefore to specify a method of the aforementioned type, with which the examination of the contents of the ROM within the integrated circuit with minimal changes, that can be performed with minimal hardware.

p0005This object is achieved by a program stored in the processor test program is provided, which is activated in the test mode of the processor and read in its execution by the processor, the contents of the ROM in sequence and in each case together with the corresponding externally supplied test data of the computing unit for comparison is supplied and an error message occurs in the memory register is stored, and that this error message is issued at the end of the test program via a terminal acting as data in the normal operation of the processor connector.

p0006In this way, only a small additional memory for the test program is required, which must include only a few commands while only elements of the processor or the integrated circuit will be used in the rest of the conduct of the study, which are present for normal operation anyway , Thus in addition to the additional test program for any changes to perform the test within the integrated circuit are practically required, as well as additional connections, in particular for the error message is not required.

p0007Basically, it is sufficient to obtain an indication as to whether the contents of the ROM is correct or even if an error has occurred. For some purposes, for example for a possible correction of the manufacturing process, but it is also convenient to know if a lot of mistakes in the contents of the ROM are present. According to one embodiment of the inventive method it is therefore appropriate that each existing fault latched and at the end of the review program an indication of the number of error messages is discharged outside. This number of error messages can be found also without additional hardware only program steps of the processor, stored and output.

p0008An arrangement for carrying out the process with an integrated circuit that includes a processor with a computing unit and at least one storage register and a read only memory and a number of external terminals of which are connected at least delivered with a test data A test setup is characterized in that in the integrated circuit there is provided a test program memory for receiving control instructions of a test program and in that the processor reads out the setting of the test mode control instructions from the test program memory and these control commands controlling the data from the read only memory sequentially reads and supplies, together with the supplied test data to the arithmetic unit for comparison and at a the inequality of the supplied data indicative control signal of the arithmetic unit modifies the contents of the storage register with respect to a predetermined initial state and at the end of the test program the content of the memory register supplying one acting as a data output during normal operation of the integrated circuit terminal.

p0009According to one embodiment of the inventive arrangement it is advantageous that the processor increases occurring at each control signal of the arithmetic unit the contents of the storage register as a binary number by one unit. This can be realized by corresponding commands in the test program.

p0010To keep the changes conventional microcontroller to perform the test according to the invention of the ROM content low, it is advantageous in a further embodiment of the invention that the read-only memory and the test program over a depending on the test mode and the flow of the test program set switch connected to the processor are. In this way it is easily possible to control the processor sequentially by the test program and through the read-only memory as the actual program memory. The switch is, for example, from the output of the memory already existing Bus Switch.

p0011The test program can be implemented in various ways. It is desired that the test program is a read-only memory. Its content is then defined as the content of the ROM for the program in the manufacture of the integrated circuit and can not be changed improperly.

p0012It is also possible that the contents of the test program is wrong, resulting in an error in the contents of the ROM can be faked for the program, although this is actually correct and the microcontroller is therefore inoperable because the test program is not used in normal operation. It is therefore advisable that the content of the test program from outside the integrated circuit is accessible. There are the contents of the test program will be first examined what can be done in a conventional manner by means of a comparison outside the integrated circuit, since the content of the test program for a third party has no essential significance. Only when the test program is working right, the actual testing of the ROM for the program can be carried out so that then generated error message in every case is due to an error in the content of the program memory.

p0013Embodiments of the invention will be explained hereinafter with reference to the drawing. Show it:<ul><li>FIG. 1 is a schematic block diagram of the essential parts of an inventive arrangement,</li><li>Fig. 2 is a flowchart illustrating a possible implementation of the method according to the invention.</li></ul>

p0014In Fig. 1, a microcontroller 1 is indicated, which is constructed as a monolithic integrated circuit and is connected to a test arrangement 22nd In the microcontroller 1, only the important for the following explanation elements are shown, while other elements for clarity are omitted.

p0015An essential element of the microcontroller 1, the processor 2, also referred to as CPU, which contains a number of switches, of which only the important for the following explanation circuits are also shown. These are the arithmetic logic Verarbeitungsenheit 12, which is generally referred to as ALU. Further, a register is indicated 14 whose output is connected to the one data input of the ALU, while the other input of the ALU 12 and the input of the register with a schematically shown internal bus 3 are connected. A control output 17 of the ALU 12, which leads a signal when the result of the carried out in the ALU 12 link is not equal to zero, via not dargestelle here programmatically switch to another register 16th

p0016Furthermore, a program memory 4 is provided which contains the executed by the microcontroller during normal operation program and as a read-only memory (ROM) is executed, and a further read-only memory 6, which contains the test program. The output 5 of the ROM 4 and the output 7 of the test program memory 6 are selectively connectable via a switch 8 to the internal bus. 3 The addressing of the memory 4 and 6 is not shown separately and in a customary manner by the processor 2 via address lines in the bus 3. When the test program without loops and jumps operates, the test program but could 6 also by a separate address generator, for example, a counter are driven.

p0017The control of the changeover switch 8, which may be implemented as a multiplexer or formed by the outputs of the two memories 4 and 6 typically downstream bus data switch, via the line 11 by a test control circuit 10 which controls and the test mode in the microcontroller 1 is again is influenced via the line 13 from the CPU 2nd Such test control 10 is provided for testing the integrated circuit 1, regardless of the described examination of the contents of the ROM 4 in each case.

p0018The microcontroller 1 is connected for testing over the already existing input-output circuits 18 and 20 with a test arrangement 22nd The input-output circuits 18 and 20 included outgoing line driver circuits and incoming lines receiving circuits, which are at least partially controllable or switchable. This particularly applies to the one-output circuits 18 via the data words with external connected devices, in this case, therefore, with the test arrangement 22, can be exchanged. The outgoing lines are often provided in the assembly 18 with a register so that this data must be generated only briefly by the processor 2 and a longer time is available to the outside.

p0019To perform the test will be on the test setup 22 via line 27, which may actually comprise several lines, a signal for setting the test mode emitted, which is fed via an output circuit 20 and the line 21 of the test control 10th Before both the test set 22 and the microcontroller 1 are set via an unillustrated reset signal in an initial position. The test control circuit 10 is now bringing on line 11 the switch 8 to the position shown and thus performs the first test command from the test program memory 6 via the bus 3 to the processor 2 to where it is stored, for example an instruction register, not shown. Thereafter, if necessary followed by additional commands that set the processor 2 to a desired state. Instead, or additionally, the processor 2 can also still be set via a connection 9 in the test mode.

p0020Thereafter, the test control circuit 10 will temporarily switch to the switch 8 and performs the first data word from the ROM 4 via the bus 3 to the processor 2 to where it is latched in the register 14 and is present at an input of ALU 12th Thereafter, the switch 8 is switched back into the position shown and a signal generated by the test arrangement 22 on the output line 23 data word corresponding to the first correct data word in the ROM 4 via the input-output circuit 18 and the bus 3 to the other input of the ALU 12 fed, and then the two data words are compared, for example, by adjusting the ALU to subtraction or logical comparison function, if it is provided. On the line 17 is only displayed if this equality or inequality has been found. In the latter case, that is the first word in the ROM 4 is wrong with the prescribed content match, the corresponding signal on line 17 is written into the register 16.

p0021After the comparison, or simultaneously therewith, the address is increased for the ROM 4 to 1, and also is supplied with a signal for the end of a test step via the line 13 the test control circuit 10, and then 10 transmits the test control circuit via the line 19 is a synchronizing signal from, which is fed via the input-output circuit 20 and the line 29 of the test arrangement 22 and there provides the next comparison value on Leitung- 23rd Further, the changeover switch 8 is switched to the illustrated position and the next test step carried out in the same manner via the line 11 again. In this way the contents of the ROM 4 is successively compared to corresponding reference values ​​of the test arrangement 22nd This case, if several error signals are generated on line 17, the contents of register 16 can be increased as a binary number also by means of corresponding control of the CPU 2 in each case by one step.

p0022Finally, if the last, ie the highest address has been generated for the ROM 4, terminates the test control circuit 10, the examination, and switches the switch 8 permanently in the position not shown, and also the contents of the register 16, whose output is connected in the usual manner is the bus 3 connected, delivered via the a output circuit 18 at an output 25th This is usually a data word in the example what the values ​​of certain bits of data, whether during the test an error signal has occurred or not.

p0023This is described in Fig. 1 with reference to the arrangement checking procedure will be explained in a more general reference to the flowchart in FIG. 2.

p0024In block 30, the resetting of the entire arrangement, ie the microcontroller and the test setup is done, to a defined initial state. In block 31, a counter in the test arrangement 22, the successively addressed the test data set to the initial position, and in the block 32 the address of the ROM is set to the initial address. In addition, in block 33, the ALU and its associated accumulator is set to zero.

p0025In block 34 a signal is transmitted via the input-output circuit generates, which causes the test set to supply the next test data to the microcontroller. In block 35 the addressed from the processor memory location in the ROM is read out and supplied to the processor, and in block 36, the test data generated by the test set are read. In block 37, the address is incremented for the ROM to 1 preliminarily.

p0026In block 40 will now be examined whether the data read from the ROM data (block 35) with the current supplied from the test set 22 data match (block 36). If this is not the case, in block 44, an error register is set or increment one error counter, and then proceeded to the block 41 while gone directly to block 41 in accordance both data, in which the signal at the output of the microcontroller, the data requests from the test set 22, is reset. Finally, it is checked in block 42 whether the last highest address of the ROM has been read out, ie. Due to the block 37, whether the next address delivered by the processor is greater than the highest address of the ROM If this is not the case, the flow is to block 33 decreased and repeated again.

p0027If the last address of the ROM is read out, however, it is checked in block 47 whether the error register is set and the fault counter has been counted from its initial position. If this is not the case, a data word is generated as a character in previously described manner at an output that the test completed and no error has occurred, whereas with a set error register and a further counted error in block 49 to another data word of the output the microcontroller is generated which indicates that the ROM is faulty. In order for the test sequence has been completed.

p0028Instead of the test in block 47 the contents of the error register or the error counter can be discharged to the outside after the block 42 necessarily since its contents directly indicates whether an error has occurred.